JP2000500619A - Ground ring of metal electronic package - Google Patents

Ground ring of metal electronic package

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Publication number
JP2000500619A
JP2000500619A JP9519824A JP51982497A JP2000500619A JP 2000500619 A JP2000500619 A JP 2000500619A JP 9519824 A JP9519824 A JP 9519824A JP 51982497 A JP51982497 A JP 51982497A JP 2000500619 A JP2000500619 A JP 2000500619A
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JP
Japan
Prior art keywords
surface
annular channel
cavity
side wall
metal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9519824A
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Japanese (ja)
Inventor
ホフマン,ポール,アール.
リーブハード,マーカス,ケイ.
Original Assignee
オリン コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US737495P priority Critical
Priority to US60/007,374 priority
Priority to US08/749,259 priority patent/US5764484A/en
Application filed by オリン コーポレイション filed Critical オリン コーポレイション
Priority to PCT/US1996/018479 priority patent/WO1997019470A1/en
Publication of JP2000500619A publication Critical patent/JP2000500619A/en
Application status is Pending legal-status Critical

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Abstract

(57)【要約】 電子パッケージ10の構成要素が、誘電被覆32で表面16を被覆された金属基体12を有する。 (57) Abstract: components of the electronic package 10 has a metal substrate 12 coated surface 16 with a dielectric coating 32. 中央に配置されたキャビティ22は誘電被覆32を通して金属基体12に深さD 1だけ延在する。 Cavity 22 which is centrally located extends a depth D 1 to a metal substrate 12 through the dielectric coating 32. キャビティ22を隣接包囲する環状チャンネル30がD 1よりも小さい深さD 2を有する。 Annular channel 30 adjacent surrounding the cavity 22 has a smaller depth D 2 than D 1. キャビティ22の底面24に結合された半導体装置12は誘電被覆32上に形成された回路トレース34と環状チャンネル30との両方に電気的に相互連結される。 The semiconductor device is coupled to the bottom surface 24 of cavity 22 12 are electrically interconnected to both the circuit traces 34 and the annular channel 30 formed on the dielectric coating 32. 環状チャンネル30を形成する方法は、金属基体14の第1側壁20から所望距離に外側壁60を有すると共に、環状チャンネル30の所望幅より実質的に大きい幅を有する先行環状チャンネル58を機械切削加工する。 A method of forming an annular channel 30, which has an outer wall 60 at a desired distance from the first side wall 20 of the metal substrate 14, mechanically cutting a preceding annular channel 58 having a substantially greater width than the desired width of the annular channel 30 to. 次に、キャビティ22が先行環状チャンネル58の外側壁60で包囲された領域に形成される。 Next, formed in a region where the cavity 22 is surrounded by an outer wall 60 of the prior annular channel 58.

Description

【発明の詳細な説明】 金属電子パッケージ用の接地リング 本発明は接地リングを有する電子パッケージおよびその接地リングの製造方法に関する。 DETAILED DESCRIPTION OF THE INVENTION ground ring present invention for metal electronic package relates to the production method of the electronic package and its grounding ring having a ground ring. 具体的に言えばそのキャビティに隣接してキャビティの限界を定める環状チャンネルが機械切削で金属基体に形成される。 Specifically adjacent its cavity an annular channel delimiting the cavity is formed in the metal substrate at a machining. 金属基体は、シリコンベース半導体チップのような一つ以上の集積回路装置を収容するパッケージの構成要素として広く使用される。 Metal substrate is widely used as a component of the package that houses one or more integrated circuit devices, such as a silicon-based semiconductor chip. 典型的には、金属基体は誘電層を被覆され、この誘電層に回路トレースのパターンが形成される。 Typically, the metal substrate is coated with a dielectric layer, a pattern of circuit traces on the dielectric layer is formed. これらの回路トレースの端部は、一つ以上の半導体装置を含むダイ取付け領域を規定する。 Ends of the circuit traces define a die attach region includes one or more semiconductor devices. これらの装置は細いボンディングワイヤー(接合線)によるなどの方法で回路トレースに対して電気的に相互連結される。 These devices are electrically interconnected with respect to how the circuit traces such as by a thin bonding wire (bonding wire). このような電子パッケージは、スコニック氏他の米国特許第5055967号、およびリン氏他の米国特許第5045921号に開示されている。 Such electronic packages are disclosed Sukonikku said another U.S. Patent No. 5055967, and Lin et al., U.S. Patent No. 5,045,921. スコニック氏他の特許では、基体がアルミニウム合金で、誘電性陽極被膜が被覆されている。 In Sukonikku said other patents, the substrate is an aluminum alloy, a dielectric anodic film is covered. リン氏他の特許では、基体が銅合金であり、誘電性重合体(ポリマー)の層で被覆されている。 In Lynn et al patent, the substrate is a copper alloy, is coated with a layer of a dielectric polymer (polymer). 半導体装置の選択箇所と基体との間に一つ以上の電気的相互連結を形成して、 これらの構成要素の部分を同じ電位にすることがしばしば望まれる。 Forming one or more electrical interconnect between the selected locations and the substrate of the semiconductor device, it is often desirable to portions of these components to the same potential. この目的を達成するために、誘電層部分が金属基体から除去される。 To this end, the dielectric layer portion is removed from the metal substrate. 誘電層のない領域は、 誘電層を化学エッチングするか、誘電層を付与する前に基体をマスキングすることによって形成できる。 Region without dielectric layer, either chemically etching the dielectric layer can be formed by masking the substrate prior to applying the dielectric layer. 共有関係にある米国特許出願では、誘電層部分がエクサイマーレーザーによる切除によって除去される。 In U.S. patent application in the sharing relationship, the dielectric layer portions are removed by ablation by excimer laser. これらの方法は全て満足のゆくものであるが、いずれも一連の複雑な段階を必要とし、これらの段階が電子パッケージ構成要素の費用を高めている。 While these methods are those Yuku of all satisfactory, both require a series of complex steps, these steps to enhance the cost of the electronic package components. それ故に、金属パッケージの構成要素において導電部分を形成する安価な方法の必要性が残されている。 Therefore, a need for an inexpensive method for forming a conductive portion in the component of the metal package is left. 誘電層のない領域は小さく、典型的には誘電層の厚さよりも僅かに大きいだけの深さで、0.051mm(0.002インチ)程度であり、最小幅は0.25 mm(0.010インチ)である。 Region without dielectric layer is small, typically only a depth slightly greater than the thickness of the dielectric layer, a 0.051 mm (0.002 inches) or so, the minimum width of 0.25 mm (0. 010 inches). 誘電層のない領域を形成するために機械的研摩は不可能であると考えられている。 Mechanical polishing in order to form a region having no dielectric layer is believed to be impossible. 所要の限定された幅を形成するために有効な直径を有する機械工具は非常に脆く、頻繁に破損を生じる。 Machine tool having an effective diameter in order to form the required limited width is very brittle, resulting in frequent breakage. 工具先端の半径は誘電層のない領域が傾斜したりワイヤーボンディング(線の接合)に不適切になるほど大きい。 The radius of the tool tip large enough area free of the dielectric layer is unsuitable for tilting or wire bonding (bonding line). かくして、本発明の目的は、低コストおよび狭い公差で形成された誘電層のない電気的相互連結領域を有する電子パッケージ用の構成要素を提供することである。 Thus, an object of the present invention is to provide a component for an electronic package having an electrical interconnect region without dielectric layer formed at a low cost and a narrow tolerance. 本発明の他の目的はこの領域を機械切削加工(milling)によって形成する方法を提供することである。 Another object of the present invention is to provide a method of forming the region by mechanical cutting (milling). 本発明の特徴は、所望幅より大きい幅の予備的な環状チャンネルがパッケージ基体に機械切削加工されることである。 Feature of the present invention is that the preliminary annular channel of greater width than the desired width is mechanically machined to the package substrate. その後、キャビティが基体に機械加工され、その周縁が先行環状チャンネルの外側壁によって境界づけられる。 Thereafter, the cavity is machined into the base body, whose periphery is bounded by the outer wall of the preceding annular channel. このキャビティは先行環状チャンネルの内側壁よりも大きい周面を有し、環状チャンネルの幅を効果的に減少させて所望幅となす。 The cavity has a larger circumference than the inner wall of the preceding annular channel, formed with the desired width effectively reduces the width of the annular channel. この結果として本発明の特徴は、中央に位置するように金属基体に設けられたキャビティ導電性の環状チャンネルによって隣接包囲することである。 The resulting feature of the present invention is to adjoining surrounded by cavity conductive annular channel provided on the metal substrate so as to be located in the center. 本発明の利点の一つは、この環状チャンネルが機械切削加工により低コストで形成され、ワイヤーボンディングに適した概ね平坦な底面を有することである。 One advantage of the present invention, the annular channel is formed at low cost by mechanical cutting, it is to have a generally flat bottom surface suitable for wire bonding. かくして、電子パッケージ用の構成要素が提供される。 Thus, the components of the electronic package is provided. この構成要素は第1側壁によって離隔された第1および第2面を備えた金属基体を有する。 This component has a metal substrate having first and second surfaces spaced apart by a first side wall. 金属基体の第一面は中央に配置されたキャビティを有する。 First surface of the metal substrate having a cavity disposed in the center. このキャビティは底壁と第2側壁とを有する。 The cavity has a bottom wall and a second side wall. 底部の深さはD 1で示される。 The depth of the bottom is indicated by D 1. 環状チャンネルは深さD 2まで金属基体に凹まされ、第2側壁の周縁を境界すると共に隣接する。 Annular channel is recessed in the metal substrate to a depth D 2, adjacent with bounding a periphery of the second side wall. 誘電被覆は第1面の周辺部分を覆っており、環状チャンネルで終端する。 Dielectric coating covers the peripheral portion of the first surface and terminates in an annular channel. この構成要素を製造する二つの方法も提供される。 Two methods for producing this component is also provided. 第一の方法では、第1側壁によって離隔された反対側の第1および第2面を有する金属基体が提供される。 In the first method, a metal substrate having first and second surfaces of the spaced opposite the first side wall is provided. 誘電層は少なくともこの第1面を覆う。 Dielectric layer covering at least the first surface. 先行環状チャンネルが第1面に機械的に切削加工される。 Preceding annular channel is mechanically cutting the first surface. 先行環状チャンネルは、深さD 2を有し、また第1側壁から長さL 1だけ間隔を置く外側壁を有する。 Preceding annular channel has a depth D 2, also has an outer wall to put the length L 1 interval from the first side wall. 環状チャンネルは長さL 2だけ側壁から間隔を隔てられた内側壁をさらに有する。 Annular channel further has an inner wall spaced apart from the side wall by a length L 2. その後、キャビティが外側壁によって包囲されるように機械切削加工される。 Subsequently mechanically cutting such cavity is surrounded by the outer wall. このキャビティは、D 2よりも大きな深さD 1を有する。 The cavity has a depth greater D 1 than D 2. キャビティは、L 2よりも長くL 1よりは短い長さL 3だけ第1側壁から間隔を隔てられた第2側壁を有する。 Cavity has a second sidewall spaced only a short length L 3 apart from the first side wall longer than L 1 than L 2. 第二の方法では、第1側壁で離隔された反対側の第1および第2面と、少なくとも第1面に重なる誘電層とを有する金属基体が提供される。 In the second method, the first and second surface opposite spaced apart first sidewall, a metal substrate having a dielectric layer overlying the at least a first surface is provided. 深さD 2を有するキャビティはこの第1面の中央部分に機械切削加工される。 Cavity having a depth D 2 is mechanically machined in a central portion of the first surface. このキャビティは長さL 3だけ第1側壁から間隔を隔ててられた第2側壁を有する。 The cavity has a second side wall which are not spaced from the first side wall by a length L 3. その後、環状チャンネルが第1面に機械切削加工される。 Thereafter, the annular channel is mechanically machined to the first surface. このチャンネルは第2側壁を隣接包囲し、またD 2よりも小い深さD 1を有する。 This channel is adjacent surrounds the second side wall, and has a small have a depth D 1 than D 2. 上述した目的、特徴および利点はこの明細書および以下の図面から明白となろう。 Above objects, features and advantages will be apparent from the specification and the following drawings. 図1は本発明によるボールグリッド配列電子パッケージを横断面で示す。 Figure 1 shows a ball grid array electronic package according to the invention in cross-section. 図2は本発明による環状チャンネルの拡大図を横断面で示す。 Figure 2 shows an enlarged view of the annular channel according to the invention in cross-section. 図3は従来技術で使用された切削工具を示す。 Figure 3 shows a cutting tool used in the prior art. 図4は本発明の方法により使用された切削工具を示す。 Figure 4 shows a cutting tool used by the method of the present invention. 図5は本発明の一つの方法により形成された環状チャンネルを頂面図で示す。 Figure 5 shows an annular channel formed by one of the methods of the present invention in top view. 図6は本発明の一つの方法により形成された環状チャンネルに隣接する関係で形成されたキャビティを頂面図で示す。 Figure 6 illustrates a cavity formed in relation adjacent to the annular channel formed by one of the methods of the present invention in top view. 図7は本発明の他の方法により形成された機械的に切削加工されたキャビティを頂面図で示す。 Figure 7 shows another mechanically machined cavities formed by the method of the present invention in top view. 図1は一つ以上の半導体装置12を取囲む電子パッケージ10を横断面図で示す。 Figure 1 shows in cross-sectional view of the electronic package 10 surrounding the one or more semiconductor devices 12. 電子パッケージ10の一つの構成要素は金属基体14である。 One of the components of the electronic package 10 is a metal substrate 14. この金属基体14は反対側に位置するほぼ共平面の第1面16および第2面18を有し、これらの面は第1側壁20で離隔されている。 The metal substrate 14 has a first surface 16 and second surface 18 substantially coplanar located opposite, these surfaces are separated by a first side wall 20. キャビティ22が第1面16の中央部分に配置されている。 Cavity 22 is arranged in the center portion of the first surface 16. このキャビティは底面24および第2側壁26を有する。 The cavity has a bottom surface 24 and a second side wall 26. 底面24は第1面16および第2面18 とほぼ共平面である。 Bottom 24 is substantially coplanar with the first surface 16 and second surface 18. 22は第1面16とほぼ同じ高さ位置に半導体装置12の頂面28を位置させる上で有効な深さD 1を有する。 22 has an effective depth D 1 in terms of positioning the top surface 28 of the semiconductor device 12 at substantially the same height as the first surface 16. 典型的には、D 1は約0.3 0mm〜約0.97mm(0.012インチ〜約0.038インチ)の範囲である。 Typically, D 1 is in the range of about 0.3 0 mm to about 0.97 mm (0.012 inches to about 0.038 inches). 環状チャンネル30は第2側壁26を包囲隣接する。 Annular channel 30 adjacent surrounds the second side wall 26. 図1の破線円で示される電子パッケージ10の一部分の拡大図である図2に最も良く見られるように、環状チャンネル30は第1面16より下方に深さD 2ほど凹まされている。 As best seen in FIG. 2 is an enlarged view of a portion of the electronic package 10 shown by a broken line circle in FIG. 1, the annular channel 30 is recessed as the depth D 2 below the first surface 16. 深さD 2 Depth D 2 は深さD 1よりは小さい。 Is smaller than the depth D 1. 誘電被覆32が第1面16の周辺部分を被覆し、環状チャンネル30に隣接して終端している。 Dielectric coating 32 covers the peripheral portion of the first surface 16, and terminates adjacent to the annular channel 30. 図1を見ると、誘電被覆32は典型的には第1側壁20、第1面16の周辺部分、および全てではないとしても第2面18のかなりの部分を被覆する。 Turning to FIG. 1, the dielectric coating 32 is typically first sidewall 20, also covers a significant portion of the second surface 18 as not being peripheral portion of the first surface 16, and all. 典型的には、金属基体14は銅、アルミニウムまたはそれらの合金から選択される。 Typically, the metal substrate 14 is selected from copper, aluminum or their alloys. 金属基体14が銅または銅基合金であるならば、誘電被覆32は典型的にはエポキシのような重合体(ポリマー)とされる。 If the metal substrate 14 is copper or a copper-based alloy, a dielectric coating 32 is typically a polymer such as an epoxy (polymer). 金属基体14がアルミニウムまたはアルミニウム基合金であるならば、誘電被覆は陽極被膜のような酸化アルミニウムとされる。 If the metal substrate 14 is aluminum or an aluminum-based alloy, a dielectric coating is aluminum oxide, such as anode coatings. エポキシである場合、その誘電被覆の厚さは0.013mm(0.0005インチ)程度とされる。 When an epoxy, the thickness of the dielectric coating is a 0.013 mm (0.0005 inches) degree. 陽極被膜の場合、誘電被覆32の厚さは0.025mm( 0.001インチ)程度とされる。 For anodic film, the thickness of the dielectric coating 32 is a 0.025 mm (0.001 inch) degree. 電子パッケージ10はさらに導電性回路トレース(trace)34を含む。 Electronic package 10 further comprises a conductive circuit traces (trace) 34. これらの回路トレースは環状チャンネル30に隣接して終端する第1端部36を有する。 These circuit traces has a first end 36 terminating adjacent to the annular channel 30. 回路トレース34は反対側の第2端部38を有し、この端部は電子パッケージ10の周面に隣接して終端している。 Circuit traces 34 has a second end 38 opposite to the end portion is terminated adjacent the peripheral surface of the electronic package 10. 回路トレース34は積層した銅箔、真空蒸着された銅または他の金属、または誘電被覆32に結合された金属ペーストのようないずれかの導電性材料から形成できる。 Circuit traces 34 may be formed from any conductive material, such as laminated copper foil, vacuum deposited copper or other metal or dielectric coating 32 to bond metal paste. 第2誘電被覆40は第1端部36、および38の一部分42を除いて回路トレース34の選択された部分を被覆している。 The second dielectric coating 40 covers selected portions of the circuit traces 34 except for the portion 42 of the first end 36, and 38. 第1電気的相互連結部44が露出部分42を経て回路トレース34に接続している。 A first electrical interconnect 44 is connected to circuit traces 34 through the exposed portion 42. 第1電気的相互連結部44は導電性エポキシまたは溶融温度の低い鑞材のようないずれかの導電性のボンディング媒体とされ得る。 The first electrical interconnect 44 may be either conductive bonding medium such as a low conductivity epoxy or melting temperature brazing material. 第1電気的相互連結部はボール、柱またはいずれかの望ましい形状を形成するようになされ得る。 The first electrical interconnect ball may be made so as to form a pillar or any desired shape. 0.025mm(0.001インチ)程度の細い直径の金、アルミニウムまたは銅製ワイヤー、またはテープ自動ボンディングに使用される薄い銅箔のような複数の第2電気的相互連結部46が、半導体装置12の第1面28上の入/出力パッドを回路トレース34の第1端部36に電気的に相互連結している。 0.025 mm (0.001 inch) about thin diameter of gold, a plurality of second electrical interconnects 46, such as a thin copper foil used in the aluminum or copper wire or tape automated bonding, the semiconductor device 12 the input / output pads on the first surface 28 of the first end portion 36 of the circuit traces 34 are electrically interconnected. 第2電気的相互連結部46の少なくとも一つは、入/出力パッドを環状チャンネル30 に電気的に相互連結している。 At least one of the second electrical interconnect portion 46, and an input / output pads to electrically interconnect the annular channel 30. 環状チャンネル30に対するワイヤーボンディングを容易にするために、第1面16および底面24とほぼ共平面である環状チャンネルの表面は可能な限り滑らかにされる。 To facilitate wire bonding for annular channel 30, the surface of the annular channel is substantially coplanar with the first surface 16 and bottom surface 24 are as smooth as possible. 2はせいぜい0.18mm(0. 007インチ)である。 D 2 is at most 0.18mm (0. 007 inches). 2は約0.051mm(0.002インチ)〜約0. D 2 is about 0.051mm (0.002 inch) to about 0. 13mm(0.005インチ)の範囲にある。 It is in the range of 13mm (0.005 inches). その後にカバー48が半導体装置12および回路トレース34の第1端部36 を包み込むようにして取付けられる。 Then the cover 48 is attached so as to enclose the first end portion 36 of the semiconductor device 12 and circuit traces 34. カバーは重合体で作られた包囲体、または第2誘電被覆40に結合された個別の金属、重合体またはセラミック構成要素とされ得る。 Cover Individual metal coupled to enclosure or a second dielectric coating 40, made of polymer may be a polymer or a ceramic component. 図2に示すように、環状チャンネル30の幅W 1は、せいぜい0.38mm( 0.015インチ)、好ましくは約0.18mm〜約0.25mm(0.007 インチ〜約0.010インチ)である。 As shown in FIG. 2, the width W 1 of the annular channel 30 is at most 0.38 mm (0.015 inches), preferably about 0.18mm~ about 0.25 mm (0.007 inches to about 0.010 inches) it is. 図3は所望幅の環状チャンネル30を機械加工することのできる従来技術で知られた工具50を示す。 Figure 3 shows the tool 50 as known in the art capable of machining the annular channel 30 of the desired width. この工具はドリルビットまたはエンドミルで構成され、 0.25mm(0.010インチ)の基準直径を有する。 The tool consists of a drill bit or an end mill, having a reference diameter of 0.25 mm (0.010 inch). 直径に対して相対的に長さの長いことは工具50を非常に脆くなし、破損し易くしている。 No very brittle long that the tool 50 relatively long relative to the diameter, are easily broken. さらに、チップ半径部52は環状チャンネル30のかなりの部分に湾曲を与え、ワイヤーボンディングを困難または不可能にしている。 Furthermore, the chip radius portion 52 gives a curved substantial portion of the annular channel 30, making it difficult or impossible to wire bonding. ワイヤーボンディングのために滑らかな表面を与える優れた方法は、図4に示した工具54を使用することである。 Excellent way provide a smooth surface for wire bonding is to use a tool 54 shown in FIG. 工具54は環状チャンネルの所望直径W 1 Tool 54 is desired diameter W 1 of the annular channel の約6倍から約15倍も大きい直径を有する。 Also it has a larger diameter of about 15-fold to about 6-fold. 工具54は環状チャンネルの所望幅の約8倍〜約12倍も大きい直径を有するのが好ましい。 Tool 54 preferably has a also large diameter of about 8 fold to about 12 times the desired width of the annular channel. 直径が工具54の長さに比較してこのように大きいので、この工具54は頑丈で破損しない。 Since such large compared to the length of the tool 54 diameter, the tool 54 is not damaged robust. さらに、直径の大きいことは工具54の先端に非常に鋭い半径部56の形成を容易にする。 Furthermore, larger diameter facilitates very sharp radius portion 56 formed at the tip of the tool 54. 本発明の方法によれば、図5に示す金属基体14は誘電被覆32で被覆された第1面を有する。 According to the method of the present invention, the metal substrate 14 shown in FIG. 5 has a first surface coated with a dielectric coating 32. 予備的チャンネル58が金属基体14の第1面に深さD 2まで機械切削加工され、この深さは最小値でも第1誘電被覆32の厚さより大きく、 下側の金属基体を露出させる。 Preliminary channel 58 is mechanically machined to a depth D 2 to the first surface of the metal substrate 14, the depth is greater than the thickness of the first dielectric coating 32 at a minimum value, to expose the underlying metal substrate. 上述したように、好ましい実施例では、深さD 2 As described above, in the preferred embodiment, the depth D 2 は約0.051mm〜約0.13mm(0.002インチ〜約0.005インチ)である。 Is about 0.051mm~ about 0.13mm (0.002 inches to about 0.005 inches). 先行環状チャンネル58の外側壁60は長さL 1だけ第1側壁20から間隔を置いている。 Prior outer wall 60 of the annular channel 58 is spaced from the first side wall 20 by a length L 1. 先行環状チャンネル58の内側壁62は距離L 2だけ第1 側壁20から間隔を置いている。 Prior inner side wall 62 of the annular channel 58 is spaced from the first side wall 20 by a distance L 2. 図6を見ると、先行環状チャンネルの深さD 2より大きい深さD 1を有するキャビティ22が次に金属基体14の第1面の中央部分に形成される。 Turning to FIG. 6, a cavity 22 having a preceding annular channel depth D 2 is greater than the depth D 1 is then formed in the center portion of the first surface of the metal substrate 14. このキャビティは機械切削加工またはコイニング加工(圧印)のようないずれかの所望される処理方法によって形成できる。 The cavity may be formed by any of the desired processing method such as mechanical cutting or coining (coining). 第2側壁26は、長さL 2より大きく長さL 1より小さい長さL 3だけ第1側壁20から間隔を置いている。 The second side wall 26 is spaced from the first side wall 20 by a length L greater than 2 the length L 1 is less than the length L 3. 3はL 1よりも大半が0.38mm(0.015インチ)小さく、L 1よりも約0.20mm〜約0. L 3 is L majority than 1 0.38 mm (0.015 inch) less, about 0.20mm~ about 0 than L 1. 30mm(0.008インチ〜約0.012インチ)程小さいのが好ましい。 Preferably small enough 30 mm (0.008 inches to about 0.012 inches). この結果、先行環状チャンネルは内側壁から環状チャンネル30の所望幅に等しい位置まで縮小すなわちカットバックされる。 As a result, the prior annular channel is reduced i.e. cutback from the inner wall to a position equal to the desired width of the annular channel 30. 先行環状チャンネル58および第1側壁20の両方が大きい直径で鋭い半径部を有する工具を使用して形成できるので、環状チャンネル30は所望の狭い幅を有し、ワイヤーボンディングに適した滑らかな面も有することになる。 Since a tool having a sharp radius portion both of the preceding annular channel 58 and the first side wall 20 with a large diameter can be formed using, annular channel 30 has a desired narrow width, also smooth surface suitable for wire bonding It will have. 第1誘電被覆32が0.025mm(0.001インチ)の厚さを有する陽極被膜であるならば、本発明による大きな直径の切削加工工具の使用はx方向およびy方向の両方で0.076mm(0.003インチ)よりも小さい欠けを形成すると判断された。 If the first dielectric coating 32 is an anode coating with a thickness of 0.025 mm (0.001 inches), 0.076 mm using a cutting tool of a large diameter according to the present invention in both the x and y directions It is judged (0.003 inch) to form small chipping than. この寸法の欠けはいずれの予測される電子パッケージ設計に関しても公差内にある。 It is within the tolerance with regard missing electronic package design, which is one of the prediction of the size. 本発明の代替方法が図7を参照して示される。 Alternate methods of the present invention is shown with reference to FIG. 所望長さL 3だけ第1側壁20 から間隔を隔てられたキャビティ22が最初に所望の処理方法によって金属基体14に形成され、第1誘電被覆32を通して所望のキャビティ深さD 1に延在される。 Desired length L 3 by the first side wall 20 a cavity 22 which is spaced from the first to be formed on the metal substrate 14 by the desired processing method, extending in the desired cavity depth D 1 through a first dielectric coating 32 that. キャビティ20が形成された後、図6に示す環状チャンネル30がそのキャビティ20の第2側壁26に包囲隣接するように機械切削加工される。 After the cavity 20 is formed an annular channel 30 shown in FIG. 6 is mechanically machined so as to surround adjacent to the second side wall 26 of the cavity 20. 大きな直径で鋭い半径部を有する工具が使用されて、第1面をキャビティ22の深さより浅い深さD 1まで切り込む。 Tool is used with a sharp radius portion with a large diameter, cut a first surface to a shallow depth D 1 than the depth of the cavity 22. 工具の全ては、所望深さまで30を形成するのが必要な部分を除いて、キャビティ20に重なり、金属基体には接触しない。 All tools, except for the necessary parts to form a 30 to a desired depth, overlapping the cavity 20 not contact the metal substrate. 工具の外縁は環状チャンネル30の滑らかな表面を形成するのに有効である。 The outer edge of the tool is effective to form the smooth surface of the annular channel 30. 本発明により、上述の目的、特徴および利点を完全に満たす機械切削加工された環状チャンネルを含んでなる一つ以上の半導体装置を収容するパッケージが提供されたことは明白である。 The present invention, it is apparent that a package which houses the above described objects, features and semiconductor device or one comprising mechanically machined annular channel completely fills the advantages have been provided. 本発明はその特定実施例に関連して説明したが、多くの代替例、変形例、および変化例が前述の説明に照らして当業者に認識されることは明白となろう。 The present invention has been described in connection with specific embodiments thereof, many alternatives, modifications, and that variations may be recognized by those skilled in the art in light of the foregoing description will become apparent. したがって、請求の範囲に記載された精神および広義の範囲内に含まれるそのような全ての代替例、変形例および変化例を包含することが意図される。 Accordingly, all such alternatives contained within has been the spirit and broad scope claimed, to encompass modifications and variations are contemplated.

Claims (1)

  1. 【特許請求の範囲】 1. [Claims] 1. 電子パッケージ(10)の構成要素であって、 第1側壁(20)によって離隔された第1面(16)および(18)を有する金属基体(14)を有し、 前記第1面(16)は内部にキャビティ(22)を有し、前記キャビティ(2 2)は底面(24)および第2側壁(26)を有し、底面(24)および第1面(16)の間の距離がD 1であり、 第1面(16)に深さD 2まで凹まされた環状チャンネル(30)を有し、前記環状チャンネル(30)は前記第2側壁(26)を隣接包囲しており、 前記第1面(16)の周縁部分が前記環状チャンネル(30)で終端していることを特徴とする構成要素。 A component of an electronic package (10), a first surface spaced apart by a first side wall (20) (16) and having a metal substrate (14) having (18), said first surface (16) has a cavity (22) therein, said has a cavity (2 2) is a bottom (24) and a second side wall (26), the distance D between the bottom surface (24) and the first surface (16) 1, the first surface has a depth D 2 (16) recessed annular channel (30), said annular channel (30) is adjacent surrounding said second side wall (26), wherein components peripheral portion of the first surface (16) is characterized in that it terminates in the annular channel (30). 2. 2. 請求の範囲第1項に記載された構成要素であって、深さD 2が0.05 1mmから0.13mmであることを特徴とする構成要素。 A component that is described in claim 1, components depth D 2 is characterized in that it is a 0.13mm from 0.05 1 mm. 3. 3. 請求の範囲第1項または第2項に記載された構成要素であって、前記環状チャンネル(30)の幅W 1が0.18mm〜0.25mmであることを特徴とする構成要素。 A component as described in paragraph 1 or claim 2, components the width W 1 of the annular channel (30) is characterized in that it is a 0.18Mm~0.25Mm. 4. 4. 請求の範囲第3項に記載された構成要素であって、前記金属基体(14 )がアルミニウム合金であり、前記第1誘電被覆(32)が陽極被膜であることを特徴とする構成要素。 A component described in claim 3, wherein the metal substrate (14) is aluminum alloy components, wherein the first dielectric coating (32) is an anode coating. 5. 5. 半導体装置(12)を包み込む電子パッケージ(10)であって、 第1側壁(20)によって離隔された第1面(16)および第2面(18)を有し、前記第1面(16)は内部にキャビティ(22)を有し、前記キャビティ(22)は底面(24)および第2側壁(26)を有し、底面(24)および第1面(16)の間の距離がD 1である金属基体(14)と、 第1面(16)に深さD 2まで凹まされ、前記第2側壁(26)を隣接包囲する環状チャンネル(30)と、 前記第1面(16)の周縁部分、前記第1側壁(20)、および前記第2面( 18)のかなりの部分に重ねられた第1誘電被覆(32)と、 前記第1誘電被覆(32)に重ねて前記第1面(16)上に形成され、前記環状チャンネル(30)で終端する第1端部(3 An electronic package encapsulating a semiconductor device (12) (10), a first surface (16) and the second surface has a (18), the first surface spaced apart by a first side wall (20) (16) has a cavity (22) therein, said cavity (22) has a bottom surface (24) and a second side wall (26), a bottom (24) and the distance between the first surface (16) is D 1 a metal substrate (14) is, recessed to a depth D 2 to the first surface (16), an annular channel (30) adjacent surrounding the second sidewall (26), said first surface (16) peripheral portion, the first side wall (20), and a substantial first dielectric coating superimposed on portion (32), wherein the first dielectric coating (32) to overlap said first of said second surface (18) It is formed on the surface (16), the first end terminating in the annular channel (30) (3 )および前記金属基体(14) の周縁に隣接して終端した第2端部(38)を有する複数の導電性回路トレース(34)と、 前記第2端部(38)に結合された複数の第1電気的相互連結部(44)と、 前記底面(24)に結合された半導体装置(12)と、 前記半導体装置(12)の入/出力部分をそれぞれ前記回路トレース(34) の第1端部(36)および前記環状チャンネル(30)に電気的に相互連結する複数の第2電気的相互連結部(46)とを特徴とする電子パッケージ。 ) And said second end terminating adjacent the peripheral edge of the metal substrate (14) and (plurality of conductive circuit traces having a 38) (34), a plurality of which is coupled to the second end (38) the first electrical interconnect portion (44), wherein the bottom semiconductor device coupled to the (24) (12), the semiconductor device first (12) of the input / output portion of each of the circuit traces (34) electronic package ends (36) and the annular channel second electrical interconnects a plurality of electrically interconnected (30) and (46), characterized. 6. 6. 電子パッケージ(10)の構成要素を製造する方法であって、 第1側壁(20)によって離隔された第1面(16)および第2面(18)を有する金属基体(14)有を準備する段階と、 少なくとも前記第1面(16)に重ねて第1誘電被覆(32)を備える段階と、 前記第1面(16)に先行環状チャンネル(58)を機械切削加工する段階であって、深さD 2と、長さL 1だけ前記第1側壁(20)から間隔を置いた外側壁(60)と、長さL 2だけ前記第1側壁(20)から間隔を置いた内側壁(62 )とを有する先行環状チャンネル(58)を切削加工する段階と、 前記外側壁(60)によって周縁を境界されたキャビティ(22)を形成する段階であって、D 2より大きい深さD 1と、L 2より大きくL 1より小さい長さL 3 A method of producing components of an electronic package (10), a metal substrate (14) having a first surface spaced apart by a first side wall (20) (16) and the second surface (18) to prepare the organic a method, comprising the steps of mechanically cutting the steps comprising a first dielectric coating superimposed on at least the first surface (16) (32), preceding annular channel to said first surface (16) to (58), the depth D 2, the length L 1 by the first side wall (20) spaced from the outer wall (60), the length L 2 by the first side wall (20) spaced from inner walls ( 62) and the steps of cutting a leading annular channel (58) having, a step of forming a cavity (22) which is bounded by the peripheral edge by the outer wall (60), D 2 is greater than the depth D 1 If greater than L 2 L 1 less than the length L 3 だけ前記第1側壁(20)から間隔を置いた第2側壁(26)とを有するキャビティ(30)を形成する段階とを特徴とする方法。 Wherein the step of forming a cavity (30) and a second side wall spaced from only the first side wall (20) (26). 7. 7. 電子パッケージ(10)の構成要素を製造する方法であって、 第1側壁(20)によって離隔された第1面(16)および第2面(18)を有する金属基体(14)有を準備する段階と、 少なくとも前記第1面(16)に重ねて第1誘電被覆(32)を備える段階と、 前記第1面(16)の中央部分に深さD 2のキャビティ(22)を形成する段階であって、長さL 3だけ前記第1側壁(20)から間隔を置いた第2側壁(2 6)を有する前記キャビティ(22)を形成する段階と、 前記第1面(16)に環状チャンネル(30)を機械切削加工する段階であって、前記第2側壁(26)を隣接包囲し、D 2より小さい深さD 1を有する環状チャンネル(30)を機械切削加工する段階とを特徴とする方法。 A method of producing components of an electronic package (10), a metal substrate (14) having a first surface spaced apart by a first side wall (20) (16) and the second surface (18) to prepare the organic forming a step, the step of providing a first dielectric coating superimposed on at least the first surface (16) (32), a cavity (22) of a depth D 2 at the center portion of the first surface (16) a is a step of forming the cavity (22) having a second side wall spaced from the length L 3 of the first side wall (20) (2 6), cyclic to the first surface (16) channel (30) comprising the steps of mechanically cutting, the second side wall (26) adjacent surrounding, wherein the steps of mechanically cutting the annular channel (30) having a D 2 less than the depth D 1 how to with. 8. 8. 請求の範囲第6項または第7項に記載された方法であって、前記環状チャンネル(30)を切削加工する段階がL 3およびL 1の間隔距離よりも6倍から15倍も大きい直径を有する機械切削加工工具(54)を使用することを特徴とする方法。 The method as described in paragraph 6 or Claim 7, a larger diameter 15 times 6 times than the annular channel (30) the spacing distance machining stages is L 3 and L 1 wherein the use of mechanical cutting tool (54) having. 9. 9. 請求の範囲第8項に記載された方法であって、前記環状チャンネル(3 0)が前記第1面(16)から0.18mm(0.007インチ)より小さい深さで機械切削加工されることを特徴とする方法。 The method as described in claim 8, is mechanically machined by 0.18 mm (0.007 inch) less than the depth from the annular channel (3 0) is the first surface (16) wherein the. 10. 10. 請求の範囲第9項に記載された方法であって、前記金属基体(14)が陽極被膜の誘電被覆(32)を被覆されたアルミニウム合金として選択されていることを特徴とする方法。 The method as according to claim 9, wherein said metal substrate (14) is selected as an aluminum alloy coated dielectric covered anode coating (32).
JP9519824A 1995-11-20 1996-11-18 Ground ring of metal electronic package Pending JP2000500619A (en)

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US737495P true 1995-11-20 1995-11-20
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US08/749,259 US5764484A (en) 1996-11-15 1996-11-15 Ground ring for a metal electronic package
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US3819431A (en) * 1971-10-05 1974-06-25 Kulite Semiconductor Products Method of making transducers employing integral protective coatings and supports
JPS6339106B2 (en) * 1982-03-29 1988-08-03 Fujitsu Ltd
US4939316A (en) * 1988-10-05 1990-07-03 Olin Corporation Aluminum alloy semiconductor packages
US5023398A (en) * 1988-10-05 1991-06-11 Olin Corporation Aluminum alloy semiconductor packages
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US6262477B1 (en) * 1993-03-19 2001-07-17 Advanced Interconnect Technologies Ball grid array electronic package
US5353195A (en) * 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
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