JP2000500619A - Ground ring for metal electronic package - Google Patents

Ground ring for metal electronic package

Info

Publication number
JP2000500619A
JP2000500619A JP9519824A JP51982497A JP2000500619A JP 2000500619 A JP2000500619 A JP 2000500619A JP 9519824 A JP9519824 A JP 9519824A JP 51982497 A JP51982497 A JP 51982497A JP 2000500619 A JP2000500619 A JP 2000500619A
Authority
JP
Japan
Prior art keywords
side wall
annular channel
cavity
metal substrate
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9519824A
Other languages
Japanese (ja)
Inventor
ホフマン，ポール，アール．
リーブハード，マーカス，ケイ．
Original Assignee
オリン コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/749,259 external-priority patent/US5764484A/en
Application filed by オリン コーポレイション filed Critical オリン コーポレイション
Publication of JP2000500619A publication Critical patent/JP2000500619A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】 電子パッケージ１０の構成要素が、誘電被覆３２で表面１６を被覆された金属基体１２を有する。中央に配置されたキャビティ２２は誘電被覆３２を通して金属基体１２に深さＤ1だけ延在する。キャビティ２２を隣接包囲する環状チャンネル３０がＤ1よりも小さい深さＤ2を有する。キャビティ２２の底面２４に結合された半導体装置１２は誘電被覆３２上に形成された回路トレース３４と環状チャンネル３０との両方に電気的に相互連結される。環状チャンネル３０を形成する方法は、金属基体１４の第１側壁２０から所望距離に外側壁６０を有すると共に、環状チャンネル３０の所望幅より実質的に大きい幅を有する先行環状チャンネル５８を機械切削加工する。次に、キャビティ２２が先行環状チャンネル５８の外側壁６０で包囲された領域に形成される。 (57) Abstract A component of an electronic package 10 has a metal substrate 12 whose surface 16 is coated with a dielectric coating 32. Cavity 22 which is centrally located extends a depth D 1 to a metal substrate 12 through the dielectric coating 32. Annular channel 30 adjacent surrounding the cavity 22 has a smaller depth D 2 than D 1. Semiconductor device 12 coupled to bottom surface 24 of cavity 22 is electrically interconnected to both circuit traces 34 formed on dielectric coating 32 and to annular channel 30. The method of forming the annular channel 30 includes machining a leading annular channel 58 having an outer wall 60 at a desired distance from the first side wall 20 of the metal substrate 14 and having a width substantially greater than the desired width of the annular channel 30. I do. Next, the cavity 22 is formed in the area surrounded by the outer wall 60 of the leading annular channel 58.

Description

【発明の詳細な説明】 金属電子パッケージ用の接地リング 本発明は接地リングを有する電子パッケージおよびその接地リングの製造方法 に関する。具体的に言えばそのキャビティに隣接してキャビティの限界を定める 環状チャンネルが機械切削で金属基体に形成される。 金属基体は、シリコンベース半導体チップのような一つ以上の集積回路装置を 収容するパッケージの構成要素として広く使用される。典型的には、金属基体は 誘電層を被覆され、この誘電層に回路トレースのパターンが形成される。これら の回路トレースの端部は、一つ以上の半導体装置を含むダイ取付け領域を規定す る。これらの装置は細いボンディングワイヤー（接合線）によるなどの方法で回 路トレースに対して電気的に相互連結される。 このような電子パッケージは、スコニック氏他の米国特許第５０５５９６７号 、およびリン氏他の米国特許第５０４５９２１号に開示されている。スコニック 氏他の特許では、基体がアルミニウム合金で、誘電性陽極被膜が被覆されている 。リン氏他の特許では、基体が銅合金であり、誘電性重合体（ポリマー）の層で 被覆されている。 半導体装置の選択箇所と基体との間に一つ以上の電気的相互連結を形成して、 これらの構成要素の部分を同じ電位にすることがしばしば望まれる。この目的を 達成するために、誘電層部分が金属基体から除去される。誘電層のない領域は、 誘電層を化学エッチングするか、誘電層を付与する前に基体をマスキングするこ とによって形成できる。共有関係にある米国特許出願では、誘電層部分がエクサ イマーレーザーによる切除によって除去される。 これらの方法は全て満足のゆくものであるが、いずれも一連の複雑な段階を必 要とし、これらの段階が電子パッケージ構成要素の費用を高めている。それ故に 、金属パッケージの構成要素において導電部分を形成する安価な方法の必要性が 残されている。 誘電層のない領域は小さく、典型的には誘電層の厚さよりも僅かに大きいだけ の深さで、０．０５１ｍｍ（０．００２インチ）程度であり、最小幅は０．２５ ｍｍ（０．０１０インチ）である。誘電層のない領域を形成するために機械的研 摩は不可能であると考えられている。所要の限定された幅を形成するために有効 な直径を有する機械工具は非常に脆く、頻繁に破損を生じる。工具先端の半径は 誘電層のない領域が傾斜したりワイヤーボンディング（線の接合）に不適切にな るほど大きい。 かくして、本発明の目的は、低コストおよび狭い公差で形成された誘電層のな い電気的相互連結領域を有する電子パッケージ用の構成要素を提供することであ る。本発明の他の目的はこの領域を機械切削加工（milling）によって形成する 方法を提供することである。 本発明の特徴は、所望幅より大きい幅の予備的な環状チャンネルがパッケージ 基体に機械切削加工されることである。その後、キャビティが基体に機械加工さ れ、その周縁が先行環状チャンネルの外側壁によって境界づけられる。このキャ ビティは先行環状チャンネルの内側壁よりも大きい周面を有し、環状チャンネル の幅を効果的に減少させて所望幅となす。 この結果として本発明の特徴は、中央に位置するように金属基体に設けられた キャビティ導電性の環状チャンネルによって隣接包囲することである。 本発明の利点の一つは、この環状チャンネルが機械切削加工により低コストで 形成され、ワイヤーボンディングに適した概ね平坦な底面を有することである。 かくして、電子パッケージ用の構成要素が提供される。この構成要素は第１側 壁によって離隔された第１および第２面を備えた金属基体を有する。金属基体の 第一面は中央に配置されたキャビティを有する。このキャビティは底壁と第２側 壁とを有する。底部の深さはＤ1で示される。環状チャンネルは深さＤ2まで金属 基体に凹まされ、第２側壁の周縁を境界すると共に隣接する。誘電被覆は第１面 の周辺部分を覆っており、環状チャンネルで終端する。 この構成要素を製造する二つの方法も提供される。第一の方法では、第１側壁 によって離隔された反対側の第１および第２面を有する金属基体が提供される。 誘電層は少なくともこの第１面を覆う。先行環状チャンネルが第１面に機械的に 切削加工される。先行環状チャンネルは、深さＤ2を有し、また第１側壁から長 さＬ1だけ間隔を置く外側壁を有する。環状チャンネルは長さＬ2だけ側壁から間 隔を隔てられた内側壁をさらに有する。その後、キャビティが外側壁によって包 囲されるように機械切削加工される。このキャビティは、Ｄ2よりも大きな深さ Ｄ1を有する。キャビティは、Ｌ2よりも長くＬ1よりは短い長さＬ3だけ第１側壁 から間隔を隔てられた第２側壁を有する。 第二の方法では、第１側壁で離隔された反対側の第１および第２面と、少なく とも第１面に重なる誘電層とを有する金属基体が提供される。深さＤ2を有する キャビティはこの第１面の中央部分に機械切削加工される。このキャビティは長 さＬ3だけ第１側壁から間隔を隔ててられた第２側壁を有する。その後、環状チ ャンネルが第１面に機械切削加工される。このチャンネルは第２側壁を隣接包囲 し、またＤ2よりも小い深さＤ1を有する。 上述した目的、特徴および利点はこの明細書および以下の図面から明白となろ う。 図１は本発明によるボールグリッド配列電子パッケージを横断面で示す。 図２は本発明による環状チャンネルの拡大図を横断面で示す。 図３は従来技術で使用された切削工具を示す。 図４は本発明の方法により使用された切削工具を示す。 図５は本発明の一つの方法により形成された環状チャンネルを頂面図で示す。 図６は本発明の一つの方法により形成された環状チャンネルに隣接する関係で 形成されたキャビティを頂面図で示す。 図７は本発明の他の方法により形成された機械的に切削加工されたキャビティ を頂面図で示す。 図１は一つ以上の半導体装置１２を取囲む電子パッケージ１０を横断面図で示 す。電子パッケージ１０の一つの構成要素は金属基体１４である。この金属基体 １４は反対側に位置するほぼ共平面の第１面１６および第２面１８を有し、これ らの面は第１側壁２０で離隔されている。 キャビティ２２が第１面１６の中央部分に配置されている。このキャビティは 底面２４および第２側壁２６を有する。底面２４は第１面１６および第２面１８ とほぼ共平面である。２２は第１面１６とほぼ同じ高さ位置に半導体装置１２の 頂面２８を位置させる上で有効な深さＤ1を有する。典型的には、Ｄ1は約０．３ ０ｍｍ〜約０．９７ｍｍ（０．０１２インチ〜約０．０３８インチ）の範囲であ る。 環状チャンネル３０は第２側壁２６を包囲隣接する。図１の破線円で示される 電子パッケージ１０の一部分の拡大図である図２に最も良く見られるように、環 状チャンネル３０は第１面１６より下方に深さＤ2ほど凹まされている。深さＤ2 は深さＤ1よりは小さい。 誘電被覆３２が第１面１６の周辺部分を被覆し、環状チャンネル３０に隣接し て終端している。 図１を見ると、誘電被覆３２は典型的には第１側壁２０、第１面１６の周辺部 分、および全てではないとしても第２面１８のかなりの部分を被覆する。典型的 には、金属基体１４は銅、アルミニウムまたはそれらの合金から選択される。金 属基体１４が銅または銅基合金であるならば、誘電被覆３２は典型的にはエポキ シのような重合体（ポリマー）とされる。金属基体１４がアルミニウムまたはア ルミニウム基合金であるならば、誘電被覆は陽極被膜のような酸化アルミニウム とされる。 エポキシである場合、その誘電被覆の厚さは０．０１３ｍｍ（０．０００５イ ンチ）程度とされる。陽極被膜の場合、誘電被覆３２の厚さは０．０２５ｍｍ（ ０．００１インチ）程度とされる。 電子パッケージ１０はさらに導電性回路トレース（trace）３４を含む。これ らの回路トレースは環状チャンネル３０に隣接して終端する第１端部３６を有す る。回路トレース３４は反対側の第２端部３８を有し、この端部は電子パッケー ジ１０の周面に隣接して終端している。回路トレース３４は積層した銅箔、真空 蒸着された銅または他の金属、または誘電被覆３２に結合された金属ペーストの ようないずれかの導電性材料から形成できる。 第２誘電被覆４０は第１端部３６、および３８の一部分４２を除いて回路トレ ース３４の選択された部分を被覆している。第１電気的相互連結部４４が露出部 分４２を経て回路トレース３４に接続している。第１電気的相互連結部４４は導 電性エポキシまたは溶融温度の低い鑞材のようないずれかの導電性のボンディン グ媒体とされ得る。第１電気的相互連結部はボール、柱またはいずれかの望まし い形状を形成するようになされ得る。 ０．０２５ｍｍ（０．００１インチ）程度の細い直径の金、アルミニウムまた は銅製ワイヤー、またはテープ自動ボンディングに使用される薄い銅箔のような 複数の第２電気的相互連結部４６が、半導体装置１２の第１面２８上の入／出力 パッドを回路トレース３４の第１端部３６に電気的に相互連結している。第２電 気的相互連結部４６の少なくとも一つは、入／出力パッドを環状チャンネル３０ に電気的に相互連結している。環状チャンネル３０に対するワイヤーボンディン グを容易にするために、第１面１６および底面２４とほぼ共平面である環状チャ ンネルの表面は可能な限り滑らかにされる。Ｄ2はせいぜい０．１８ｍｍ（０． ００７インチ）である。Ｄ2は約０．０５１ｍｍ（０．００２インチ）〜約０． １３ｍｍ（０．００５インチ）の範囲にある。 その後にカバー４８が半導体装置１２および回路トレース３４の第１端部３６ を包み込むようにして取付けられる。カバーは重合体で作られた包囲体、または 第２誘電被覆４０に結合された個別の金属、重合体またはセラミック構成要素と され得る。 図２に示すように、環状チャンネル３０の幅Ｗ1は、せいぜい０．３８ｍｍ（ ０．０１５インチ）、好ましくは約０．１８ｍｍ〜約０．２５ｍｍ（０．００７ インチ〜約０．０１０インチ）である。 図３は所望幅の環状チャンネル３０を機械加工することのできる従来技術で知 られた工具５０を示す。この工具はドリルビットまたはエンドミルで構成され、 ０．２５ｍｍ（０．０１０インチ）の基準直径を有する。直径に対して相対的に 長さの長いことは工具５０を非常に脆くなし、破損し易くしている。さらに、チ ップ半径部５２は環状チャンネル３０のかなりの部分に湾曲を与え、ワイヤーボ ンディングを困難または不可能にしている。 ワイヤーボンディングのために滑らかな表面を与える優れた方法は、図４に示 した工具５４を使用することである。工具５４は環状チャンネルの所望直径Ｗ1 の約６倍から約１５倍も大きい直径を有する。工具５４は環状チャンネルの所望 幅の約８倍〜約１２倍も大きい直径を有するのが好ましい。直径が工具５４の長 さに比較してこのように大きいので、この工具５４は頑丈で破損しない。さらに 、直径の大きいことは工具５４の先端に非常に鋭い半径部５６の形成を容易にす る。 本発明の方法によれば、図５に示す金属基体１４は誘電被覆３２で被覆された 第１面を有する。予備的チャンネル５８が金属基体１４の第１面に深さＤ2まで 機械切削加工され、この深さは最小値でも第１誘電被覆３２の厚さより大きく、 下側の金属基体を露出させる。上述したように、好ましい実施例では、深さＤ2 は約０．０５１ｍｍ〜約０．１３ｍｍ（０．００２インチ〜約０．００５インチ ）である。先行環状チャンネル５８の外側壁６０は長さＬ1だけ第１側壁２０か ら間隔を置いている。先行環状チャンネル５８の内側壁６２は距離Ｌ2だけ第１ 側壁２０から間隔を置いている。 図６を見ると、先行環状チャンネルの深さＤ2より大きい深さＤ1を有するキャ ビティ２２が次に金属基体１４の第１面の中央部分に形成される。このキャビテ ィは機械切削加工またはコイニング加工（圧印）のようないずれかの所望される 処理方法によって形成できる。第２側壁２６は、長さＬ2より大きく長さＬ1より 小さい長さＬ3だけ第１側壁２０から間隔を置いている。Ｌ3はＬ1よりも大半が ０．３８ｍｍ（０．０１５インチ）小さく、Ｌ1よりも約０．２０ｍｍ〜約０． ３０ｍｍ（０．００８インチ〜約０．０１２インチ）程小さいのが好ましい。 この結果、先行環状チャンネルは内側壁から環状チャンネル３０の所望幅に等 しい位置まで縮小すなわちカットバックされる。先行環状チャンネル５８および 第１側壁２０の両方が大きい直径で鋭い半径部を有する工具を使用して形成でき るので、環状チャンネル３０は所望の狭い幅を有し、ワイヤーボンディングに適 した滑らかな面も有することになる。 第１誘電被覆３２が０．０２５ｍｍ（０．００１インチ）の厚さを有する陽極 被膜であるならば、本発明による大きな直径の切削加工工具の使用はｘ方向およ びｙ方向の両方で０．０７６ｍｍ（０．００３インチ）よりも小さい欠けを形成 すると判断された。この寸法の欠けはいずれの予測される電子パッケージ設計に 関しても公差内にある。 本発明の代替方法が図７を参照して示される。所望長さＬ3だけ第１側壁２０ から間隔を隔てられたキャビティ２２が最初に所望の処理方法によって金属基体 １４に形成され、第１誘電被覆３２を通して所望のキャビティ深さＤ1に延在さ れる。キャビティ２０が形成された後、図６に示す環状チャンネル３０がそのキ ャビティ２０の第２側壁２６に包囲隣接するように機械切削加工される。大きな 直径で鋭い半径部を有する工具が使用されて、第１面をキャビティ２２の深さよ り浅い深さＤ1まで切り込む。工具の全ては、所望深さまで３０を形成するのが 必要な部分を除いて、キャビティ２０に重なり、金属基体には接触しない。工具 の外縁は環状チャンネル３０の滑らかな表面を形成するのに有効である。 本発明により、上述の目的、特徴および利点を完全に満たす機械切削加工され た環状チャンネルを含んでなる一つ以上の半導体装置を収容するパッケージが提 供されたことは明白である。本発明はその特定実施例に関連して説明したが、多 くの代替例、変形例、および変化例が前述の説明に照らして当業者に認識される ことは明白となろう。したがって、請求の範囲に記載された精神および広義の範 囲内に含まれるそのような全ての代替例、変形例および変化例を包含することが 意図される。DETAILED DESCRIPTION OF THE INVENTION                     Ground ring for metal electronic package   The present invention relates to an electronic package having a ground ring and a method of manufacturing the ground ring. About. Specifically, define the cavity limits adjacent to the cavity An annular channel is formed in the metal substrate by machining.   Metal substrates provide one or more integrated circuit devices, such as silicon-based semiconductor chips. Widely used as a component of the package to house. Typically, the metal substrate is A dielectric layer is coated, and a pattern of circuit traces is formed on the dielectric layer. these The end of the circuit trace defines a die attach area containing one or more semiconductor devices. You. These devices are turned by a method such as using a thin bonding wire. Electrically interconnected to the road trace.   Such electronic packages are disclosed in U.S. Pat. No. 5,055,967 to Sconic et al. And U.S. Pat. No. 5,045,921 to Lin et al. Sconic In his patent, the substrate is an aluminum alloy with a dielectric anodic coating . In the Lin et al. Patent, the substrate is a copper alloy and is a layer of a dielectric polymer. Coated.   Forming one or more electrical interconnections between selected portions of the semiconductor device and the substrate; It is often desirable to bring these component parts to the same potential. For this purpose To accomplish, the dielectric layer portion is removed from the metal substrate. The area without the dielectric layer Chemically etch the dielectric layer or mask the substrate before applying the dielectric layer. And can be formed by: In a co-owned U.S. patent application, the dielectric It is removed by excision with an immersion laser.   All of these methods are satisfactory, but all require a series of complex steps. In essence, these steps add to the cost of electronic packaging components. Therefore The need for inexpensive methods of forming conductive parts in metal package components Is left.   The area without the dielectric layer is small, typically only slightly larger than the thickness of the dielectric layer The depth is about 0.051 mm (0.002 inch) and the minimum width is 0.25 mm (0.010 inch). Mechanical polishing to form regions without dielectric layers Ma is considered impossible. Effective for forming the required limited width Machine tools with different diameters are very brittle and frequently break. The radius of the tool tip is Areas without a dielectric layer may be tilted or inappropriate for wire bonding. Bigger.   Thus, it is an object of the present invention to provide a dielectric layer formed at low cost and with tight tolerances. To provide components for an electronic package having a large electrical interconnect region. You. Another object of the present invention is to form this area by machining. Is to provide a way.   A feature of the present invention is that a preliminary annular channel with a width greater than the desired width is packaged. That is, the substrate is machined. The cavity is then machined into the substrate And its periphery is bounded by the outer wall of the preceding annular channel. This cap Vity has a larger peripheral surface than the inner wall of the leading annular channel, Is effectively reduced to the desired width.   As a result, the feature of the present invention is that the metal substrate is provided so as to be located at the center. The cavity is to be surrounded by a conductive annular channel.   One of the advantages of the present invention is that the annular channel can be machined at low cost. Formed and have a generally flat bottom surface suitable for wire bonding.   Thus, a component for an electronic package is provided. This component is on the first side A metal substrate having first and second surfaces separated by a wall. Metal substrate The first surface has a centrally located cavity. This cavity is on the bottom wall and the second side With a wall. Bottom depth is D1Indicated by Annular channel has depth DTwoUntil metal It is recessed in the base and borders and adjoins the periphery of the second side wall. Dielectric coating on the first side And terminates in an annular channel.   Two methods of manufacturing this component are also provided. In the first method, the first sidewall A metal substrate having opposing first and second surfaces separated by The dielectric layer covers at least this first surface. Leading annular channel mechanically on the first side It is cut. The leading annular channel has a depth DTwoHaving a length from the first side wall. L1Has outer walls only spaced. The annular channel has length LTwoOnly from the side wall It further has a spaced-apart inner wall. Then the cavity is wrapped by the outer wall Machined to be enclosed. This cavity is DTwoGreater than depth D1Having. The cavity is LTwoL longer than1Shorter length LThreeOnly the first side wall A second sidewall spaced from the second sidewall.   In a second method, opposing first and second surfaces separated by a first sidewall are reduced by at least A metal substrate having a dielectric layer overlapping the first surface. Depth DTwoHaving The cavity is machined in the center of this first surface. This cavity is long LThreeA second side wall spaced only from the first side wall. Then, A channel is machined into the first surface. This channel surrounds the second side wall adjacently And DTwoDepth D smaller than1Having.   The foregoing objects, features and advantages will be apparent from this specification and the following drawings. U.   FIG. 1 shows a ball grid array electronic package according to the present invention in cross section.   FIG. 2 shows an enlarged view of the annular channel according to the invention in cross section.   FIG. 3 shows a cutting tool used in the prior art.   FIG. 4 shows a cutting tool used according to the method of the present invention.   FIG. 5 shows in a top view an annular channel formed by one method of the present invention.   FIG. 6 illustrates the relationship adjacent to an annular channel formed by one method of the present invention. The formed cavity is shown in top view.   FIG. 7 shows a mechanically cut cavity formed by another method of the present invention. Is shown in a top view.   FIG. 1 shows in cross-section an electronic package 10 surrounding one or more semiconductor devices 12. You. One component of the electronic package 10 is a metal substrate 14. This metal substrate 14 has opposing generally coplanar first and second surfaces 16 and 18, These surfaces are separated by a first side wall 20.   A cavity 22 is located at a central portion of the first surface 16. This cavity It has a bottom surface 24 and a second side wall 26. The bottom surface 24 includes the first surface 16 and the second surface 18. Is almost coplanar. Reference numeral 22 denotes a position of the semiconductor device 12 substantially at the same height as the first surface 16. Effective depth D for positioning top surface 281Having. Typically, D1Is about 0.3 0 mm to about 0.97 mm (0.012 inch to about 0.038 inch) You.   An annular channel 30 surrounds and adjoins the second side wall 26. Indicated by the dashed circle in FIG. As best seen in FIG. 2, which is an enlarged view of a portion of the electronic package 10, The channel 30 has a depth D below the first surface 16.TwoIt is so concave. Depth DTwo Is depth D1Less than.   A dielectric coating 32 covers the periphery of the first surface 16 and is adjacent to the annular channel 30. Terminated.   Referring to FIG. 1, the dielectric coating 32 is typically on the first sidewall 20, the periphery of the first surface 16. Covers a minute, and a significant portion, if not all, of the second surface 18. Typical In one embodiment, the metal substrate 14 is selected from copper, aluminum or alloys thereof. Money If the metal substrate 14 is copper or a copper-based alloy, the dielectric coating 32 is typically an epoxy. It is considered to be a polymer (like polymer). The metal base 14 is made of aluminum or aluminum. If it is a luminium-based alloy, the dielectric coating is aluminum oxide, such as an anodic coating. It is said.   If epoxy, the thickness of the dielectric coating is 0.013 mm (0.0005 inch). N). In the case of an anodic coating, the thickness of the dielectric coating 32 is 0.025 mm ( 0.001 inch).   Electronic package 10 further includes conductive circuit traces 34. this These circuit traces have a first end 36 that terminates adjacent to the annular channel 30. You. The circuit trace 34 has an opposite second end 38, which is an electronic package. It terminates adjacent to the peripheral surface of the die 10. Circuit trace 34 is a laminated copper foil, vacuum Of deposited copper or other metal or metal paste bonded to the dielectric coating 32 Such a conductive material can be used.   A second dielectric coating 40 is provided on the circuit trace except for the first end 36 and a portion 42 of the 38. A selected portion of the case 34 is covered. The first electrical interconnect 44 is exposed It is connected to a circuit trace 34 via a minute 42. The first electrical interconnect 44 is Conductive bondin such as conductive epoxy or low melting temperature braze Media. The first electrical interconnect may be a ball, pillar, or any desired Can be made to form different shapes.   0.025 mm (0.001 inch) thin gold, aluminum or Such as copper wire or thin copper foil used for tape automatic bonding A plurality of second electrical interconnects 46 are connected to input / output on first surface 28 of semiconductor device 12. Pads are electrically interconnected to first ends 36 of circuit traces 34. 2nd At least one of the gas interconnects 46 connects the input / output pads to the annular channel 30. Are electrically interconnected. Wire bond to annular channel 30 An annular channel that is substantially coplanar with the first surface 16 and the bottom surface 24 to facilitate The surface of the channel is made as smooth as possible. DTwoAt most 0.18 mm (0. 007 inches). DTwoIs from about 0.051 mm (0.002 inches) to about 0.2 mm. It is in the range of 13 mm (0.005 inches).   Thereafter, cover 48 is connected to semiconductor device 12 and first end 36 of circuit trace 34. It is attached so as to wrap around. The cover is an enclosure made of polymer, or A separate metal, polymer or ceramic component coupled to the second dielectric coating 40; Can be done.   As shown in FIG. 2, the width W of the annular channel 301Is at most 0.38mm ( 0.015 inch), preferably from about 0.18 mm to about 0.25 mm (0.007 inch). Inches to about 0.010 inches).   FIG. 3 is known in the prior art which allows machining of an annular channel 30 of a desired width. Shows the tool 50 that has been used. This tool consists of a drill bit or end mill, It has a reference diameter of 0.25 mm (0.010 inches). Relative to the diameter The long length makes the tool 50 not very brittle and easy to break. In addition, The radius 52 provides a curvature to a substantial portion of the annular channel 30, and Making it difficult or impossible.   An excellent way to provide a smooth surface for wire bonding is shown in FIG. That is, the tool 54 is used. The tool 54 has the desired diameter W of the annular channel.1 It has a diameter that is about 6 to about 15 times larger. Tool 54 can be an annular channel Preferably, it has a diameter that is about 8 to about 12 times the width. The diameter is the length of the tool 54 With such a large size, the tool 54 is robust and does not break. further The large diameter facilitates the formation of a very sharp radius 56 at the tip of the tool 54. You.   According to the method of the present invention, the metal substrate 14 shown in FIG. It has a first surface. The preliminary channel 58 has a depth D on the first surface of the metal substrate 14.TwoUntil Machined, the depth of which is at a minimum even greater than the thickness of the first dielectric coating 32, Exposing the lower metal substrate. As mentioned above, in the preferred embodiment, the depth DTwo Is about 0.051 mm to about 0.13 mm (0.002 inch to about 0.005 inch) ). The outer wall 60 of the leading annular channel 58 has a length L1Only the first side wall 20 Are spaced apart from each other. The inner wall 62 of the leading annular channel 58 has a distance LTwoOnly the first It is spaced from the side wall 20.   Referring to FIG. 6, the depth D of the leading annular channelTwoGreater depth D1With the Vitities 22 are then formed in the central portion of the first surface of metal substrate 14. This cavite Can be any desired such as machining or coining It can be formed by a processing method. The second side wall 26 has a length LTwoLarger length L1Than Small length LThreeOnly from the first side wall 20. LThreeIs L1More than most 0.38mm (0.015 inch) small, L1About 0.20 mm to about 0.2 mm. Preferably, it is as small as 30 mm (0.008 inches to about 0.012 inches).   As a result, the leading annular channel is equal to the desired width of the annular channel 30 from the inner wall. It is reduced or cut back to a new position. Leading annular channel 58 and Both first side walls 20 can be formed using a tool having a large diameter and a sharp radius. Therefore, the annular channel 30 has a desired narrow width and is suitable for wire bonding. It also has a smooth surface.   Anode wherein the first dielectric coating 32 has a thickness of 0.025 mm (0.001 inch) If it is a coating, the use of a large diameter cutting tool according to the invention can be applied in the x direction and Chips smaller than 0.076 mm (0.003 inch) in both the y and y directions It was determined that. This lack of dimensions is a factor in any expected electronic package design. Also within tolerance.   An alternative method of the present invention is shown with reference to FIG. Desired length LThreeOnly the first side wall 20 A cavity 22 spaced from a metal substrate is first formed by a desired processing method. 14 and through the first dielectric coating 32 the desired cavity depth D1Extended to It is. After the cavity 20 has been formed, the annular channel 30 shown in FIG. Machine cutting is performed so as to surround and be adjacent to the second side wall 26 of the cavity 20. big A tool having a sharp radius and a diameter is used to reduce the first surface to the depth of the cavity 22. Shallower depth D1Cut into it. All of the tools should form 30 to the desired depth Except for the necessary part, it overlaps the cavity 20 and does not contact the metal substrate. tool Is effective to form a smooth surface of the annular channel 30.   In accordance with the present invention, a machined and machined product that fully meets the objects, features and advantages set forth above. A package containing one or more semiconductor devices comprising an annular channel is provided. It is clear that they have been offered. Although the invention has been described with reference to specific embodiments thereof, Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. That will be clear. Therefore, the spirit and broad scope defined in the claims It is intended that all such alternatives, modifications and variations included within the box be included. Intended.

Claims (1)

【特許請求の範囲】 １． 電子パッケージ（１０）の構成要素であって、 第１側壁（２０）によって離隔された第１面（１６）および（１８）を有する 金属基体（１４）を有し、 前記第１面（１６）は内部にキャビティ（２２）を有し、前記キャビティ（２ ２）は底面（２４）および第２側壁（２６）を有し、底面（２４）および第１面 （１６）の間の距離がＤ1であり、 第１面（１６）に深さＤ2まで凹まされた環状チャンネル（３０）を有し、前 記環状チャンネル（３０）は前記第２側壁（２６）を隣接包囲しており、 前記第１面（１６）の周縁部分が前記環状チャンネル（３０）で終端している ことを特徴とする構成要素。 ２． 請求の範囲第１項に記載された構成要素であって、深さＤ2が０．０５ １ｍｍから０．１３ｍｍであることを特徴とする構成要素。 ３． 請求の範囲第１項または第２項に記載された構成要素であって、前記環 状チャンネル（３０）の幅Ｗ1が０．１８ｍｍ〜０．２５ｍｍであることを特徴 とする構成要素。 ４． 請求の範囲第３項に記載された構成要素であって、前記金属基体（１４ ）がアルミニウム合金であり、前記第１誘電被覆（３２）が陽極被膜であること を特徴とする構成要素。 ５． 半導体装置（１２）を包み込む電子パッケージ（１０）であって、 第１側壁（２０）によって離隔された第１面（１６）および第２面（１８）を 有し、前記第１面（１６）は内部にキャビティ（２２）を有し、前記キャビティ （２２）は底面（２４）および第２側壁（２６）を有し、底面（２４）および第 １面（１６）の間の距離がＤ1である金属基体（１４）と、 第１面（１６）に深さＤ2まで凹まされ、前記第２側壁（２６）を隣接包囲す る環状チャンネル（３０）と、 前記第１面（１６）の周縁部分、前記第１側壁（２０）、および前記第２面（ １８）のかなりの部分に重ねられた第１誘電被覆（３２）と、 前記第１誘電被覆（３２）に重ねて前記第１面（１６）上に形成され、前記環 状チャンネル（３０）で終端する第１端部（３６）および前記金属基体（１４） の周縁に隣接して終端した第２端部（３８）を有する複数の導電性回路トレース （３４）と、 前記第２端部（３８）に結合された複数の第１電気的相互連結部（４４）と、 前記底面（２４）に結合された半導体装置（１２）と、 前記半導体装置（１２）の入／出力部分をそれぞれ前記回路トレース（３４） の第１端部（３６）および前記環状チャンネル（３０）に電気的に相互連結する 複数の第２電気的相互連結部（４６）とを特徴とする電子パッケージ。 ６． 電子パッケージ（１０）の構成要素を製造する方法であって、 第１側壁（２０）によって離隔された第１面（１６）および第２面（１８）を 有する金属基体（１４）有を準備する段階と、 少なくとも前記第１面（１６）に重ねて第１誘電被覆（３２）を備える段階と 、 前記第１面（１６）に先行環状チャンネル（５８）を機械切削加工する段階で あって、深さＤ2と、長さＬ1だけ前記第１側壁（２０）から間隔を置いた外側壁 （６０）と、長さＬ2だけ前記第１側壁（２０）から間隔を置いた内側壁（６２ ）とを有する先行環状チャンネル（５８）を切削加工する段階と、 前記外側壁（６０）によって周縁を境界されたキャビティ（２２）を形成する 段階であって、Ｄ2より大きい深さＤ1と、Ｌ2より大きくＬ1より小さい長さＬ3 だけ前記第１側壁（２０）から間隔を置いた第２側壁（２６）とを有するキャビ ティ（３０）を形成する段階とを特徴とする方法。 ７． 電子パッケージ（１０）の構成要素を製造する方法であって、 第１側壁（２０）によって離隔された第１面（１６）および第２面（１８）を 有する金属基体（１４）有を準備する段階と、 少なくとも前記第１面（１６）に重ねて第１誘電被覆（３２）を備える段階と 、 前記第１面（１６）の中央部分に深さＤ2のキャビティ（２２）を形成する段 階であって、長さＬ3だけ前記第１側壁（２０）から間隔を置いた第２側壁（２ ６）を有する前記キャビティ（２２）を形成する段階と、 前記第１面（１６）に環状チャンネル（３０）を機械切削加工する段階であっ て、前記第２側壁（２６）を隣接包囲し、Ｄ2より小さい深さＤ1を有する環状チ ャンネル（３０）を機械切削加工する段階とを特徴とする方法。 ８． 請求の範囲第６項または第７項に記載された方法であって、前記環状チ ャンネル（３０）を切削加工する段階がＬ3およびＬ1の間隔距離よりも６倍から １５倍も大きい直径を有する機械切削加工工具（５４）を使用することを特徴と する方法。 ９． 請求の範囲第８項に記載された方法であって、前記環状チャンネル（３ ０）が前記第１面（１６）から０．１８ｍｍ（０．００７インチ）より小さい深 さで機械切削加工されることを特徴とする方法。 １０． 請求の範囲第９項に記載された方法であって、前記金属基体（１４）が 陽極被膜の誘電被覆（３２）を被覆されたアルミニウム合金として選択されてい ることを特徴とする方法。[Claims]   1. A component of the electronic package (10),   Has first surfaces (16) and (18) separated by a first side wall (20) A metal substrate (14);   The first surface (16) has a cavity (22) therein, and the cavity (2) 2) has a bottom surface (24) and a second side wall (26), the bottom surface (24) and the first surface The distance between (16) is D1And   Depth D on the first surface (16)TwoWith an annular channel (30) recessed to the front Said annular channel (30) surrounds said second side wall (26) adjacently;   A peripheral portion of the first surface (16) terminates in the annular channel (30). A constituent element characterized in that:   2. A component as claimed in claim 1, wherein the depth DTwoIs 0.05 A component characterized by being 1 mm to 0.13 mm.   3. A component according to claim 1 or 2, wherein the ring is Width W of the shape channel (30)1Is 0.18 mm to 0.25 mm Component to be used.   4. 4. A component according to claim 3, wherein said metal substrate (14) is provided. ) Is an aluminum alloy, and the first dielectric coating (32) is an anode coating. Component characterized by the following.   5. An electronic package (10) enclosing a semiconductor device (12),   A first side (16) and a second side (18) separated by a first side wall (20); Wherein the first surface (16) has a cavity (22) therein; (22) has a bottom surface (24) and a second side wall (26); The distance between one surface (16) is D1A metal substrate (14),   Depth D on the first surface (16)TwoRecessed to surround the second side wall (26) adjacently An annular channel (30);   A peripheral portion of the first surface (16), the first side wall (20), and the second surface ( 18) a first dielectric coating (32) over a substantial portion of   The ring formed on the first surface (16) overlying the first dielectric coating (32); A first end (36) terminating in a toroidal channel (30) and said metal substrate (14) Conductive circuit traces having a second end (38) terminated adjacent the periphery of (34),   A plurality of first electrical interconnects (44) coupled to the second end (38);   A semiconductor device (12) coupled to said bottom surface (24);   The input / output portion of the semiconductor device (12) is connected to the circuit trace (34), respectively. Electrically interconnects with a first end (36) of the first and said annular channel (30). An electronic package comprising a plurality of second electrical interconnects (46).   6. A method of manufacturing a component of an electronic package (10), comprising:   A first side (16) and a second side (18) separated by a first side wall (20); Preparing a metal substrate (14) having;   Providing a first dielectric coating (32) at least over the first surface (16); ,   Machining the leading annular channel (58) on the first surface (16); And depth DTwoAnd the length L1Outer wall only spaced from said first side wall (20) (60) and length LTwoInner wall (62) spaced from the first side wall (20) only. Cutting the leading annular channel (58) comprising:   Forming a cavity (22) bounded by the outer wall (60) Stage, DTwoGreater depth D1And LTwoGreater than L1Smaller length LThree A second side wall (26) spaced only from said first side wall (20). Forming a tee (30).   7. A method of manufacturing a component of an electronic package (10), comprising:   A first side (16) and a second side (18) separated by a first side wall (20); Preparing a metal substrate (14) having;   Providing a first dielectric coating (32) over at least the first surface (16); ,   The central portion of the first surface (16) has a depth DTwoOf forming the cavity (22) Floor, length LThreeA second side wall (2) spaced from the first side wall (20) only Forming said cavity (22) having 6);   Machining the annular channel (30) on the first surface (16). And surrounding the second side wall (26) adjacently,TwoSmaller depth D1Ring Machining the channel (30).   8. A method as claimed in claim 6 or claim 7, wherein said annular zipper is provided. The step of cutting the channel (30) is LThreeAnd L16 times longer than the distance Characterized by using a machining tool (54) having a diameter as large as 15 times. how to.   9. 9. The method according to claim 8, wherein the annular channel (3) is provided. 0) is less than 0.18 mm (0.007 inch) deep from the first surface (16) A method characterized by being machine-cut with the above. 10. 10. The method according to claim 9, wherein said metal substrate (14) is The dielectric coating (32) of the anodic coating has been selected as the coated aluminum alloy. A method comprising:
JP9519824A 1995-11-20 1996-11-18 Ground ring for metal electronic package Pending JP2000500619A (en)

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US737495P 1995-11-20 1995-11-20
US60/007,374 1995-11-20
US08/749,259 US5764484A (en) 1996-11-15 1996-11-15 Ground ring for a metal electronic package
PCT/US1996/018479 WO1997019470A1 (en) 1995-11-20 1996-11-18 Ground ring for metal electronic package

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JP2018006408A (en) * 2016-06-28 2018-01-11 株式会社ジェイデバイス Semiconductor package and manufacturing method thereof

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EP0956589A1 (en) 1999-11-17
WO1997019470A1 (en) 1997-05-29

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