CN210467806U - Semiconductor package assembly with convex micro pins - Google Patents
Semiconductor package assembly with convex micro pins Download PDFInfo
- Publication number
- CN210467806U CN210467806U CN201922010215.2U CN201922010215U CN210467806U CN 210467806 U CN210467806 U CN 210467806U CN 201922010215 U CN201922010215 U CN 201922010215U CN 210467806 U CN210467806 U CN 210467806U
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- CN
- China
- Prior art keywords
- adhesive layer
- semiconductor package
- lead frame
- pins
- package assembly
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The semiconductor packaging assembly with the convex miniature pins comprises a lead frame unit, a semiconductor unit arranged on the lead frame unit and a packaging adhesive layer covering the semiconductor unit and the lead frame unit, and particularly, the pins of the lead frame unit can protrude to the packaging adhesive layer, each pin is provided with a concave hole which is formed by sinking the bottom surface of an extending part of the pin to the top surface direction of the pin and extends to penetrate through the outer peripheral surface adjacent to the bottom surface.
Description
Technical Field
The present invention relates to a semiconductor package assembly, and more particularly to a semiconductor package assembly with an outwardly protruding micro pin.
Background
Referring to fig. 1, fig. 1 is a conventional semiconductor package structure with protruding micro leads (micro) and includes a lead frame unit 11, a package adhesive layer 12, and a semiconductor device (not shown) disposed on the lead frame unit 11 and encapsulated by the package adhesive layer 12. The lead frame unit 11 has a die pad 111 for carrying the semiconductor device, and a plurality of leads 112 surrounding the die pad 111 and spaced apart from the die pad 111 by a gap, wherein the leads 112 protrude from the package adhesive layer 12. However, since the bottom surfaces 113 of the pins 112 protruding outward are planar, when this semiconductor package structure is to be applied to subsequent soldering with other circuit boards, it is generally difficult for the solder used for soldering to climb up from the bottom surfaces 113 of the pins 112 to the side surfaces of the pins 112 via reflow (reflow). Since the mechanical strength of the connection between the semiconductor package and the other circuit board is greatly related to the contact area between the solder and the leads 112, and when the solder cannot be exposed from the side surfaces of the leads 112, the soldering condition between the leads 112 and the solder cannot be directly detected from the appearance detection during the manufacturing process, thereby increasing the difficulty of the detection.
Disclosure of Invention
An object of the utility model is to provide a can promote soldering tin and climb, and change in the semiconductor package subassembly that has the miniature pin of evagination that detects the pin solder.
The utility model discloses semiconductor packaging subassembly with miniature pin of evagination contains lead frame unit, semiconductor unit, and encapsulation glue film.
The lead frame unit is provided with a chip seat, a plurality of pins arranged on the periphery of the chip seat and a plurality of concave holes, wherein the chip seat is provided with a bottom surface and a top surface which are opposite to each other, each pin is provided with a main body part adjacent to the chip seat and an extending part extending from the main body part towards the direction far away from the chip seat, the main body part and the extending part are respectively provided with a bottom surface and a top surface which are opposite to each other, the extending part is also provided with a top surface and a bottom surface which are connected with the extending part and an outer peripheral surface which is far away from the chip seat, the concave holes are respectively formed on the pins, and each concave hole is formed by sinking from the bottom surface of the corresponding extending part of the pin to the top.
The semiconductor unit is provided with a semiconductor chip arranged on the top surface of the chip seat and a plurality of leads which can respectively electrically connect the semiconductor chip and the pins.
The packaging adhesive layer covers the semiconductor unit and the lead frame unit, the extending part of the lead frame unit extends out of the packaging adhesive layer, and the bottom surfaces of the chip holder, the pins and the packaging adhesive layer are coplanar with each other.
Preferably, the utility model discloses semiconductor package subassembly with miniature pin of evagination, wherein, the orthographic projection of each shrinkage pool with the orthographic projection part of encapsulation glue film overlaps.
Preferably, the semiconductor package assembly with protruding micro pins of the present invention further comprises a plurality of concave holes, wherein each concave hole is formed from the bottom surface of the main body portion adjacent to the extension portion and the bottom surface of the extension portion to the top surface of the main body portion adjacent to the extension portion and extends to the outer peripheral surface adjacent to the bottom surface of the extension portion.
Preferably, the utility model discloses semiconductor package subassembly with miniature pin of evagination, wherein, the footpath width of each shrinkage pool is less than the width of the outer peripheral face of corresponding pin, and the degree of depth of each shrinkage pool is less than the height of this pin.
Preferably, the semiconductor package assembly with the protruding micro pins of the present invention has a distance between the outer peripheral surface and the package adhesive layer ranging from 0.05mm to 0.3 mm.
Preferably, the semiconductor package assembly with the protruding micro-pins of the present invention further includes a sealing member disposed between the first and second lead frame units.
Preferably, the semiconductor package assembly with the protruded micro pins of the present invention further comprises a top surface of the encapsulation adhesive layer, wherein the top surface of the encapsulation adhesive layer is a quadrilateral, each corner of the quadrilateral is an arc, and the surface area of the top surface of the encapsulation adhesive layer is gradually increased toward the direction of the lead frame unit.
The beneficial effects of the utility model reside in that: by using the structural design of the lead frame unit, concave holes extending to the peripheral surfaces of the pins are formed on the bottom surfaces of the pins of the lead frame unit, so that when the semiconductor packaging assembly packaged by using the lead frame unit is electrically connected with other circuit boards by virtue of soldering tin, the degree of tin climbing can be increased by virtue of the concave holes, the contact area between the soldering tin and the pins is increased, the visible area can be increased by virtue of the peripheral surfaces, and the visual detection is easier.
Drawings
Other features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings, in which:
FIG. 1 is a perspective view illustrating a conventional semiconductor package structure with protruding micro-pins;
FIG. 2 is a schematic perspective view illustrating an embodiment of a semiconductor package structure with protruding micro pins according to the present invention;
fig. 3 is a perspective view illustrating an embodiment of the present invention from another perspective;
FIG. 4 is a cross-sectional view taken along section line 4-4 of FIG. 3;
FIG. 5 is a schematic diagram illustrating a manufacturing process of the embodiment of the present invention; and
fig. 6 is a schematic view illustrating a manufacturing process of the embodiment of the present invention.
Detailed Description
Referring to fig. 2 to 4, fig. 2 and 3 are schematic perspective views of a semiconductor package assembly with protruding micro pins according to an embodiment of the present invention at different viewing angles, and fig. 4 is a sectional view of a section line 4-4 in fig. 3.
The embodiment includes a lead frame unit 2, a semiconductor unit 3, and an encapsulant layer 4.
The lead frame unit 2 has a die pad 21 for carrying a semiconductor chip, a plurality of leads 22 disposed on the periphery of the die pad 21, and a plurality of recesses 25.
The chip holder 21 is made of a conductive material such as: copper-based alloy or iron-nickel alloy, etc., having a bottom surface 211 and a top surface 212 opposite to each other.
The leads 22 are made of the same conductive material as the die pad 21. Each lead 22 has a main portion 23 adjacent to the die pad 21 and an extending portion 24 extending from the main portion 23 in a direction away from the die pad 21.
The main body 23 and the extension 24 have a bottom surface 231, 241 and a top surface 232, 242 opposite to each other, respectively, and the extension 24 further has an outer peripheral surface 243 connecting the top surface 242 and the bottom surface 241 of the extension 24 and being away from the die pad 21. The top surface 232 of the main body 23 and the top surface 242 of the extension 24 together form the top surface 222 of the corresponding lead 22, the bottom surface 231 of the main body 23 and the bottom surface 241 of the extension 24 together form the bottom surface 221 of the corresponding lead 22, and the outer peripheral surface 243 is the surface of the lead 22 farthest from the die pad 21.
The concave hole 25 is formed in the pin 22. Each concave hole 25 is correspondingly formed on one lead 22, and is at least formed by being recessed from the bottom surface 241 of the extension portion 24 of the corresponding lead 22 toward the top surface 242 of the extension portion 24, and extends through to the outer peripheral surface 243 adjacent to the bottom surface 241 of the extension portion 24.
The shape of the concave hole 25 may be a semicircular shape with a uniform diameter and width, or a curved surface with a non-uniform diameter and width, or an asymmetric shape, and the shape is not particularly limited as long as the concave hole 25 can extend from the bottom surface 221 of the lead 22 to the adjacent outer circumferential surface 243. In the present embodiment, the concave holes 25 are semicircular holes having a uniform diameter width W1, and each concave hole 25 extends from the bottom surface 231 of the main body 23 adjacent to the extension portion 24 to penetrate through to the outer peripheral surface 243.
The semiconductor unit 3 has a semiconductor chip 31 disposed on the top surface 212 of the die pad 21, and a plurality of wires 32 for electrically connecting the semiconductor chip 31 and the leads 22, respectively.
The packaging adhesive layer 4 may be made of transparent or opaque insulating material, and covers the semiconductor unit 3 and the leadframe unit 2 (i.e. covers the die pad 21 and the main body portions 23 of the leads 22), and the extending portions 24 of the leads 22 protrude outward from the packaging adhesive layer 4, and the concave holes 25 are not filled in the packaging adhesive layer 4.
The packaging adhesive layer 4 has a bottom surface 41 in the same direction as the bottom surface 211 of the die pad 21. The bottom surface 211 of the die pad 21, the bottom surfaces 231 of the main portions 23 of the leads 22 and the bottom surface 241 of the extension portion 24 are exposed from the encapsulant layer 4, and the bottom surfaces 211 of the die pad 21, the bottom surfaces 221 of the leads 22 and the bottom surface 41 of the encapsulant layer 4 are coplanar with each other. In the present embodiment, the encapsulant layer 4 is an opaque insulating material, but the practical embodiment is not limited thereto.
The cross section of the packaging adhesive layer 4 is quadrilateral, each corner of the quadrilateral is arc-shaped, and the surface area of the cross section increases gradually from the top surface of the packaging adhesive layer 4 to the direction of the lead frame unit 2.
In some embodiments, the concave hole 25 is formed in the extending portion 24, and the encapsulating adhesive layer 4 further extends to cover a portion of the extending portion 24 of the lead 22. Therefore, the orthographic projection of the concave hole 25 and the orthographic projection of the packaging glue layer 4 are partially overlapped.
In addition, in some embodiments, in order to increase the contact area between the solder and the concave hole 25 in the subsequent soldering process, the concave hole 25 may also extend from a portion of the main body portion 23 to the extension portion 24 and penetrate the outer peripheral surface 243. At this time, no matter whether the packaging adhesive layer 4 has the extending portion 24 extending to partially cover, the orthographic projection of the concave hole 25 and the orthographic projection of the packaging adhesive layer 4 are partially overlapped.
In some embodiments, in order not to affect the package size of the semiconductor package assembly, each of the leads 22 protrudes to the extension portion 24 outside the package adhesive layer 4, and the distance S from the outer peripheral surface 243 to the edge of the package adhesive layer 4 is between 0.05mm and 0.3 mm.
In other embodiments, in order to prevent the concave holes 25 from affecting the strength of the leads 22, the diameter width W1 of each concave hole 25 is smaller than the width W2 of the outer peripheral surface 243 of the lead 22, and the depth D of each concave hole 25 is smaller than the height H of the lead 22.
It should be noted that, in some embodiments, the exposed surface of the lead frame unit 2 may further have one or more conductive layers (not shown), and the conductive layer may be selected from metals or alloys, such as nickel, palladium, silver, or gold. The conductive coating can improve the adhesion between the lead frame unit 2 and the leads 32 or between the lead frame unit 2 and the packaging adhesive layer 4, thereby improving the reliability of the semiconductor package assembly. In addition, the conductive plating layer can also assist the wettability of the solder and the leads 22, so that the solder can easily climb from the exposed surfaces of the leads 22 from the concave holes 25, the contact area of the semiconductor packaging component and the solder can be enhanced, the climbing degree of the solder is increased, and the welding condition can be easily visually detected from the outer peripheral surface 243 of the semiconductor packaging component.
The manufacturing method of the above embodiment will be specifically described below.
Referring to fig. 4 and 5, the semiconductor package assembly with protruding micro-pins according to the present invention is prepared by providing a substrate 900 made of conductive material, such as copper alloy or iron-nickel alloy.
Then, a first etching process is performed to etch and remove unnecessary portions of the substrate 900, so as to form a plurality of leadframe units 2 and a plurality of connecting channels 901 for separating the leadframe units 2 on the substrate 900. The lead frame units 2 are distributed in several groups, each lead frame unit 2 has a chip carrier 21 located at the center, and a plurality of leads 22 extending from the connecting channel 901 toward the chip carrier 21 and spaced apart from each other.
Then, a second etching is performed to form concave holes 25 on the leads 22.
Specifically, the step is to etch downward from the bottom 221 of the leads 22 by etching, so as to form a strip-shaped groove 25 'extending along the length direction of the lead 22 in each lead 22, and the diameter W1 and the depth D of the groove 25' are respectively smaller than the width W2 and the height H of the lead 22.
Then, referring to fig. 6, the semiconductor chips 31 are respectively disposed on the top surfaces 212 of the die pads 21, and the semiconductor chips 31 and the leads 22 are electrically connected by wires 32 by a wire bonding process, so as to obtain a semi-formed product.
Then, the semi-formed product is clamped in a mold (not shown), and a molding compound is injected by molding, the molding compound covers the semiconductor chip 31, the leads 22 and the lead frame unit 2, but does not cover the extending portions 24 of the leads 22, the bottom surface 211 of the die pad 21 and the bottom surfaces 221 of the leads 22, and is not filled in the grooves 25', so that after the molding compound is cured, a plurality of mutually separated packaging compound layers 4 corresponding to each lead frame unit 2 can be formed, and a packaging semi-finished product with a plurality of packaging units 902 can be obtained.
Then, along the cutting lines (as shown by the phantom lines in fig. 6), the semiconductor package assembly shown in fig. 3 is obtained by cutting from the positions corresponding to the exposed leads 22 of each package unit 902 and at a distance from the package adhesive layer 4.
To sum up, the utility model discloses this semiconductor package subassembly with miniature pin of evagination borrows and corresponds formation shrinkage pool 25 by the pin 22 in this lead frame unit 2, consequently, utilizes the semiconductor package subassembly that this lead frame unit 2 encapsulation obtained when carrying out subsequent soldering tin processing procedure, can borrow the height that tin was climbed by shrinkage pool 25 increase, promotes solder and pin 22's area of contact to outer peripheral face (side) 243 of accessible pin 22 increases the visible area, and changes in visual detection, so can reach the purpose of the utility model really.
The above description is only an example of the present invention, and the scope of the present invention should not be limited thereby, and all the simple equivalent changes and modifications made according to the claims and the contents of the specification should be included in the scope of the present invention.
Claims (7)
1. A semiconductor package assembly having raised micro pins, comprising: which comprises the following steps:
the lead frame unit is provided with a chip seat, a plurality of pins arranged on the periphery of the chip seat and a plurality of concave holes, wherein the chip seat is provided with a bottom surface and a top surface which are opposite to each other, each pin is provided with a main body part adjacent to the chip seat and an extension part extending from the main body part to the direction far away from the chip seat, the main body part and the extension part are respectively provided with a bottom surface and a top surface which are opposite to each other, the extension part is also provided with a top surface and a bottom surface which are connected with the extension part and a peripheral surface far away from the chip seat, the concave holes are respectively formed on the pins, and each concave hole is formed by sinking from the bottom surface of the extension part of the corresponding pin to the top surface of the;
a semiconductor unit having a semiconductor chip disposed on the top surface of the die pad and a plurality of wires for electrically connecting the semiconductor chip and the leads, respectively; and
and the packaging adhesive layer covers the semiconductor unit and the lead frame unit, the extending part of the lead frame unit extends out of the packaging adhesive layer, and the bottom surfaces of the chip holder, the pins and the packaging adhesive layer are coplanar with each other.
2. The semiconductor package assembly with protruding micro pins of claim 1, wherein: the orthographic projection of each concave hole is partially overlapped with the orthographic projection of the packaging adhesive layer.
3. The semiconductor package assembly with protruding micro pins of claim 2, wherein: each concave hole is formed by sinking from the bottom surface of the main body part adjacent to the extension part and the bottom surface of the extension part to the top surface of the main body part and the extension part and extends to penetrate through the outer peripheral surface adjacent to the bottom surface of the extension part.
4. The semiconductor package assembly with protruding micro pins of claim 1, wherein: the diameter width of each concave hole is smaller than the width of the peripheral surface of the corresponding pin, and the depth of each concave hole is smaller than the height of the pin.
5. The semiconductor package assembly with protruding micro pins of claim 1, wherein: the distance between the peripheral surface and the packaging adhesive layer is 0.05 mm-0.3 mm.
6. The semiconductor package assembly with protruding micro pins of claim 1, wherein: the surface of the packaging adhesive layer and the surface of the adjacent lead frame unit jointly define an obtuse angle.
7. The semiconductor package assembly of claim 6, wherein: the overlooking cross section of the packaging adhesive layer is quadrilateral, each corner of the quadrilateral is arc-shaped, and the surface area of the overlooking cross section is gradually increased from the top surface of the packaging adhesive layer to the direction of the lead frame unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922010215.2U CN210467806U (en) | 2019-11-20 | 2019-11-20 | Semiconductor package assembly with convex micro pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922010215.2U CN210467806U (en) | 2019-11-20 | 2019-11-20 | Semiconductor package assembly with convex micro pins |
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| Publication Number | Publication Date |
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| CN210467806U true CN210467806U (en) | 2020-05-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201922010215.2U Active CN210467806U (en) | 2019-11-20 | 2019-11-20 | Semiconductor package assembly with convex micro pins |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111739810A (en) * | 2020-06-22 | 2020-10-02 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor device |
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2019
- 2019-11-20 CN CN201922010215.2U patent/CN210467806U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111739810A (en) * | 2020-06-22 | 2020-10-02 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor device |
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