CN207250487U - Wafer stage chip encapsulating structure - Google Patents
Wafer stage chip encapsulating structure Download PDFInfo
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- CN207250487U CN207250487U CN201721321262.3U CN201721321262U CN207250487U CN 207250487 U CN207250487 U CN 207250487U CN 201721321262 U CN201721321262 U CN 201721321262U CN 207250487 U CN207250487 U CN 207250487U
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- dielectric layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
The utility model provides a kind of wafer stage chip encapsulating structure, and the wafer stage chip encapsulating structure includes：Semiconductor chip；Re-wiring layer, including low-k dielectric layer, in low-k dielectric layer and low-k dielectric layer upper surface metal connecting layer；Solder projection, is electrically connected positioned at the upper surface of re-wiring layer, and with metal connecting layer；Protective layer, positioned at the periphery of semiconductor chip and re-wiring layer.The utility model forms protective layer by the low-k dielectric layer periphery in semiconductor chip and re-wiring layer; the steam of outside can be effectively avoided to penetrate into low-k dielectric layer so that low-k dielectric layer is more easily rupturable; firm low-k dielectric layer can be played again; the effect for preventing external force from being destroyed to low-k dielectric layer; so that low-k dielectric layer is not in slight crack in cutting process, and then it ensure that the performance of encapsulation chip.
Description
Technical field
A kind of semiconductor package and method for packing are the utility model is related to, is sealed more particularly to a kind of wafer stage chip
Assembling structure.
Background technology
, can be in wafer in order to meet the needs of small size development in existing wafer stage chip encapsulating structure (WLCSP)
Low-k dielectric layer (for example, re-wiring layer) is used in level chip-packaging structure, and to be subsequently cut by laser (laser
Saw) or blade cuts (blade saw)；But since low-k dielectric layer is more crisp, especially big compression ring is exposed in low-k dielectric layer
In border, after the steam in air is entered in low-k dielectric layer so that low-k dielectric layer meeting in follow-up cutting process
Slight crack (crack) is easily produced, and the presence of slight crack can seriously affect the performance of encapsulation chip in low-k dielectric layer.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of encapsulation of wafer stage chip
Structure, can cause low-k dielectric layer to produce slight crack for solving presence of the prior art in cutting process, and then influence encapsulation
The problem of performance of chip.
In order to achieve the above objects and other related objects, the utility model provides a kind of wafer stage chip encapsulating structure, institute
Stating wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer upper surface gold
Belong to articulamentum；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal connecting layer and the semiconductor core
Piece is electrically connected；
Solder projection, is electrically connected positioned at the upper surface of the re-wiring layer, and with the metal connecting layer；
Protective layer, positioned at the periphery of the semiconductor chip and the re-wiring layer, and by the semiconductor chip
Side and the side plastic packaging of the low-k dielectric layer.
Preferably, the re-wiring layer includes：
First low-k dielectric layer, positioned at the front of the semiconductor chip；
At least one layer of metal line layer, is electrically connected in first low-k dielectric layer, and with the semiconductor chip；
Second low-k dielectric layer, is covered in the upper surface of first low-k dielectric layer and the metal line layer；
Underbump metallization layer, in second low-k dielectric layer and the second low-k dielectric layer surface, and it is described convex
The lower surface of block lower metal layer is electrically connected with the upper surface of the metal line layer；Wherein
First low-k dielectric layer and second low-k dielectric layer collectively form the low-k dielectric layer, the metal wire
Layer and the Underbump metallization layer collectively form the metal connecting layer.
Preferably, the metal connecting layer includes one layer of metal line layer, and the metal line layer is located at the low-k dielectric layer
It is interior, it is electrically connected with the semiconductor chip and the solder projection.
Preferably, the protective layer is high polymer waterproof material layer.
Preferably, the material of the protective layer is epoxy resin layer.
Preferably, the upper surface of the protective layer is not less than the upper surface of the low-k dielectric layer, and under the protective layer
Surface and the lower surface flush of the semiconductor chip.
Preferably, the wafer stage chip encapsulating structure includes a semiconductor chip.
Preferably, the wafer stage chip encapsulating structure includes at least two semiconductor chips.
The utility model also provides a kind of preparation method of wafer stage chip encapsulating structure, the wafer stage chip encapsulation knot
The preparation method of structure includes the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate is interior formed with several semiconductor chips；
2) in the Semiconductor substrate upper surface formed re-wiring layer, the re-wiring layer include low-k dielectric layer,
In the low-k dielectric layer and the low-k dielectric layer upper surface metal connecting layer；
3) solder projection, the solder projection and metal connecting layer electricity are formed in the upper surface of the re-wiring layer
Connection；
4) in forming groove in the low-k dielectric layer and the Semiconductor substrate, the groove is situated between through the low k up and down
Matter layer is simultaneously extended in the Semiconductor substrate, and the groove surround each described half between each semiconductor chip
Conductor chip；
5) in filling protective layer in the groove；
6) reduction processing is carried out to the Semiconductor substrate from the lower surface of the Semiconductor substrate so that the protective layer
Lower surface with retain the Semiconductor substrate lower surface flush
7) cutting separation is carried out from the protective layer.
Preferably, step 4) includes the following steps：
4-1) in formation first groove portion, low k dielectric described in first groove portion up/down perforation in the low-k dielectric layer
Layer, the first groove portion surround each semiconductor chip between each semiconductor chip；
4-2) in formation second groove portion, the second groove in the Semiconductor substrate of first groove portion bottom
Portion is connected with the first groove portion；The second groove portion is surround each described between each semiconductor chip
Semiconductor chip；The second groove portion and the first groove portion collectively form the groove.
Preferably, step 4-1) in, using laser in forming the first groove portion in the low-k dielectric layer；Step 4-
2) in, using synthesizing knife in forming the second groove portion in the Semiconductor substrate of first groove portion bottom.
Preferably, in step 7), each semiconductor chip is carried out from the protective layer using laser cutting parameter
Cutting separation.
As described above, the wafer stage chip encapsulating structure of the utility model, has the advantages that：
The wafer stage chip encapsulating structure of the utility model passes through the low-k dielectric layer in semiconductor chip and re-wiring layer
Periphery forms protective layer, and protective layer is by semiconductor chip and the side wall plastic packaging of low-k dielectric layer, you can effectively to avoid the water of outside
Vapour, which is penetrated into low-k dielectric layer, make it that low-k dielectric layer is more easily rupturable, and can play the firm low-k dielectric layer, prevents external force
The effect destroyed to the low-k dielectric layer, so that the low-k dielectric layer in the utility model is not in cutting process
Slight crack, and then ensure that the performance of encapsulation chip.
Brief description of the drawings
Fig. 1 is shown as the flow of the preparation method of the wafer stage chip encapsulating structure provided in the utility model embodiment one
Figure.
Fig. 2~Figure 10 is shown as the preparation method of the wafer stage chip encapsulating structure provided in the utility model embodiment one
The structure diagram that each step is presented, wherein, Figure 10 is shown as the structure of the wafer stage chip encapsulating structure of the utility model
Schematic diagram.
Component label instructions
10 semiconductor chips
101 connection weld pads
11 re-wiring layers
111 low-k dielectric layer
1111 first low-k dielectric layer
1112 second low-k dielectric layer
112 metal connecting layers
1121 metal line layers
1122 Underbump metallization layers
12 solder projections
13 protective layers
14 Semiconductor substrates
15 grooves
151 first groove portions
152 second groove portions
16 lasers
17 synthesizing knives
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1~Figure 10.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the utility model provides a kind of preparation method of wafer stage chip encapsulating structure, the wafer scale core
The preparation method of chip package includes the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate is interior formed with several semiconductor chips；
2) in the Semiconductor substrate upper surface formed re-wiring layer, the re-wiring layer include low-k dielectric layer,
In the low-k dielectric layer and the low-k dielectric layer upper surface metal connecting layer；
3) solder projection, the solder projection and metal connecting layer electricity are formed in the upper surface of the re-wiring layer
Connection；
4) in forming groove in the low-k dielectric layer and the Semiconductor substrate, the groove is situated between through the low k up and down
Matter layer is simultaneously extended in the Semiconductor substrate, and the groove surround each described half between each semiconductor chip
Conductor chip；
5) in filling protective layer in the groove；
6) reduction processing is carried out to the Semiconductor substrate from the lower surface of the Semiconductor substrate so that the protective layer
Lower surface with retain the Semiconductor substrate lower surface flush；
7) cutting separation is carried out from the protective layer.
In step 1), S1 steps and Fig. 2 in please referring to Fig.1, there is provided semi-conductive substrate 14, the Semiconductor substrate
Formed with several semiconductor chips 10 in 14.
As an example, the Semiconductor substrate 14 can be silicon substrate, Sapphire Substrate or gallium nitride substrate etc.；It is preferred that
Ground, in the present embodiment, the Semiconductor substrate 14 is Silicon Wafer.
As an example, the semiconductor chip 10 can be any one semiconductor functional chip, the semiconductor chip
10 front is exposed formed with the connection weld pad 101 for drawing its inside function device electricity, the upper surface of the connection weld pad 101
In the upper surface of the semiconductor chip 10, i.e., the upper surface of described connection weld pad 101 and the upper table of the semiconductor chip 10
Face flush.
S2 steps and Fig. 3 in please referring to Fig.1, re-wiring layer 11 is formed in the upper surface of the Semiconductor substrate 14,
The re-wiring layer 11 includes low-k dielectric layer 111, in the low-k dielectric layer 111 and 111 upper table of low-k dielectric layer
The metal connecting layer 112 in face.
In one example, wrapped as shown in figure 3, forming the re-wiring layer 11 in the upper surface of the Semiconductor substrate 14
Include following steps：
2-1) the first low-k dielectric layer 1111 is formed in the upper surface of the Semiconductor substrate 14；
2-2) in forming the first opening (not shown) in first low-k dielectric layer 1111, first opening exposes
The connection weld pad 101；
2-3) in the described first opening and first low-k dielectric layer 1111 of first mouth periphery upper surface
Metal line layer 1121 is formed, the metal line layer 1121 is connected with the connection weld pad 101；
2-4) the second low k dielectric is formed in the upper surface of the metal line layer 1121 and first low-k dielectric layer 1111
Layer 1112；
2-5) in forming the second opening (not shown) in second low-k dielectric layer 1112, second opening exposes
The metal line layer 1121；
2-6) in the described second opening and second low-k dielectric layer 1112 of second mouth periphery upper surface
Underbump metallization layer 1122 is formed, the Underbump metallization layer 1122 is connected with the metal line layer 1121.
Certainly, in other examples, existing any one re-wiring layer preparation process can also be used to prepare includes
The re-wiring layer 11 of the low-k dielectric layer 111, the metal line layer 1121 and the Underbump metallization layer 1122.
In another example, the re-wiring layer 11 includes one layer of low-k dielectric layer 111 and one layer of metal line layer 1121,
The re-wiring layer 11 is formed in the upper surface of the Semiconductor substrate 14 to include the following steps：
2-1) low-k dielectric layer 111 is formed in the upper surface of the Semiconductor substrate 14；
2-2) in forming opening (not shown) in the low-k dielectric layer 111, the opening exposes the connection weld pad
101；
2-3) in the opening and the low-k dielectric layer 111 of the mouth periphery upper surface formed metal line layer
1121, the metal line layer 1121 is connected with the connection weld pad 101.
In step 3), S3 steps and Fig. 4 in please referring to Fig.1, weldering is formed in the upper surface of the re-wiring layer 11
Expect convex block 12, the solder projection 12 is electrically connected with the metal connecting layer 112.
In one example, solder projection 12 is formed in the upper surface of the re-wiring layer 11 to include the following steps：
3-1) metal column is formed in the upper surface of the re-wiring layer 11；
3-2) soldered ball is formed in the upper surface of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering,
Any of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver,
A kind of material or two kinds and two or more combined materials in titanium, can form the soldered ball by planting ball reflux technique.
In another example, can be by planting ball reflux technique as shown in figure 4, the solder projection 12 is a soldered ball
Soldered ball is directly formed as the solder projection 12.
Specifically, when the metal connecting layer 112 in the re-wiring layer 11 includes metal line layer 1121 and described
During Underbump metallization layer 1122, the solder projection 12 is formed at the upper surface of the Underbump metallization layer 1122；When described heavy
When the metal connecting layer 112 in new route layer 11 only includes the metal line layer 1121, the solder projection 12 is formed at
The upper surface of the metal line layer 1121.
In step 4), the S4 steps and Fig. 5 to Fig. 6 that please refer to Fig.1, in the low-k dielectric layer 111 and the semiconductor
Groove 15 is formed in substrate 14, the groove through the low-k dielectric layer 111 and extends to the Semiconductor substrate 14 about 15
Interior, the groove 15 surround each semiconductor chip 10 between each semiconductor chip 10.
As an example, include following step in forming groove 15 in the low-k dielectric layer 111 and the Semiconductor substrate 14
Suddenly：
4-1) in formation first groove portion 151, the 151 up/down perforation institute of first groove portion in the low-k dielectric layer 111
Low-k dielectric layer 111 is stated, the first groove portion 151 surround each semiconductor between each semiconductor chip 10
Chip 10, as shown in Figure 5；
It is described 4-2) in formation second groove portion 152 in the Semiconductor substrate 14 of 151 bottom of first groove portion
Second groove portion 152 is connected with the first groove portion 151；The second groove portion 152 is located at each semiconductor chip
Between 10, and around each semiconductor chip 10；The second groove portion 152 is collectively formed with the first groove portion 151
The groove 15, as shown in Figure 6.
It should be noted that step 4-2) in shape in the Semiconductor substrate 14 of 151 bottom of first groove portion
Into the second groove portion 152 lateral dimension can as shown in Figure 6 be less than the adjacent semiconductor chip 10 between
Away from during forming the second groove portion 152, removing that the part between the adjacent semiconductor chip 10 is described partly to lead
Body substrate 14；Can also be between the lateral dimension in the second groove portion 152 is equal between the adjacent semiconductor chip 10
Away from during forming the second groove portion 152, remove between the adjacent semiconductor chip 10 all described partly leads
Body substrate 14.
As an example, step 4-1) in, the laser that laser 16 is launched can be used in shape in the low-k dielectric layer 111
Into the first groove portion 151, certainly, in other examples, etching technics or mechanical cutting processes can also be used in described
The first groove portion 151 is formed in low-k dielectric layer 111.
As an example, step 4-2) in, partly led in the described of 151 bottom of first groove portion using synthesizing knife 17
The second groove portion 152 is formed in body substrate 14, certainly, in other examples, can also use laser or etching technics in institute
State and the second groove portion 152 is formed in the Semiconductor substrate 14 of 151 bottom of first groove portion.
In step 5), the S5 steps and Fig. 7 that please refer to Fig.1, in filling protective layer 13 in the groove 15.
As an example, gluing process meeting InkJet printing processes can be used in the filling protective layer in the groove 15
13。
As an example, the protective layer 13 can be high polymer waterproof material layer, the protective layer 13 is used for follow-up each institute
State the semiconductor chip 10 and the four sides side wall plastic packaging of the low-k dielectric layer 111 after the cutting separation of semiconductor chip 10, i.e.,
It is possible to prevente effectively from exterior steam penetrates into the low-k dielectric layer 111 so that the low-k dielectric layer 111 is more easily rupturable, again
The firm low-k dielectric layer 111 can be played, the effect for preventing external force from being destroyed to the low-k dielectric layer 111, so that this
The low-k dielectric layer 111 in utility model is not in slight crack in cutting process, and then ensure that the property of encapsulation chip
Energy.
As an example, the protective layer 13 can be but be not limited only to epoxy resin layer.
In step 6), S6 steps and Fig. 8 in please referring to Fig.1, from the lower surface of the Semiconductor substrate 14 to described
Semiconductor substrate 14 carries out reduction processing so that under the lower surface of the protective layer 13 and the Semiconductor substrate 14 retained
Surface flush.
As an example, can use the technique such as grinding technics, etching technics to the Semiconductor substrate 14 from lower surface into
Row reduction processing.
In step 7), S7 steps and Fig. 9 and Figure 10 in please referring to Fig.1, by each semiconductor chip 10 described in
Cutting separation is carried out at protective layer 13.
In one example, laser cutting parameter can be used from the protective layer 13 between each semiconductor chip 10
Place carries out cutting separation, you can with using the laser that laser 16 is launched by each semiconductor chip 10 from the protective layer 13
Place carries out cutting separation, to obtain including the wafer stage chip encapsulating structure of a semiconductor chip 10, such as Figure 10
It is shown.
In another example, laser cutting parameter can also be used between two or more semiconductor chips 10
Cutting separation is carried out at the protective layer 13, to obtain the wafer stage chip of two or more semiconductor chips 10 envelope
Assembling structure.
Embodiment two
Incorporated by reference to Fig. 2 to Figure 10 with continued reference to Figure 10, the present embodiment also provides a kind of wafer stage chip encapsulating structure, described
Wafer stage chip encapsulating structure includes：Semiconductor chip 10；Re-wiring layer 11, the re-wiring layer 11 include low k dielectric
Layer 111, in the low-k dielectric layer 111 and 111 upper surface of low-k dielectric layer metal connecting layer 112；The low k is situated between
Matter layer 111 is located at the front of the semiconductor chip 10, and the metal connecting layer 112 is electrically connected with the semiconductor chip 10
Connect；Solder projection 12, the solder projection 12 are located at the upper surface of the re-wiring layer 11, and with the metal connecting layer
112 are electrically connected；Protective layer 13, the protective layer 13 are located at the periphery of the semiconductor chip and 10 re-wiring layers 11,
And by the side of the semiconductor chip 10 and the side plastic packaging of the low-k dielectric layer 111.
It should be noted that can be as shown in Figure 10, the wafer stage chip encapsulating structure further includes Semiconductor substrate
14, the semiconductor chip 10 is located in the Semiconductor substrate 14, and the protective layer 13 is located at outside the semiconductor chip 10
The surrounding side for the Semiconductor substrate 14 enclosed, by the semiconductor chip 10 and the institute of the periphery of the semiconductor chip 10
State 14 plastic packaging of Semiconductor substrate；Can also be that the protective layer 13 can be located immediately at four sides of the semiconductor chip 10
Face, by the 10 direct plastic packaging of semiconductor chip, i.e., can also be to go the Semiconductor substrate 14 as shown in Figure 10
Remove, the semiconductor chip 10 is occupied such as the position of the Semiconductor substrate 14 in Figure 10, that is, the semiconductor chip 10
The all areas of the lower section of re-wiring layer 11 between the protective layer 13.
As an example, the Semiconductor substrate 14 can be silicon substrate, Sapphire Substrate or gallium nitride substrate etc.；It is preferred that
Ground, in the present embodiment, the Semiconductor substrate 14 is Silicon Wafer.
As an example, the semiconductor chip 10 can be any one semiconductor functional chip, the semiconductor chip
10 front is exposed formed with the connection weld pad 101 for drawing its inside function device electricity, the upper surface of the connection weld pad 101
In the upper surface of the semiconductor chip 10, i.e., the upper surface of described connection weld pad 101 and the upper table of the semiconductor chip 10
Face flush.
In one example, as shown in Fig. 3 and Figure 10, the re-wiring layer 11 includes：First low-k dielectric layer 1111, institute
State the front that the first low-k dielectric layer 1111 is located at the semiconductor chip 10；At least one layer of metal line layer 1121, the metal wire
Layer 1121 is electrically connected in first low-k dielectric layer 1111 with the semiconductor chip 10；Second low-k dielectric layer
1112, second low-k dielectric layer 1112 is covered in first low-k dielectric layer 1111 and the upper table of the metal line layer 1121
Face；Underbump metallization layer 1122, the Underbump metallization layer 1122 are located in second low-k dielectric layer 1112 and described second
1112 surface of low-k dielectric layer, and the lower surface of the Underbump metallization layer 1122 and the upper surface electricity of the metal line layer 1121
Connection；Wherein, first low-k dielectric layer 1111 and second low-k dielectric layer 1112 collectively form the low-k dielectric layer
111, the metal line layer 1121 and the Underbump metallization layer 1122 collectively form the metal connecting layer 112.
In another example, the metal connecting layer 112 only includes one layer of metal line layer 1121, and the metal line layer
1121 in the low-k dielectric layer 111, are electrically connected with the semiconductor chip 10 and the solder projection 12.
In one example, the solder projection 12 includes metal column and soldered ball, wherein, the metal column positioned at it is described again
The upper surface of wiring layer 11, and be electrically connected with the re-wiring layer 11；The soldered ball is located at the upper surface of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials.The material of the soldered ball can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials.
In another example, as shown in Figure 10, the solder projection 12 is a soldered ball.
As an example, the protective layer 13 is high polymer waterproof material layer.Preferably, the material of the protective layer 13 can be with
For but be not limited only to epoxy resin layer.
As an example, the upper surface of the protective layer 13 is not less than the upper surface of the low-k dielectric layer 111, i.e., described guarantor
Upper surface flush of the upper surface of sheath 13 with the low-k dielectric layer 111 or the upper surface higher than the low-k dielectric layer 111,
And the lower surface of the protective layer 13 and the lower surface flush of the semiconductor chip 10, to ensure the protective layer 13 by institute
State the side of semiconductor chip 10 and the side plastic packaging of the low-k dielectric layer 111.
In one example, as shown in Figure 10, the wafer stage chip encapsulating structure includes a semiconductor chip 10.
In another example, the wafer stage chip encapsulating structure can also include two or more semiconductor chips
10.The protective layer 13 around each semiconductor chip 10 is provided between the adjacent semiconductor chip 10.
In conclusion the wafer stage chip encapsulating structure of the utility model, the wafer stage chip encapsulating structure includes：Half
Conductor chip；Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer upper surface
Metal connecting layer；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal connecting layer and the semiconductor
Chip is electrically connected；Solder projection, is electrically connected positioned at the upper surface of the re-wiring layer, and with the metal connecting layer；Protection
Layer, positioned at the periphery of the semiconductor chip and the re-wiring layer, and by the side of the semiconductor chip and the low k
The side plastic packaging of dielectric layer.The wafer stage chip encapsulating structure of the utility model passes through in semiconductor chip and re-wiring layer
Low-k dielectric layer periphery forms protective layer, and protective layer is by semiconductor chip and the side wall plastic packaging of low-k dielectric layer, you can effectively to keep away
The steam for exempting from outside is penetrated into low-k dielectric layer so that low-k dielectric layer is more easily rupturable, and can play the firm low k dielectric
Layer, the effect for preventing external force from being destroyed to the low-k dielectric layer, so that the low-k dielectric layer in the utility model is being cut through
Be not in slight crack in journey, and then ensure that the performance of encapsulation chip.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (8)
1. a kind of wafer stage chip encapsulating structure, it is characterised in that the wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer upper surface metal connect
Connect layer；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal connecting layer and semiconductor chip electricity
Connection；
Solder projection, is electrically connected positioned at the upper surface of the re-wiring layer, and with the metal connecting layer；
Protective layer, positioned at the periphery of the semiconductor chip and the re-wiring layer, and by the side of the semiconductor chip
And the side plastic packaging of the low-k dielectric layer.
2. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The re-wiring layer includes：
First low-k dielectric layer, positioned at the front of the semiconductor chip；
At least one layer of metal line layer, is electrically connected in first low-k dielectric layer, and with the semiconductor chip；
Second low-k dielectric layer, is covered in the upper surface of first low-k dielectric layer and the metal line layer；
Underbump metallization layer, in second low-k dielectric layer and the second low-k dielectric layer surface, and under the convex block
The lower surface of metal layer is electrically connected with the upper surface of the metal line layer；Wherein
First low-k dielectric layer and second low-k dielectric layer collectively form the low-k dielectric layer, the metal line layer and
The Underbump metallization layer collectively forms the metal connecting layer.
3. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The metal connecting layer includes one layer
Metal line layer, and the metal line layer is located in the low-k dielectric layer, is electrically connected with the semiconductor chip and the solder projection
Connect.
4. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The protective layer is macromolecule waterproof
Material layer.
5. wafer stage chip encapsulating structure according to claim 4, it is characterised in that：The material of the protective layer is epoxy
Resin bed.
6. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The upper surface of the protective layer is not low
In the upper surface of the low-k dielectric layer, and the lower surface of the protective layer and the lower surface flush of the semiconductor chip.
7. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The wafer stage chip encapsulating structure
Including a semiconductor chip.
8. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The wafer stage chip encapsulating structure
Including at least two semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721321262.3U CN207250487U (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721321262.3U CN207250487U (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure |
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| Publication Number | Publication Date |
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| CN207250487U true CN207250487U (en) | 2018-04-17 |
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| CN107611093A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |