TWI430406B - 3dic architecture with interposer for bonding dies - Google Patents

Description

Integrated circuit component and method of forming same

The present disclosure relates to integrated circuits, and more particularly to three-dimensional integrated circuits (3DICs) including interposers and methods of forming the same.

Since the invention of the integrated circuit, the semiconductor industry has experienced continuous rapid growth due to the continuous increase in the integration density of various electronic components (ie, transistors, diodes, resistive components, capacitive components, etc.). For the most part, this increase in integration density comes from the repeated minimization of the minimum feature size, which allows more components to be integrated into the given wafer area.

These integration enhancements are actually two-dimensional in nature, where the integrated components occupy a volume that is substantially on the surface of the semiconductor wafer. Although the significant enhancement of the lithography process has made considerable progress in the fabrication of two-dimensional integrated circuits, the density that can be achieved in two dimensions has physical limitations. One of these limitations is the minimum size required to make these components. Also, when more components are placed in a wafer, more complex designs are needed. Another additional limitation is that as the number of components increases, the number and length of interconnects between components increases significantly. As the length and number of interconnects increase, the RC delay and power consumption of the circuit also increase.

Thus, three-dimensional integrated circuits (3DICs) are formed in which two wafers can be stacked, in which one through-silicon vias (TSVs) are formed to connect another wafer to the package substrate. The through-conducting conductive structure is often formed after a front-end-of-line (FEOL) in which components such as transistors are formed, and possibly also in a back-end-of-line (BEOL) process. ) (formed in which an interconnect structure is formed). This can result in yield loss of the formed wafer. Furthermore, since the conductive structure is formed after the formation of the integrated circuit, the manufacturing process time is also lengthened.

An embodiment of the present invention provides an integrated circuit component, including: an interposer having substantially no integrated circuit component, wherein the interposer includes: a substrate having a first side and opposite to the first side a plurality of through-substrate conductive structures are disposed in the substrate; a first interconnect structure is disposed on the first side of the substrate and electrically coupled to the at least one of the through-substrate conductive structures; a second interconnect structure is disposed on the second side of the substrate and electrically coupled to the at least one of the through substrate conductive structures; a first wafer bonded to the first interconnect structure; And a second wafer bonded to the second interconnect structure.

An embodiment of the present invention provides an integrated circuit component, including: an interposer having substantially no integrated circuit component, wherein the interposer includes: a substrate having a first side and opposite to the first side a plurality of through-substrate conductive structures are disposed in the substrate; a first interconnect structure is disposed on the first side of the substrate and electrically coupled to the at least one of the through-substrate conductive structures; An opening in the substrate adjacent to at least one of the through-substrate conductive structures; a first wafer bonded to the first interconnect structure; and a second wafer formed in the opening And bonded to the first interconnect structure.

An embodiment of the present invention provides a method of forming an integrated circuit component, comprising: providing a germanium substrate having substantially no integrated circuit component; forming a through-substrate conductive structure from a front side of the germanium substrate through the germanium substrate to Forming a first interconnecting structure on the front side of the germanium substrate, wherein the first interconnecting structure comprises at least one dielectric layer and a metal structure in the at least one dielectric layer; a first wafer is bonded to the first interconnect structure; the germanium substrate is removed from a back side of the germanium substrate to expose one end of the through-substrate conductive structure; and a first side is formed on the back side of the germanium substrate a second interconnect structure, and the second interconnect structure is electrically coupled to the end of the through-substrate conductive structure; forming an opening, passing through the second interconnect structure and the germanium substrate, and reaching the first a surface of one of the interconnect structures; and bonding a second wafer to the surface of the first interconnect structure in the opening.

Other embodiments are also disclosed.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers. Many structures may be drawn to different sizes for simplicity and clarity.

A novel three-dimensional integrated circuit (3DIC) and a method of forming the same are provided. The intermediate process steps of the manufacturing embodiment will be explained. Variations of the embodiments will be discussed. In the drawings and embodiments, like reference numerals will be used to refer to the like.

Referring to Figure 1A, a substrate 10 is provided. Throughout the description, the substrate 10 and the corresponding interconnect structures 12 and 32 (not shown in FIG. 1A, please refer to FIG. 1D) will collectively be referred to as an interposer wafer 100. Substrate 10 may be formed from a semiconductor material such as germanium, germanium, tantalum carbide, gallium arsenide, or other commonly used semiconductor materials. Alternatively, substrate 10 is formed from a dielectric material. The interposer wafer 100 generally does not have integrated circuit components, and includes active components such as transistors and diodes. Moreover, the interposer wafer 100 may include (or may not have) passive components such as capacitive elements, resistive elements, inductive elements, varactors, and/or the like.

A front-side interconnect structure 12 is formed over the substrate 10. The interconnect structure 12 includes one or more dielectric layers 18 and metal lines 14 and vias 16 in the dielectric layer 18. Throughout the description, the side of the interposer wafer 100 that faces upward in FIG. 1A is referred to as the front side, and the side that faces downward is referred to as the back side. Metal lines 14 and vias 16 are referred to as front-side redistribution lines (RDLs). Furthermore, through-substrate vias (TSVs) 20 are formed in the substrate 10 to a predetermined depth and may pass through some or all of the dielectric layers 18. The through substrate conductive structure 20 is electrically coupled to the front side redistribution line (14/16).

Next, a front side (metal) bump (or pad) 24 is formed on the front side of the interposer wafer 100, and is electrically coupled to the through substrate conductive structure 20 and the redistribution line (14/16). In an embodiment, the front side metal bumps 24 are solder bumps, such as eutectic solder bumps. In another embodiment, the front side metal bumps 24 are copper bumps or other metal bumps that may be formed of gold, silver, nickel, tungsten, aluminum, and/or alloys of the foregoing. The front side metal bumps 24 may protrude from the surface of the interconnect structure 12.

Referring to FIG. 1B, the dies 22 are bonded to the front side metal bumps 24. The wafer 22 may be an element wafer including integrated circuit components, for example, including a transistor, a capacitive element, an inductive element, a resistive element (not shown), and the like. Moreover, the wafer 22 can be a logic chip including a core circuit, and can be, for example, a central processing unit (CPU) wafer. The bond between the wafer 22 and the front side metal bumps 24 may be solder bonding or direct metal-to-metal bonding, such as copper-to-copper bonding. Alternatively, the wafer 22 is joined after the back side inner wiring structure 32 (Fig. 1D) is formed, as will be discussed in detail later. The primer 23 is injected into the space between the wafer 22 and the interposer wafer 100 and cured.

Referring to FIG. 1C, a carrier 26 (which may be a glass wafer) is bonded to the front side of the interposer wafer 100 through the adhesive layer 28. Adhesive layer 28 can be a UV glue or can be formed from other known adhesive materials. Wafer backside polishing is performed to thin the substrate 10 from the back side until the through substrate conductive structure 20 is exposed. An etching process can be performed to further reduce the surface of the substrate 10 such that the through substrate conductive structure 20 protrudes from the back surface of the remaining portion of the substrate 10.

Next, as shown in FIGS. 1D and 1E, the back side interconnect structure 32 is formed to connect through the base conductive structure 20. In many embodiments, the backside interconnect structure 32 can have a structure similar to the front side interconnect structure 12, and can include metal bumps and one or more layers of redistribution circuitry. For example, the backside interconnect structure 32 can include a dielectric layer 34 on the substrate 10, wherein the dielectric layer 34 can be a low-temperature polyimide layer or a well-known dielectric material. Formed, for example, spin-on glass, cerium oxide, cerium oxynitride, or the like. Dielectric layer 34 can be formed using chemical vapor deposition (CVD). When a low temperature polyimide layer is used, the dielectric layer 34 can also function as a stress buffer layer. As shown in FIG. 1E, a bump under metal layer (UBM) 36 and a back side metal bump 38A are then formed. Similarly, the backside metal bumps 38A can be solder bumps, such as eutectic solder bumps, copper bumps, or other metal bumps formed of gold, silver, nickel, tungsten, aluminum, and/or alloys of the foregoing. Piece. In an embodiment, the under bump metal layer 36 and the back side metal bump 38A may comprise a blanket-formed under bump metal layer, a mask formed on the under bump metal layer, having an opening, opening The backside metal bumps 38A are plated, the mask is removed, and a quick etch is performed to remove portions of the underlying metal layer of the blanket bump that were previously covered by the mask.

Referring to FIG. 1F, the wafer 50 is bonded to the back side of the interposer wafer 100. The wafer 50 is electrically coupled to the wafer 22 through the front side interconnect structure 12 , the back side interconnect structure 32 , and the through substrate conductive structure 20 . Wafer 22 and wafer 50 can be different types of wafers. For example, wafer 22 can be a logic wafer, such as a CPU wafer, and wafer 50 can be a memory wafer.

Next, as shown in FIG. 1H, a large bump 38B is formed on the back side of the interposer wafer 100, and is electrically coupled to the back side interconnect structure 32, the through substrate conductive structure 20, and possibly the wafer. 22 and 50. The large bumps 38B can be solder bumps, for example formed of eutectic solder, although they can be other types of bumps, such as metal bonds. In other embodiments, the order in which the wafer 50 is bonded and the large bumps 38B are formed may be reversed. Figure 1G shows another embodiment in which large bumps 38B are formed first, followed by bonding of wafers 50 to form the structure shown in Figure 1H. In these embodiments, bumps 38A (hereinafter referred to as small bumps) and large bumps 38B may be formed simultaneously using a one-step bump formation process.

In Fig. 1I, the carrier substrate 26 as shown in Fig. 1H is removed, and the adhesive layer 28 is rendered viscous, for example, by irradiating the adhesive layer 28 (UV glue) with ultraviolet light. Next, the dicing tape 60 is attached to the front side of the final structure. Next, dicing along line 62 separates interposer wafer 100 and wafers 22 and 50 bonded to interposer wafer 100 into a plurality of wafers.

In FIG. 1I, the back side of the portion of the interposer wafer 100 is not available for forming the large bumps 38B due to the presence of the wafer 50. However, in other embodiments shown in Figures 2A-2D, more large bumps 38B may be formed because some of the large bumps 38B (labeled 38B' as shown in Figure 2D) may be formed. Vertically aligned and overlaid on wafer 50. A brief process flow is shown in Figure 2A-2D. The initial process steps of this embodiment can be substantially the same as those shown in Figures 1A-1F, in which the small bumps 38A are formed to bond the wafer 50, and this time no large bumps 38B are formed. Next, as shown in FIG. 2A, the wafer 50 is bonded to the back side of the interposer wafer 100. The primer 52 is filled into the space between the wafer 50 and the interposer wafer 100, and then the primer 52 is cured.

Referring to FIG. 2B, a molding compound 54 (or encapsulating material) is formed on the wafer 50 and the interposer wafer 100. The top surface of the encapsulation compound 54 can be higher or higher than the top surface of the wafer 50. Referring to FIG. 2C, deep vias 56 are formed to pass through the encapsulation compound 54 and electrically coupled to the back side interconnect structure 32. Next, an interconnect structure 58 is formed that includes a redistribution trace 49 that is electrically coupled to the deep via 56 and then forms a under bump metal layer (not labeled) and a large bump 38B. Again, a stress buffer layer may be formed under the under bump metal layer, which may be formed from a polyimide layer or a solder resist. It can be seen that some of the large bumps 38B (labeled 38B') can be formed directly on a portion of the wafer 50 and vertically overlap the portion of the wafer 50, so that the number of large bumps 38B can be increased beyond that shown in FIG. structure.

In the 2D drawing, the carrier substrate 26 is removed. Next, the dicing tape 60 is attached to the front side of the final structure. Next, dicing is performed to separate the interposer wafer 100 and the wafers 22 and 50 bonded to the interposer wafer 100 into a plurality of wafers.

3A-3D shows another embodiment. The initial process steps of this embodiment can be substantially the same as those shown in FIGS. 1A-1F and 2A, wherein the wafer 50 is bonded over the interposer wafer 100. Next, as shown in FIG. 3A, a dummy wafer 66 is bonded over the interposer wafer 100, wherein the material of the dummy wafer is also referred to as an encapsulating material. In one embodiment, the dummy wafer 66 is a dummy wafer. In another embodiment, dummy wafer 66 is formed from other semiconductor materials, such as tantalum carbide, gallium arsenide, or the like. The dummy wafer 66 may have no integrated circuit components (eg, capacitive components, resistive components, varactor components, inductive components, and/or transistors) therein. In yet another embodiment, the dummy wafer 66 can be a dielectric wafer. Cavities 68 are formed in the dummy wafer 66. Bonding of the dummy wafer 66 onto the interposer wafer 100 can include oxide-to-oxide bonding. In one embodiment, an oxide layer 69, which may be made of yttrium oxide (eg, thermal oxide), is formed on the dummy wafer 66 before the dummy wafer 66 is bonded to the interposer wafer 100. The oxide layer 70 is formed on the interposer wafer 100 in advance. Next, the oxide layer 69 is bonded to the oxide layer 70 by oxide-to-oxide bonding. Thus, wafer 50 is housed in cavity 68 and the surface 72 of the final structure is flat.

Next, as shown in FIG. 3B, a through-substrate conductive structure (ie, deep via 56) is formed to pass through the dummy wafer 66 and the oxide layers 69 and 70, and is electrically coupled to the back side interconnect. Structure 32. Next, an interconnect structure 58 is formed that includes a redistribution trace 49 that is electrically coupled to the deep via 56 and then forms a under bump metal layer (not labeled) and a large bump 38B. Again, the large bump 38B includes a bump 38B' that is formed directly over the wafer 50 and that is vertically overlaid on the wafer 50.

In Fig. 3C, the carrier substrate 26 is removed. Next, the dicing tape 60 is adhered to one side of the final structure. Next, dicing is performed to separate the interposer wafer 100 and the wafers 22 and 50 bonded to the interposer wafer 100 into a plurality of wafers.

4A-4D shows yet another embodiment in which the wafer 50 is located in a cavity in the interposer wafer 100. First, the structure shown in Fig. 4A is formed, wherein the process can be substantially the same as that shown in Figs. 1A-1E. Therefore, the details of the formation are not discussed here. Next, as shown in FIG. 4B, an opening 74 is formed in the interposer wafer 100, and for example, wet etching or dry etching can be used. This is done by forming and patterning the photoresist 76 and then etching the interposer wafer 100 through the openings in the photoresist 76. The etching may stop when the front side interconnect structure 12 is etched, or when a portion of the metal features in the front side interconnect structure 12 are exposed. The metal structure exposed in the front side interconnect structure 12 can be used as a bond pads.

In FIG. 4C, the wafer 50 is inserted into the opening 74 and bonded to the metal structure in the front side interconnect structure 12. The bonding can be solder bonding, metal to metal bonding, or similar bonding. Therefore, the wafer 50 can be electrically coupled to the wafer 22 and through the substrate conductive structure 20. Next, the primer 80 is filled into the remaining space in the opening 74.

Referring to FIG. 4D, a large bump 38B is formed. In another embodiment, the large bump 38B is formed prior to the formation of the opening 74 (Fig. 4B) and the bonding of the wafer 50. In Fig. 4E, the dicing tape 60 is pasted, and the three-dimensional integrated circuit shown in Fig. 4E can be cut into individual wafers.

In another embodiment, after forming the structure shown in FIG. 4C, the package compound 54 (2B-2D pattern) or the dummy wafer 66 (3A-3C pattern) is formed/joined and displayed on the 4C. The structure of the figure, as well as the opposite side of the interposer wafer 100 relative to the wafer 22. The remaining process steps can be similar to those shown in Figures 2B-2D and 3A-3C and are therefore not discussed here. Moreover, in each of the embodiments discussed above, wafer 22 can be bonded over interposer wafer 50 before or after bonding wafer 50, and can be bonded after formation of large bumps 38B.

In the above embodiments, the through-substrate conductive structures 20 in the interposer wafer 100 (see, for example, FIG. 1C) may have the same length. In another embodiment, the through substrate conductive structures 20 can have different lengths. 5A-5D illustrate an embodiment of forming a through-substrate conductive structure 20 having different lengths. Referring to FIG. 5A, a substrate 10 of the interposer wafer 100 is provided, and an interconnect structure 12 is formed on the substrate 10. The interconnect structure 12 includes under bump metal layers and bumps (not labeled). Next, as shown in FIG. 5B, the wafer 22 is bonded onto the interposer wafer 100, and the underfill 23 is injected into the space between the wafer 22 and the interposer wafer 100, and the underfill 23 is cured.

Referring to FIG. 5C, the carrier substrate 26 (which may be a glass wafer) is bonded to the front side of the interposer wafer 100 through the adhesive layer 28. Wafer backside grinding is performed to thin the substrate 10 from the back side to the desired thickness. Next, through-substrate conductive structure openings (TSV openings), which are occupied by the through-substrate conductive structures 20, are formed to pass through the substrate 10. Furthermore, the through-substrate conductive structure opening extends into the dielectric layer 18 to form the interconnect structure 12. Next, a metal material is filled in the through-substrate conductive structure opening to form the through-substrate conductive structure 20, and a dielectric layer 25 is formed to electrically isolate the through-substrate conductive structure 20 from the substrate 10. In the final structure, the metal features 88 (of the interconnect structure 12) include metal structures 88A and 88B, wherein the metal structures 88A are buried inside the deeper dielectric layer 18 than the metal structures 88B. In the formation of the through-substrate conductive structure openings, the metal structures 88A and 88B can be used as an etch stop layer, and thus the etching of the dielectric layer 18 is stopped at different depths. Therefore, the length L1 (Fig. 5D) of the through-substrate conductive structure 20A is greater than the length L2 of the through-substrate conductive structure 20B. Subsequent processing steps may be substantially the same as those shown in Figures 1E-1I, or substantially the same as shown in other embodiments (when appropriate).

It can be seen that in embodiments (e.g., panels 1I, 2D, 3C, and 4E), no substrate conductive structures are required in any of the wafers 22 and 50, although the through-substrate conductive structures can be formed on the wafers 22 and 50. . However, the components in the wafers 22 and 50 can be electrically coupled to the large bumps 38B and electrically coupled to each other. In a conventional three-dimensional integrated circuit, the through-substrate conductive structure is formed after the integrated circuit in the element wafer is formed. This results in a loss of yield and an increase in the packaging process time. However, in the embodiment, the substrate conductive structures are not required to be worn in any of the component wafers 22 and 50, and the loss of yield due to the formation of the through-substrate conductive structures in the wafers 22 and 50 can be avoided. Moreover, since the interposer wafer 100 and the corresponding through-substrate conductive structure can be formed when the wafers 22 and 50 have been formed, the flow time can be reduced.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

10. . . Base

12, 32, 58. . . Inline structure

14. . . Metal line

16. . . Via window

18, 25. . . Dielectric layer

20, 20A, 20B. . . Substrate conductive structure

22, 50. . . Wafer

23, 52, 80. . . Primer

twenty four. . . Front side (metal) bump (or pad)

26‧‧‧Loading substrate

28‧‧‧Adhesive layer

34‧‧‧ dielectric layer

36‧‧‧Under bump metal layer

38‧‧‧Back side metal bumps

38A, 38B, 38B’‧‧‧Bumps

49‧‧‧Re-route

54‧‧‧Packaging compounds

56‧‧‧deep window

60‧‧‧Cut Tape

62‧‧‧ line

66‧‧‧Virtual Wafer

68‧‧‧ Cavity

69, 70‧‧‧ oxide layer

72‧‧‧ surface

74‧‧‧ openings

76‧‧‧Light resistance

88, 88A, 88B‧‧‧Metal structure

100‧‧‧Interposer Wafer

L1, L2‧‧‧ length

1A-1I is a cross-sectional view showing a process for fabricating a three-dimensional integrated circuit in which a wafer is bonded to both sides of an interposer in accordance with an embodiment of the present invention.

2A-2D are cross-sectional views showing a process for fabricating a three-dimensional integrated circuit in accordance with an embodiment of the present invention in which a potting compound is used to form a planar surface for forming more large bumps.

3A-3C are cross-sectional views showing a process for fabricating a three-dimensional integrated circuit in accordance with an embodiment of the present invention in which dummy wafers are used to form a planar surface for forming more large bumps.

4A-4E are cross-sectional views showing a process for fabricating a three-dimensional integrated circuit in which a wafer is located in the opening of the interposer in accordance with an embodiment of the present invention.

5A-5D are cross-sectional views showing a process for fabricating a three-dimensional integrated circuit in accordance with an embodiment of the present invention, wherein the through-substrate conductive structures in the interposer have different lengths.

10. . . Base

12, 32. . . Inline structure

20. . . Substrate conductive structure

22, 50. . . Wafer

80. . . Primer

38B. . . Bump

60. . . Cutting tape

100. . . Interposer wafer

Claims (10)

An integrated circuit component comprising: an interposer having substantially no integrated circuit component, wherein the interposer comprises: a substrate having a first side and a second side opposite to the first side; a substrate conductive structure is disposed in the substrate; a first interconnect structure is disposed on the first side of the substrate and electrically coupled to the at least one of the through substrate conductive structures; and a second interconnect The structure is located on the second side of the substrate and electrically coupled to the at least one of the through-substrate conductive structures; a first wafer bonded to the first interconnect structure; a second wafer bonded Above the second interconnect structure; an encapsulation material over the second wafer; and a cavity between the encapsulation material and the second wafer. The integrated circuit component of claim 1, further comprising: a packaging material over the second interconnect structure and surrounding the second wafer; a conductive via through the package The material is electrically coupled to the second interconnect structure; a third interconnect structure is disposed over the encapsulation material and electrically connected to the conductive via; and a bump is formed on the The third interconnect structure is electrically coupled to the conductive via. The integrated circuit component of claim 1, further comprising: a conductive via, passing through the package material and electrically coupled to the second interconnect structure; a third interconnect The structure is disposed on the package material and electrically coupled to the conductive via window; and a bump is formed on the third interconnect structure and electrically coupled to the conductive via window. The integrated circuit component of claim 3, wherein the encapsulating material comprises a dummy substrate. The integrated circuit component of claim 1, wherein the through-substrate conductive structures have different lengths and extend from the substrate into different depths of the first interconnect structure. The integrated circuit component of claim 1, further comprising a solder bump located above the second interconnect structure and adjacent to the second wafer. An integrated circuit component comprising: an interposer having substantially no integrated circuit component, wherein the interposer comprises: a substrate having a first side and a second side opposite to the first side; a substrate conductive structure, located in the substrate; a first interconnect structure on the first side of the substrate and electrically coupled to the at least one of the through substrate conductive structures; and an opening on the substrate And adjacent to at least one of the piercing bases a bottom conductive structure; a first wafer bonded over the first interconnect structure; and a second wafer formed in the opening and bonded to the first interconnect structure. The integrated circuit component of claim 7, further comprising a second interconnect structure disposed on the second side of the substrate and electrically coupled to the at least one of the through-substrate conductive structures. A method of forming an integrated circuit component, comprising: providing a germanium substrate having substantially no integrated circuit component; forming a through-substrate conductive structure from a front side of the germanium substrate through the germanium substrate to a predetermined depth; Forming a first interconnect structure on the front side of the germanium substrate, wherein the first interconnect structure comprises at least one dielectric layer and a metal structure in the at least one dielectric layer; bonding a first wafer to the a first interconnect structure; removing the germanium substrate from a back side of the germanium substrate to expose one end of the through-substrate conductive structure; forming a second interconnect structure on the back side of the germanium substrate, The second interconnect structure is electrically coupled to the end of the through-substrate conductive structure; an opening is formed through the second interconnect structure and the germanium substrate, and reaches the first interconnect structure a surface; and bonding a second wafer to the surface of the first interconnect structure in the opening. An integrated circuit component comprising: An interposer, substantially without an integrated circuit component, wherein the interposer includes: a substrate having a first side and a second side opposite to the first side; a plurality of through-substrate conductive structures located on the substrate a first interconnect structure on the first side of the substrate and electrically coupled to the at least one of the through-substrate conductive structures; and a second interconnect structure located on the substrate On the two sides, and electrically coupled to the at least one of the through-substrate conductive structures; a first wafer bonded to the first interconnect structure; and a second wafer bonded to the second interconnect structure Above; wherein the through substrate conductive structures have different lengths and extend from the substrate into different depths of the first interconnect structure.