CN101572260B - Multi-chip stacking type packaging body - Google Patents
Multi-chip stacking type packaging body Download PDFInfo
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- CN101572260B CN101572260B CN2008100958443A CN200810095844A CN101572260B CN 101572260 B CN101572260 B CN 101572260B CN 2008100958443 A CN2008100958443 A CN 2008100958443A CN 200810095844 A CN200810095844 A CN 200810095844A CN 101572260 B CN101572260 B CN 101572260B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention provides a multi-chip stacking type packaging body which comprises a first line base plate, a first chip, a second line base plate and a second chip, wherein the first chip is arranged on the first line base plate and is provided with a first active surface far away from the first line base plate; and the second line base plate is arranged on the first chip and comprises a dielectric layer, a first line layer and a second line layer. The first line layer is electrically connected with the first chip and the first line base plate; the second line layer is electrically connected with the first line base plate; and the first line layer and the second line layer are respectively arranged at two opposite sides of the dielectric layer. The second chip is arranged on the second line base plate and is electrically connected with the second line layer. The second chip is provided with a second active surface, and the second active surface and the first active surface face the second line base plate.
Description
Technical field
The invention relates to a kind of multi-chip stacking packaging body (multi-chip stack packageassembly), and multi-chip stacking packaging body particularly preferable relevant for a kind of effectiveness and that manufacturing cost is lower.
Background technology
Along with electronics technology evolution constantly, functional more complicated and more humane electronic product is weeded out the old and bring forth the new.In addition, the outward appearance of electronic product is also towards light, thin, short, little trend design.Therefore, on semiconductor packaging, develop the form of many high-density semiconductor encapsulation, for example the multi-chip stacking packaging body.
Fig. 1 is the generalized section of existing a kind of multi-chip stacking packaging body.Please refer to Fig. 1, multi-chip stacking packaging body 100 has a circuit base plate (wiring substrate) 110, the active supine chip of multi-disc, and for example one first chip 120 and is disposed at second chip 130 between the circuit base plate 110 and first chip 120, many first bonding wires (bonding wire) 140, many second bonding wires 150 and a plurality of soldered balls (solder ball) 160.Each first connection pad (pad) 122 of first chip 120 electrically connects by one of them of these first bonding wires 140 and first conductive channel 112 of circuit base plate 110.Each second connection pad 132 of second chip 130 electrically connects by second conductive channel 114 of these second bonding wires 150 with circuit base plate 110.These soldered balls 160 are disposed at the lower surface of circuit base plate 110, away from the upper side of second chip 130.Soldered ball as shown in Figure 1, the active face of first chip 120 up, the position of causing its first connection pad 122 is the right sides that are positioned at multi-chip stacking packaging body 100, so that first conductive channel 112 in circuit base plate 110 is electrically connected at the soldered ball 160b of the leftmost side in order to make first connection pad 122, need in circuit base plate 110, to do the coiling design; Relatively, the position of second connection pad 132 then can be located at the left side of multi-chip stacking packaging body 100, so that second conductive channel 114 in circuit base plate 110 also needs to do the coiling design equally in order to make second connection pad 132 be electrically connected at the soldered ball 160a of the rightmost side in circuit base plate 110.
Yet, because the length of each first bonding wire 140 is different from the length of each second bonding wire 150,, the signal that first chip 120 is produced transfers to the required asynchronism(-nization) of each first conductive channel 112 by first connection pad 122 so transferring to signal that required time of each first conductive channel 112 and second chip 130 produced by first connection pad 122.The problem that has signal delay when therefore, multi-chip stacking packaging body 100 operates produces.In addition, the coiling of first conductive channel 112 shown in above-mentioned and second conductive channel 114 design causes the problem of signal delay equally.
Prior art is in order to address the above problem, and makes layer (redistributionlayer) (not the illustrating) of rerouting on chip.For chip, after wafer (not illustrating) completes, become in these predetermined cuts on the zone of chip to expose a plurality of contacts (contact) (not illustrating), but these contacts are not necessarily arranged according to designer's demand.Therefore, become in these predetermined cuts to make the layer that reroutes on the zone of chip, make that being exposed to outer connection pad at last can arrange and be electrically connected to these contacts respectively by the circuit (circuit) of the layer that reroutes according to designer's demand.After the layer that reroutes is finished, wafer will cut to form chip.
Yet, the width of circuit of layer of rerouting less (width between be between 5 microns and 10 microns) and its material are mostly for golden, and the relatively poor and golden price of conductivity of gold is comparatively expensive, and the efficient of the transmission signals of therefore existing multi-chip stacking packaging body is relatively poor and cost is higher.In addition, in the prior art, make when rerouting layer, all predetermined cuts of a wafer become on the zone of chip all must make the layer that reroutes simultaneously.But in practical application, the designer wishes to make the layer that reroutes on these predetermined cuts become the some in zone of chip, and other predetermined cuts become the zone of chip then not wish to make the layer that reroutes.Therefore, the reroute technology of layer of existing making can't satisfy the demand of user and often cause the utilance of wafer to reduce, and then increases the cost of making the multi-chip stacking packaging body.In addition, make the layer that reroutes and must carry out in dust free room, the cost of manufacture of therefore existing multi-chip stacking packaging body is higher.
Summary of the invention
The present invention proposes a kind of multi-chip stacking packaging body, and its effectiveness is preferable and manufacturing cost is lower.
For specifically describing content of the present invention, propose a kind of multi-chip stacking packaging body at this and comprise one first circuit base plate, one first chip, one second circuit base plate and one second chip.First chip configuration and has one first active face on first circuit base plate, wherein first active face is towards the first direction away from first circuit base plate.Second circuit base plate is disposed on first chip, and it comprises a dielectric layer, one first line layer and one second line layer.First line layer is electrically connected to first chip and first circuit base plate.Second line layer is electrically connected to first circuit base plate, and first line layer and second line layer are disposed at the relative both sides of dielectric layer respectively.Second chip configuration and is electrically connected to second line layer on second circuit base plate.Second chip has one second active face, and second active face is towards the second direction of first circuit base plate, and wherein, first direction is parallel to each other with second direction and is opposite.
In one embodiment of this invention, first circuit base plate has a lower surface, and lower surface comprises one first soldered ball and one second soldered ball.
In one embodiment of this invention, first chip has more first connection pad and second connection pad that is disposed on first active face, and wherein first connection pad is electrically connected at first soldered ball, and second connection pad is electrically connected at second soldered ball.Second chip also has the 3rd connection pad and the 4th connection pad that is disposed on second active face, wherein, the 3rd connection pad is electrically connected at first soldered ball, the 4th connection pad then is electrically connected at second soldered ball, and one first connection pad and the corresponding setting in the 3rd connection pad diagonal angle, second connection pad then with the corresponding setting in the 4th connection pad diagonal angle.
In one embodiment of this invention, first line layer is the layer that reroutes.
In one embodiment of this invention, comprise that also a plurality of first electrically connects part (electrical connectionelement), it is disposed between first chip and second circuit base plate, to electrically connect first line layer of first chip and second circuit base plate.
In one embodiment of this invention, each first electric connection part is a conductive projection (conductivebump).
In one embodiment of this invention, comprise that also a plurality of second electrically connects part, it is disposed between second chip and second circuit base plate, to electrically connect second line layer of second chip and second circuit base plate.
In one embodiment of this invention, each second electric connection part is a conductive projection.
In sum, because second circuit base plate has first line layer and second line layer, and first chip and second chip can be respectively by first line layer and second line layer and be electrically connected to first circuit base plate, so compare with prior art, first chip and second chip do not need the extra layer that reroutes of making again.Therefore, the cost of manufacture of multi-chip stacking packaging body is lower, and the utilance that cuts into the wafer of first chip and second chip is promoted.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 is the generalized section of existing a kind of multi-chip stacking packaging body.
Fig. 2 is the generalized section of a kind of multi-chip stacking packaging body of one embodiment of the invention.
Fig. 3 is the exploded perspective view of first chip among Fig. 2, second circuit base plate and second chip.
Fig. 4 is the following view of second circuit base plate among Fig. 3.
Fig. 5 is the top view of second circuit base plate among Fig. 3.
Fig. 6 is the generalized section of a kind of multi-chip stacking packaging body of another embodiment of the present invention.
The main element symbol description:
100,200,600: the multi-chip stacking packaging body
110: circuit base plate
112: the first conductive channels
114: the second conductive channels
120,220: the first chips
122,224: the first connection pads
130,240: the second chips
132,226: the second connection pads
140: the first bonding wires
150: the second bonding wires
160,214: soldered ball
210: the first circuit base plates
212,232: dielectric layer
214a: first soldered ball
214b: second soldered ball
222: the first active faces
230: the second circuit base plates
234: the first line layers
234a: first circuit
234b: second circuit
236: the second line layers
236a: tertiary circuit
236b: the 4th circuit
242: the second active faces
244: the three connection pads
246: the four connection pads
252: the first conductive support
254: the second conductive support
260: the first electric connection parts
270: the second electric connection parts
610: knitting layer
622: the three conductive support
624: the four conductive support
D1: first spacing
D2: second spacing
D3: the 3rd spacing
D4: the 4th spacing
G1, G2, G3, G4, G5, G6: distance
G7, G8: length
H1, H2: highly
L1: first conductive trace
L2: second conductive trace
L3: the 3rd conductive trace
L4: the 4th conductive trace
P1: the first peripheral connection pad
P2: the second peripheral connection pad
P3: the 3rd peripheral connection pad
P4: surrounding connection pad
P5: the 5th connection pad
P6: the 6th connection pad
P7: the 7th connection pad
P8: the 8th connection pad
S1, S2: stacked structure
T1, T3: first conductive channel
T2, T4: second conductive channel
Embodiment
Fig. 2 is the generalized section of a kind of multi-chip stacking packaging body of one embodiment of the invention.Fig. 3 is the exploded pictorial stereogram of first chip among Fig. 2, second circuit base plate and second chip.
Please be simultaneously with reference to Fig. 2 and Fig. 3, multi-chip stacking packaging body 200 comprises one first circuit base plate 210, for example being printed circuit board (PCB), one first chip 220, for example is memory chip, one second circuit base plate 230 and one second chip 240, for example is memory chip.First chip 220 is disposed on the upper surface of first circuit base plate 210, first chip 220 has one first active face 222, first active face 222 is towards the first direction away from this first circuit base plate 210, and the directly contact of the upper surface (not illustrating) of first circuit base plate 210 of getting along well.
Second circuit base plate 230 is disposed on first active face 222 of first chip 220, and second circuit base plate 230 comprises a dielectric layer 232, one first line layer 234 and one second line layer 236, and wherein first line layer 234 for example is the layer that reroutes.First line layer 234 is electrically connected to first chip 220 and first circuit base plate 210.Second line layer 236 is electrically connected to first circuit base plate 210, and first line layer 234 and second line layer 236 are disposed at the relative both sides of dielectric layer 232 respectively.Second chip 240 is disposed on second circuit base plate 230, and second chip 240 is electrically connected to second line layer 236.Second chip 240 has one second active face 242, and the formation of second active face 242 is the second directions towards second circuit base plate 230, and second direction is parallel to each other with first direction and is opposite, meaning promptly first active face 222 towards first line layer, 234, the second active faces 242 towards second line layer 236.
From the above, because second circuit base plate 230 of present embodiment has first line layer 234 and second line layer 236, and first chip 220 and second chip 240 can be respectively by first line layer 234 and second line layer 236 and be electrically connected to first circuit base plate 210, so compare with prior art, first chip 220 of present embodiment and second chip 240 do not need the extra layer that reroutes of making again.Therefore, the cost of manufacture of the multi-chip stacking packaging body 200 of present embodiment is lower, and the utilance that cuts into the wafer of first chip and second chip is promoted.
Below explain for the thin bilge construction of the multi-chip stacking packaging body 200 of present embodiment.In the present embodiment, multi-chip stacking packaging body 200 comprises that also at least one first conductive support 252, at least one second conductive support 254, at least one first electrically connect part 260, at least one second and electrically connect part 270.First circuit base plate 210 also can have a plurality of soldered balls 214, is schematic illustration at this, so enumerate at least one first soldered ball 214a and at least one second soldered ball 214b at this.These first conductive support 252 (its material comprises gold) are disposed between second circuit base plate 230 and first circuit base plate 210, and these second conductive support 254 (its material comprises gold) are disposed between second circuit base plate 230 and first circuit base plate 210 equally.These first electric connection parts 260 (for example being conductive projection) are disposed between first chip 220 and second circuit base plate 230, to electrically connect first chip 220 and first line layer 234.These second electric connection parts 270 (for example being conductive projection) are disposed between second chip 240 and second circuit base plate 230, to electrically connect second chip 240 and second line layer 236.The first soldered ball 214a, the second soldered ball 214b are disposed at the lower surface of first circuit base plate 210, away from a side of first chip 220.
With regard to first circuit base plate 210, first circuit base plate 210 has a dielectric layer 212, at least one first conductive channel T3 and at least one second conductive channel T4.These first conductive channel T3 and these second conductive channels T4 all can run through dielectric layer 212 so that the first conductive channel T3 electrically connects first conductive support 252 and the first soldered ball 214a, and the second conductive channel T4 electrically connects second conductive support 254 and the second soldered ball 214b.In detail, with regard to relative position shown in Figure 2, second conductive support 254 that connects the left side and the height of the second conductive channel T4 of the second soldered ball 214b in left side are same as the height of the first conductive channel T3 of the first soldered ball 214a on first conductive support 252 that is connected the right side and right side approximately.Therefore, compare with prior art, the first conductive channel T3 and the second conductive channel T4 need not to do the coiling design in first circuit base plate 210, then can avoid the problem of signal delay.
Refer again to the 2nd and Fig. 3, first chip 220 also has at least one first connection pad 224 (Fig. 3 schematically illustrates two) and at least one second connection pad 226 (Fig. 3 schematically illustrates two) that is disposed on first active face 222.Second chip 240 also has at least one the 3rd connection pad 244 (Fig. 3 schematically illustrates two) and at least one the 4th connection pad 246 (Fig. 3 schematically illustrates two) that is disposed on second active face 242.The diagonal angle, position of each first connection pad 224 is corresponding to the position of these the 3rd connection pads 244, and the diagonal angle, position of each second connection pad 226 is corresponding to the position of these the 4th connection pads 246.
In addition, with regard to second circuit base plate 230, second circuit base plate 230 has at least one first conductive channel T1 (Fig. 3 schematically illustrates two) and at least one second conductive channel T2 (Fig. 3 schematically illustrates two).These first conductive channel T1 and these second conductive channels T2 run through the dielectric layer 232 of second circuit base plate 230 so that the first conductive channel T1 electrically connects first line layer 234 and second line layer, 236, the second conductive channel T2 electrically connect first line layer 234 and one second line layer 236.
Below be further described for the electrical connection of above-mentioned these members.In the present embodiment, each first connection pad 224 is electrically connected to first circuit base plate 210 by the first circuit 234a of correspondence with the first corresponding conductive support 252.In detail, each first connection pad 224 is electrically connected to first circuit base plate 210 by the first electric connection part 260 of correspondence, corresponding the 5th connection pad P5, the first corresponding conductive trace L1, the first corresponding peripheral connection pad P1 with the first corresponding conductive support 252 in regular turn.
Each second connection pad 226 is electrically connected to first circuit base plate 210 by the second circuit 234b of correspondence with the second corresponding conductive support 254.In detail, each second connection pad 226 is electrically connected to first circuit base plate 210 by the first electric connection part 260 of correspondence, corresponding the 6th connection pad P6, the second corresponding conductive trace L2, the second corresponding peripheral connection pad P2 with the second corresponding conductive support 254 in regular turn.
Each the 3rd connection pad 244 is electrically connected to first circuit base plate 210 by the tertiary circuit 236a of correspondence, the first corresponding conductive channel T1 with the first corresponding conductive support 252.In detail, each the 3rd connection pad 244 can electrically connect the 7th connection pad P7 of part 270, correspondence, corresponding the 3rd conductive trace L3, the 3rd peripheral connection pad P3 of correspondence, the first corresponding conductive channel T1, the first corresponding peripheral connection pad P1 by second of correspondence in regular turn and be electrically connected to first circuit base plate 210 with the first corresponding conductive support 252.
Each the 4th connection pad 246 is electrically connected to first circuit base plate 210 by the 4th circuit 236b of correspondence, the second corresponding conductive channel T2 with the second corresponding conductive support 254.In detail, each the 4th connection pad 246 can electrically connect the 8th connection pad P8 of part 270, correspondence, corresponding the 4th conductive trace L4, the surrounding connection pad P4 of correspondence, the second corresponding conductive channel T2, the second corresponding peripheral connection pad P2 by second of correspondence in regular turn and be electrically connected to first circuit base plate 210 with the second corresponding conductive support 254.
Fig. 4 is the bottom view of second circuit base plate among Fig. 3.Fig. 5 is the top view of second circuit base plate among Fig. 3.Please refer to Fig. 2, Fig. 3, Fig. 4 and Fig. 5, in present embodiment, the width of the first circuit 234a is more than or equal to 20 microns and be less than or equal to 40 microns, the width of the second circuit 234b more than or equal to 20 microns and be less than or equal to 40 microns, the width of tertiary circuit 236a more than or equal to 20 microns and be less than or equal to 40 microns width with the 4th circuit 236b more than or equal to 20 microns and be less than or equal to 40 microns.In addition, the material of first line layer 234 and second line layer 236 comprises copper, and the conductivity of copper is than Jin Weijia.In addition, the making of second circuit base plate 230 does not need to carry out in dust free room.Therefore, compare with the layer that reroutes of the chip of prior art, the efficient of second circuit base plate, 230 transmission signals of present embodiment is preferable and cost of manufacture is lower.
In present embodiment, one first space D 1 between each first connection pad 224 and corresponding second connection pad 226 is greater than zero and be less than or equal to 100 microns.One the 3rd space D 3 between each the 5th connection pad P5 and corresponding the 6th connection pad P6 is greater than zero and be less than or equal to 100 microns.One second space D 2 between each the 3rd connection pad 244 and corresponding the 4th connection pad 246 is greater than zero and be less than or equal to 100 microns.One the 4th space D 4 between each the 7th connection pad P7 and corresponding the 8th connection pad P8 is greater than zero and be less than or equal to 100 microns.In addition, the length (that is apart from G1, G2 and G3 sum) of each first circuit 234a equals the length (that is apart from G4, G5 and G6 sum) of each second circuit 234b, and the length G7 of each tertiary circuit 236a equals the length G8 of each the 4th circuit 236b.In addition, the length (that is apart from G1, G2 and G3 sum) height H 1 and that equal each first circuit 234a of the length G7 of each tertiary circuit 236a and the corresponding first conductive channel T1, and the height H 2 of the length G8 of each the 4th circuit 236b and the second conductive channel T2 with equal respectively the length of second circuit 234b (that is apart from G4, G5 and G6 and).
From the above, the length in the path of transmission signals between the length in the path of transmission signals between each first connection pad 224 and first circuit base plate 210, each second connection pad 226 and first circuit base plate 210, respectively between the 3rd connection pad 244 and first circuit base plate 210 length in the path of transmission signals and respectively between the 4th connection pad 246 and first circuit base plate 210 length in the path of transmission signals identical approximately.Therefore, the multi-chip stacking packaging body 200 of present embodiment can be avoided the problem of the signal delay that existing multi-chip stacking packaging body 100 had.
Fig. 6 is the generalized section of a kind of multi-chip stacking packaging body of another embodiment of the present invention.Please refer to Fig. 6, multi-chip stacking packaging body 600 is similar to multi-chip stacking packaging body 200 (please refer to Fig. 2), and the difference part only is that multi-chip stacking packaging body 600 has two groups of stacked structure S1, S2 that are made of first chip 220, second circuit base plate 230 and second chip 240.And this stacked structure S1 is positioned on the stacked structure S2, and first chip 220 of stacked structure S1 is disposed on second chip 240 of stacked structure S2 by knitting layer 610.In addition, multi-chip stacking packaging body 600 also comprises at least one the 3rd conductive support 622 and at least one the 4th conductive support 624.These the 3rd conductive support 622 (its material comprises gold) are disposed between second circuit base plate 230 of second circuit base plate 230 of stacked structure S1 and stacked structure S2, to electrically connect these second circuit base plates 230.These the 4th conductive support 624 (its material comprises gold) are disposed between these second circuit base plates 230 equally, to electrically connect these second circuit base plates 230.
In sum, the multi-chip stacking packaging body of embodiments of the invention has one of them of following these advantages at least:
1. because second circuit base plate of embodiments of the invention has first line layer and second line layer, and first chip and second chip can be respectively by first line layer and second line layer and be electrically connected to first circuit base plate, so compare with prior art, first chip of embodiments of the invention and second chip do not need the extra layer that reroutes of making again.Therefore, the cost of manufacture of the multi-chip stacking packaging body of embodiments of the invention is lower, and the utilance that cuts into the wafer of first chip and second chip is promoted.
2. the width of each circuit on second circuit base plate of embodiments of the invention (its scope is between between 20 microns and 40 microns) is the line width (its scope is between 5 microns and 10 microns) greater than the layer that reroutes of the chip of prior art, and the material of each circuit on second circuit base plate comprises copper, and the conductivity of copper is than Jin Weijia.In addition, the making of second circuit base plate does not need to carry out in dust free room.Therefore, compare with the layer that reroutes of the chip of prior art, the efficient of the second circuit base plate transmission signals of embodiments of the invention is preferable and cost of manufacture is lower.
The length in the path of transmission signals between the length in the path of transmission signals between each first connection pad of embodiments of the invention and first circuit base plate, each second connection pad and first circuit base plate, respectively between the 3rd connection pad and first circuit base plate length in the path of transmission signals and respectively between the 4th connection pad and first circuit base plate length in the path of transmission signals identical approximately.Therefore, the multi-chip stacking packaging body of embodiments of the invention can be avoided the problem of the signal delay that existing multi-chip stacking packaging body had.
4. first conductive channel of embodiments of the invention and second conductive channel need not additionally again to doing the coiling design in first circuit base plate, can avoid the problem of the signal delay that existing multi-chip stacking packaging body had equally.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (8)
1. a multi-chip stacking packaging body is characterized in that, comprising:
One first circuit base plate;
One first chip is disposed on this first circuit base plate, and has one first active face, and wherein this first active face is towards the first direction away from this first circuit base plate;
One second circuit base plate, be disposed on this first chip, it comprises a dielectric layer, one first line layer and one second line layer, this first line layer is electrically connected to this first chip and this first circuit base plate, this second line layer is electrically connected to this first circuit base plate, and wherein this first line layer and this second line layer are disposed at the relative both sides of this dielectric layer respectively; And
One second chip is disposed on this second circuit base plate, and is electrically connected to this second line layer, wherein this second chip has one second active face, and this second active face is towards the second direction of this first circuit base plate, and wherein, this first direction is parallel to each other with second direction and is opposite.
2. multi-chip stacking packaging body as claimed in claim 1 is characterized in that, this first circuit base plate has a lower surface, and this lower surface comprises one first soldered ball and one second soldered ball.
3. multi-chip stacking packaging body as claimed in claim 2, it is characterized in that, this first chip has more first connection pad and second connection pad that is disposed on this first active face, and wherein this first connection pad is electrically connected at this first soldered ball, and this second connection pad is electrically connected at this second soldered ball; This second chip also has the 3rd connection pad and the 4th connection pad that is disposed on this second active face, wherein, the 3rd connection pad is electrically connected at this first soldered ball, the 4th connection pad then is electrically connected at this second soldered ball, and this one first connection pad and the corresponding setting in the 3rd connection pad diagonal angle, this second connection pad then with the corresponding setting in the 4th connection pad diagonal angle.
4. as claim 1,2 or 3 described multi-chip stacking packaging bodies, it is characterized in that this first line layer is the layer that reroutes.
5. multi-chip stacking packaging body as claimed in claim 1, it is characterized in that, comprise that also a plurality of first electrically connects part, it is disposed between this first chip and this second circuit base plate, to electrically connect this first line layer of this first chip and this second circuit base plate.
6. multi-chip stacking packaging body as claimed in claim 5 is characterized in that, respectively this first electric connection part is a conductive projection.
7. multi-chip stacking packaging body as claimed in claim 1, it is characterized in that, comprise that also a plurality of second electrically connects part, it is disposed between this second chip and this second circuit base plate, to electrically connect this second line layer of this second chip and this second circuit base plate.
8. multi-chip stacking packaging body as claimed in claim 7 is characterized in that, respectively this second electric connection part is a conductive projection.
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| CN2008100958443A CN101572260B (en) | 2008-04-30 | 2008-04-30 | Multi-chip stacking type packaging body |
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| CN2008100958443A CN101572260B (en) | 2008-04-30 | 2008-04-30 | Multi-chip stacking type packaging body |
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| US10297550B2 (en) * | 2010-02-05 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC architecture with interposer and interconnect structure for bonding dies |
| KR101711045B1 (en) | 2010-12-02 | 2017-03-02 | 삼성전자 주식회사 | Stacked Package Structure |
| CN102637652B (en) * | 2012-04-27 | 2015-04-29 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation, integral semiconductor encapsulation adopting semiconductor encapsulation and manufacture method of semiconductor encapsulation |
| US9252054B2 (en) * | 2013-09-13 | 2016-02-02 | Industrial Technology Research Institute | Thinned integrated circuit device and manufacturing process for the same |
| KR101922885B1 (en) | 2017-12-22 | 2018-11-28 | 삼성전기 주식회사 | Fan-out semiconductor package |
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| CN1728378A (en) * | 2004-07-28 | 2006-02-01 | 希旺科技股份有限公司 | Encapsulation of flash memory chips in pile type, and method |
| CN1823561A (en) * | 2003-07-16 | 2006-08-23 | 麦斯韦尔技术股份有限公司 | Packaging of semiconductor devices for incrased reliability |
| KR20070040869A (en) * | 2005-10-13 | 2007-04-18 | 삼성전자주식회사 | Stack package using metal tools with projection and groove |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1823561A (en) * | 2003-07-16 | 2006-08-23 | 麦斯韦尔技术股份有限公司 | Packaging of semiconductor devices for incrased reliability |
| CN1728378A (en) * | 2004-07-28 | 2006-02-01 | 希旺科技股份有限公司 | Encapsulation of flash memory chips in pile type, and method |
| KR20070040869A (en) * | 2005-10-13 | 2007-04-18 | 삼성전자주식회사 | Stack package using metal tools with projection and groove |
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