CN108550565A - Chip packaging structure and packaging method thereof - Google Patents

Chip packaging structure and packaging method thereof Download PDF

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Publication number
CN108550565A
CN108550565A CN201810303905.4A CN201810303905A CN108550565A CN 108550565 A CN108550565 A CN 108550565A CN 201810303905 A CN201810303905 A CN 201810303905A CN 108550565 A CN108550565 A CN 108550565A
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chip
hole
adapter plate
substrate
pads
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CN201810303905.4A
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Chinese (zh)
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徐健
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华进半导体封装先导技术研发中心有限公司
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Priority to CN201810303905.4A priority Critical patent/CN108550565A/en
Publication of CN108550565A publication Critical patent/CN108550565A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905Shape
    • H01L2224/49051Connectors having different shapes
    • H01L2224/49052Different loop heights
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Abstract

The invention relates to the field of semiconductor technology, and discloses a chip packaging structure and a method thereof. The chip packaging structure comprises the components of a substrate which is used for loading a chip; a patching board which is provided with at least one through hole that penetrates the surface and is arranged on a chip, wherein a plurality of welding spots on the chipare arranged in the through hole, wherein the patching board has conducting lines. The welding spots are connected with the conducting lines through first bonding lines. The conducting lines are connected with the substrate through second bonding lines. In the chip packaging structure, a signal on the chip is introduced to the patching board through the first bonding lines; and then the signal isintroduced to the substrate through the conducting lines and the second bonding lines which are arranged on the patching board beforehand, thereby realizing signal intercommunication. Therefore, introduction of the signal on the chip to the substrate is not required in a long-distance lead arrangement manner is not required, thereby reducing process complexity, improving yield and reducing cost. Furthermore, because the distance of the bonding line in the structure is relatively low, impedance of the signal can be better controlled, and electric performance of a product is improved.

Description

芯片封装结构及封装方法 Chip packaging structure and packaging method

技术领域 FIELD

[0001 ]本发明涉及半导体技术领域,具体涉及一种芯片封装结构及封装方法。 [0001] The present invention relates to semiconductor technology, and particularly relates to a chip package and packaging method.

背景技术 Background technique

[0002]随着科技的不断发展以及消费者对电子产品要求的提高,手机等消费电子产品向着不断多元化、高性能快速发展;尺寸也向着轻、薄、短、小的趋势发展。 [0002] With the continuous development of technology and consumer electronic products require improvement, mobile phones and other consumer electronics products towards increasingly diverse, high-performance rapid development; size also toward light, thin, short, small trend. 因此,也对电子产品中的集成电路提出了更高的要求。 Therefore, also in integrated circuits for electronic products put forward higher requirements.

[0003]现有技术中,集成电路通常通过以下两种途径来缩小产品体积及减轻产品重量: 第一种为SOC (System On Chip),即系统级芯片,将存储器、处理器、模拟电路、数字电路、接口电路等集成在一个芯片上,以实现语音、图像、数据处理等功能;第二种为SIP (System In package),即系统级封装,将各种功能的集成电路芯片组合在一个封装体中,以实现与S0C 相同的功能。 [0003] In the prior art, an integrated circuit is typically reduced by two ways for weight and volume of product: as a first SOC (System On Chip), i.e., system-on-chip, memory, processors, analog circuits, digital circuitry, interfaces and other integrated circuit on a chip, voice, image and data processing functions; the second is a SIP (system in package), i.e., a system in package, the integrated circuit chip in a combination of functions the package in order to achieve the same functionality S0C.

[0004]相比较于S0C,SIP由于其具有灵活度高、集成度高、设计周期短、开发成本低等特点而被广泛应用。 [0004] Compared to S0C, SIP because of its high flexibility, high integration, short design cycles, low cost development is widely used. 但是,由于各种芯片在设计之初采用不同的封装结构,芯片表面的信号Pad分布各不相同,在后期采用SIP封装模块加工时,无法满足原先芯片的封装结构,导致工艺难度大大增加,产品的成品率也大打折扣。 However, due to a variety of different chip packaging structure early in the design, signal distribution Pad chip surface varies, using a SIP processing module package, a package structure can not meet the original chip late, resulting in greatly increased the difficulty of the process, the product the yield is greatly reduced.

[0005]例如:很多DRAM产品,在设计之初采用WBGA的封装结构,芯片的信号Pad分布在芯片的中间。 [0005] For example: many DRAM products used in the beginning of the design WBGA package, chip Pad signal distribution in the middle of the chip. 如果后期采用SIP封装结构,无法在基板的表层进行空腔挖孔操作,只能通过大跨度的打引线操作,将信号引到基板上。 A SIP package if the latter can not be operated in the cavity dug in the surface layer of the substrate, only by the operation leads to play a large span, the signal is introduced onto the substrate. 这样操作的话,引线跨度巨大,工艺风险巨大,而随之伴随的是低的成品率。 Doing so, it leads span a huge, huge risk process, and will be accompanied by a low yield.

发明内容 SUMMARY

[0006]为此,本发明所要解决的技术问题是现有技术中,采用sip封装芯片时,引线跨度大、工艺风险高以及成品率低。 [0006] To this end, the present invention is to solve the technical problems in the prior art, when employed sip packaged chips, wire span, high risk and low yield process.

[0007] 为解决上述技术问题,本发明采用的技术方案如下: [0007] To solve the above problems, the present invention employs the following technical solutions:

[0008] 根据第一方面,本发明实施例提供了一种芯片封装结构,包括: [0008] According to a first aspect, the present invention provides a chip package structure, comprising:

[0009] 基板,用于装载芯片; [0009] substrates, for loading the chip;

[0010] 转接板,具有至少一个穿透表面的通孔,设置于所述芯片上,所述芯片上的若干焊点位于所述通孔内; [0010] The adapter plate having a through hole penetrating at least one surface disposed on the chip, a plurality of pads on the chip located in said through hole;

[0011] 所述转接板具有导电线路,所述焊点通过第一键合线与所述导电线路连接,所述导电线路通过第二键合线与所述基板连接。 The [0011] adapter board having a conductive line, and the line connected to the conductive pad by a first bonding wire, the conductive line is connected via a second bonding wire and the substrate.

[0012] 可选地,所述导电线路设置于所述转接板的表面或者内部。 [0012] Alternatively, the conductive trace disposed on the inner surface or the adapter plate.

[0013] 可选地,所述导电线路的数量与所述焊点的数量相同,且所述导电线路的两端均设置有暴露在所述转接板上表面的焊盘,同一所述导电线路两端的所述焊盘分别通过所述键合线连接所述焊点和所述基板。 [0013] Alternatively, the same number of the pads of the conductive line, and both ends of the conductive lines are provided with a plate surface of the adapter pad, the same conductive exposure the pad across the line wires respectively connected to said bonding pads of said substrate and said through.

[0014] 可选地,所述通孔的数量为一个,所述焊点均位于所述通孔内。 [0014] Alternatively, the number of the through hole is a, the pads are located in the through hole.

[0015] 可选地,所述通孔数量与所述焊点的数量相同,每个所述焊点各自位于与其对应的所述通孔内。 [0015] Alternatively, the number of via holes and the number of pads of the same, each of said pads are each located in the corresponding through hole.

[0016] 可选地,所述转接板为硅板或玻璃板或高分子材料板中的至少一种或多种层叠组合。 [0016] Alternatively, the adapter plate is at least one or more combinations of a silicon plate or a laminated glass plate or a polymeric material.

[0017] 可选地,所述转接板的棱角为平滑的圆弧角。 [0017] Alternatively, the adapter plate is smooth angular arc angle.

[0018] 可选地,所述转接板通过焊接或贴装或粘合连接于所述芯片上。 [0018] Alternatively, the adapter plate by welding or adhesive connection or mounted on the chip.

[0019] 可选地,所述焊点与所述通孔孔壁之间的距离不小于5〇um。 [0019] Alternatively, the distance between the pads and the through hole wall is not less than 5〇um.

[0020] 根据第二方面,本发明实施例提供了一种芯片封装方法,包括以下步骤: [0020] According to a second aspect, embodiments of the present invention provides a method of chip package, comprising the steps of:

[0021] 提供一带有通孔的转接板; [0021] The adapter plate provided with a through hole;

[0022] 在所述转接板表面布线,形成导电线路; [0022] surface of the wiring board in the adapter, forming a conductive circuit;

[0023] 将转接板设置在芯片表面,并使得所述芯片上的焊点位于所述通孔内露出; [0023] The adapter plate provided on the chip surface, and such that the pads on the chip is exposed in said through hole;

[0024] 通过第一键合线连接所述焊点与所述导电线路,通过第二键合线连接所述导电线路与所述基板连接。 [0024] The connecting pad and the conductive line through a first bonding wire connecting the conductive trace connected to the substrate through the second bonding wire.

[0025] 本发明的技术方案,具有如下优点: [0025] aspect of the present invention has the following advantages:

[0026]根据第一方面,本发明实施例提供的芯片封装结构,芯片装载于基板上,转接板设置于芯片上,且在转接板上开设穿透表面的通孔,芯片上的若干焊点均位于通孔内,转接板上具有导电线路,芯片上的焊点可以通过第一键合线与导电线路连接,并且导电线路可以通过第二键合线与基板连接。 [0026] According to a first aspect, the chip package structure according to an embodiment of the present invention, a chip mounted on the substrate, the adapter plate disposed on the chip, and defines a through hole penetrating the surface of the adapter plate, a plurality of on-chip pads are located in the through hole, the adapter board with conductive traces, pads on the chip by bonding wires connected to the first conductive line and second conductive line may be a bond wire connected to the substrate through. 即是说,该芯片封装结构中,通过第一键合线将芯片上的信号引至转接板上,再经由转接板上预先设置好的导电线路以及第二键合线,将信号引至基板, 实现信号的互联。 That is, the chip package structure, by a first bonding wire lead on the chip signal to the adapter plate, and then set a good bonding and a second conductive trace lines via the adapter board in advance, the signal primer to the substrate, interconnected signal. 由此,无需通过大跨度打引线的方式将芯片上的信号引至基板上,降低了工艺的复杂性,提高了成品率,降低了成本。 Thus, the leads by way of Long Span without beat signal lead on the chip to the substrate, reducing the complexity of the process, improve the yield, reducing the cost. 同时,由于该结构中的键合线跨度较小,可以更好的管控信号的阻抗,提高了产品的电性能。 Meanwhile, since the structure of the narrow span of the bonding wires, impedance control signals can better improve the electrical properties of the product.

[0027]根据第一方面,本发明实施例提供的芯片封装结构,导电线路可以设置于转接板的表面,也可以设置于转接板的内部。 [0027] According to a first aspect, the chip package structure according to an embodiment of the present invention, the conductive line may be disposed on the surface of the adapter plate, may be provided inside the adapter plate. 将导电线路设置于转接板表面时,工艺难度较低,可操作性强;将导电线路设置于转接板内部时,有利于保护导电线路不受外界破坏。 When the conductive traces disposed on the surface of the adapter plate, a lower difficulty of the process, easy to operate; conductive traces disposed inside the adapter plate, it is advantageous to protect the conductive circuit from external damage. 用户可根据实际需求对导电线路的位置进行设置,可选择性高。 The user can set the position of the conductive lines according to the actual needs, select high.

[0028]根据第一方面,本发明实施例提供的芯片封装结构,导电线路的数量与焊点数量相同,芯片上的每个焊点均具有与其对应的导电线路,导电线路的两端设置有焊盘,第一键合线的两端分别连接芯片上的焊点以及与之对应的导电线路一端的焊盘,另一端的焊盘则连接基板。 [0028] According to a first aspect, the chip package structure according to an embodiment of the present invention, the number of conductive lines with the same number of solder joints, each of the pads on the chip has a corresponding conductive trace, conductive traces are provided at both ends both ends of the pad, the first bonding wire and solder pads are connected to one end of the corresponding conductive lines on the chip, and the other end is connected to the substrate pads. 由此,有利于实现键合线的有序连接,避免线路的紊乱。 This is advantageous in order to achieve bonding wire is connected, to avoid disturbance of the line.

[0029]根据第一方面,本发明实施例提供的芯片封装结构,通孔仅有一个,焊点均位于通孔内,由此,在转接板上仅需形成一个通孔,简化了工序,降低了制作难度;另外,通孔的数量也可以与焊点的数量相同,每个焊点各自位于与其对应的通孔内,即,焊点与通孔——对应,由此,打线过程中,有利于键合线与焊点的对位,避免键合线连接到其他焊点上而造成连线的杂乱。 [0029] According to a first aspect, the chip package structure according to an embodiment of the present invention, only one through-hole pads are located in the through hole, whereby, the adapter board only a through hole is formed, the step is simplified reduced production of the difficulty; Further, the number of vias may be same as the number of pads, each pad located on each through-hole corresponding thereto, i.e., pads and through-holes - corresponding to, thereby, wire process, and facilitate the bonding pads on the bit line, to avoid the bonding wire is connected to the other connection pad caused by clutter.

[0030]根据第一方面,本发明实施例提供的芯片封装结构,转接板的棱角为平滑的圆弧角。 [0030] According to a first aspect, the edges of the chip package structure embodiment provided, the adapter plate of the embodiment of the present invention is a smooth arc angle. 由于第一键合线和第二键合线会接触到转接板侧面的棱角,如果棱角太尖锐,有可能会磨损第一键合线和第二键合线,从而造成键合线的破损,影响导电性能。 Since the first bonding wire and the second bonding wire to come into contact with the side edges of the adapter plate, if the edges are too sharp, there may be wear of the first bonding wire and the second bonding wire, thereby resulting in breakage of the bonding wire affect conductivity. 本发明实施例将转接板的棱角设置为平滑的圆弧角,有利于避免第一键合线和第二键合线被尖锐的棱角所磨损。 EXAMPLE The adapter plate edges embodiment of the present invention is provided a smooth arc angle, it is advantageous to avoid the first bonding wire and the second bonding wire is worn by sharp edges.

[0031]根据第一方面,本发明实施例提供的芯片封装结构,焊点与通孔孔壁之间的距离不小于50WI1。 [0031] According to a first aspect, the distance between the chip package, the through hole wall pads provided in the embodiment of the present invention is not less than 50WI1. 即,为后期打线工艺提供了一定的安全距离,保证第一键合线可顺利连接到芯片焊点上,而不会因空间过小而难以操作。 That is, for the latter to provide a wire bonding process of a safe distance, to ensure that the first bonding wire can be smoothly connected to the chip pad, and the space is too small will not be difficult to handle.

[0032] 根据第二方面,本发明实施例提供的芯片封装方法,包括以下步骤:提供一带有通孔的转接板;在转接板表面布线,形成导电线路;将转接板设置在芯片表面,并使得芯片上的焊点位于通孔内露出;通过第一键合线连接焊点与导电线路,通过第二键合线连接导电线路与基板连接。 [0032] According to a second aspect, chip packaging method according to an embodiment of the present invention, comprising the steps of: providing an adapter plate having a through hole; a surface of the wiring in the adapter plate, forming a conductive circuit; chip provided on the adapter plate surface, and positioned such that the pads on the chip are exposed through hole; pads connected to the conductive wiring through the first bonding wire connected to the conductive line and a second substrate are connected by bonding wires. 通过该芯片封装方法,通过第一键合线将芯片上的信号引至转接板上,再经由转接板上预先设置好的导电线路以及第二键合线,将信号引至基板,实现信号的互联。 By this method of chip packaging, the first bonding wire lead on the chip signal to the adapter plate, and then set a good bonding and a second conductive trace lines via the adapter board in advance, the lead signal to the substrate, to achieve Internet signal. 由此,无需通过大跨度打引线的方式将芯片上的信号引至基板上,降低了工艺的复杂性,提高了成品率,降低了成本。 Thus, the leads by way of Long Span without beat signal lead on the chip to the substrate, reducing the complexity of the process, improve the yield, reducing the cost. 同时,由于该结构中的键合线跨度较小,可以更好的管控信号的阻抗,提尚了广品的电性能。 Meanwhile, since the structure of the narrow span of the bonding wires, impedance can be better control signals, provide electrical performance still wide product.

附图说明 BRIEF DESCRIPTION

[0033]为了更清楚地说明本发明具体实施方式或现有技术中的技术方案,下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0033] In order to more clearly illustrate the accompanying drawings specific embodiments of the present invention or the prior art technical solution, or the following specific embodiments will be described in the prior art are required simply introduced hereinafter, described below the drawings are in some embodiments of the present invention, those of ordinary skill in the art is concerned, without creative efforts, can obtain other drawings based on these drawings.

[0034]图1为本发明实施例1提供的芯片封装结构的俯视图; [0034] FIG. 1 is a plan view of a chip package provided in Example 1 of the present invention;

[0035]图2为本发明实施例1提供的芯片封装结构的剖视图; [0035] FIG. 2 is a sectional view of a chip package structure according to an embodiment of the present invention provides;

[0036]图3为本发明实施例1提供的芯片封装结构中转接板的结构示意图; [0036] Fig 3 a schematic view of the structure of a chip package structure embodiment provided by the adapter plate of the embodiment of the invention;

[0037]图4为本发明实施例1提供的芯片封装结构的另一实施方式的结构示意图; [0037] FIG. 4 schematic structural diagram of another embodiment of a chip package structure according to an embodiment of the present invention provides;

[0038]图5为本发明实施例1提供的芯片封装结构的又一实施方式的结构示意图; [0038] FIG. 5 schematic structural diagram of another embodiment of a chip package structure of an embodiment 1 of the embodiment of the present invention provides;

[0039]附图标记: [0039] reference numerals:

[0040] 1-基板;2-芯片;3-转接板;31-通孔;32-焊点;33-导电线路;34-焊盘;4-第一键合线;5-第二键合线。 [0040] 1- substrate; 2- chip; 3- adapter plate; 31- through hole; 32- pads; 33- conductive trace; 34- pad; 4- first bond wire; 5- second key wires.

具体实施方式 Detailed ways

[0041]下面将结合附图对本发明的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。 [0041] The following with reference to the aspect of the present invention are clearly and completely described, obviously, the described embodiments are part of the embodiments of the present invention rather than all embodiments. 基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments of ordinary skill in the art without any creative effort shall fall within the scope of the present invention. [0042]在本发明的描述中,需要说明的是,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性。 [0042] In the description of the present invention, it is explained that the terms "first", "second" are for illustrative purposes only, and not intended to indicate or imply relative importance.

[0043]此外,下面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。 [0043] The technical features of the different embodiments of the invention described below as long as it is not involved in a conflict with each other can be bonded to each other.

[0044] 实施例1 [0044] Example 1

[0045] 本发明实施例公开了一种芯片封装结构,如图1所示,包括基板1、芯片2以及转接板3。 Embodiment [0045] The present invention discloses a chip package structure, shown in Figure 1, comprises a substrate 1, chip 2 and 3 the adapter plate. 其中, among them,

[0046]基板1用于装载芯片2,一般地,芯片2可以贴装在基板1上。 [0046] The substrate 1 for loading chip 2, generally, the chip 2 may be mounted on the substrate 1.

[0047] 转接板3设置于芯片2上,其具有至少一个穿透表面的通孔31,芯片2上的若干焊点32位于通孔31内。 [0047] The adapter plate 3 on the chip 2 is provided, having at least one through hole penetrating the surface 31, a plurality of pads on the chip 232 is located within the through hole 31. 一般地,转接板3可以通过焊接方式连接于芯片2上,也可以采用贴装或粘合方式连接于芯片2上,在此不做限制。 Generally, the adapter plate 3 may be connected by soldering to the chip 2, it can also be used to mount or adhesively connected to the chip 2, which is not limited.

[0048]作为本发明的一种优选实施方式,转接板3为硅板或玻璃板或高分子材料板中的至少一种或多种层叠组合。 [0048] As a preferred embodiment of the present invention, the adapter plate 3 is at least one or more combinations of a silicon plate or a laminated glass plate or a polymeric material. 用户可根据实际需求选择转接板的材料和种类,在此不做限制。 The user can choose according to the actual needs of the type of materials and the adapter plate, which is not limited. [0049]如图1-3所示,转接板3具有导电线路33,焊点32通过第一键合线4与导电线路33连接,导电线路33通过第二键合线5与基板1连接。 [0049] As shown in Figure 1-3, the adapter plate 3 having the conductive line 33, the conductive pad 324 is connected to line 33 via a first bonding wire, a conductive line 33 through the second bonding wire 5 is connected to the substrate 1 . 其中,第一键合线4和第二键合线5可以为金线、银线或铜线等。 Wherein the first bonding lines 4 and 5 may be the second bond wire as the gold, silver or copper.

[0050]该芯片封装结构中,通过第一键合线4将芯片2上的信号引至转接板3上,再经由转接板3上预先设置好的导电线路33以及第二键合线5,将信号引至基板1,实现信号的互联。 [0050] The chip package structure, by a first signal on the second chip bond wire lead 4 to the adapter plate 3, and then through the adapter plate 3 is set in advance on a good conductive trace 33 and the second bond wire 5, the signal primer to the substrate 1, interconnected signal. 由此,无需通过大跨度打引线的方式将芯片2上的信号引至基板1上,降低了工艺的复杂性, 提高了成品率,降低了成本。 Thus, the leads by way of Long Span without beat signal lead on the chip 2 onto the substrate 1, reducing the complexity of the process, improve the yield, reducing the cost. 同时,由于该结构中的键合线跨度较小,可以更好的管控信号的阻抗,提高了产品的电性能。 Meanwhile, since the structure of the narrow span of the bonding wires, impedance control signals can better improve the electrical properties of the product.

[0051]作为本发明的一种优选实施方式,导电线路33设置于转接板3的表面。 [0051] As a preferred embodiment of the invention, conductive traces 33 disposed on a surface of the adapter plate 3. 如此,工艺难度较低,可操作性强。 Thus, the lower difficulty of the process, easy to operate. 作为可替换实施方式,导电线路33设置于转接板3的内部,如此有利于保护导电线路33不受外界破坏。 As an alternative embodiment, the conductive trace 33 is provided inside the adapter plate 3, and so help protect the conductive wires 33 from external damage. 用户可根据实际需求对导电线路33的位置进行设置,具有可选择性,灵活性高。 According to the actual needs of the user can position the conductive line 33 is provided with selectable, high flexibility.

[0052]作为本发明的一种优选实施方式,导电线路33的数量与焊点32的数量相同,且导电线路33的两端均设置有暴露在转接板3上表面的焊盘34,同一导电线路33两端的焊盘34 分别通过键合线连接焊点32和基板1。 [0052] As a preferred embodiment, the conductive line 33 to the number of pads of the present invention, the same number of 32, and both ends of the conductive lines 33 are provided exposed on the surface of the adapter plate 3 pads 34, the same the conductive pads 34 are connected to both ends of the line 33 and the pads 32 of the substrate 1 by bonding wires. 即,芯片2上的每个焊点32均具有与其对应的导电线路33,第一键合线4的两端分别连接芯片2上的焊点32以及与之对应的导电线路33—端的焊盘34,另一端的焊盘M则连接基板1。 That is, each of the pads 32 on the chip 2 has a corresponding conductive trace 33, both ends of the first bond wire 4 are connected to the pads 32 and the conductive pads 33 on the end of the line the corresponding chip 2 34, the other end is connected to the substrate pads M 1. 由此,有利于实现键合线的有序连接,避免线路的紊乱。 This is advantageous in order to achieve bonding wire is connected, to avoid disturbance of the line.

[0053]作为本发明的一种优选实施方式,通孔31的数量为一个,焊点32均位于通孔31内。 [0053] As a preferred embodiment of the present invention, the number of through-holes 31 a, 31 pads 32 are located in the through hole. 由此,在转接板3上仅需形成一个通孔31,简化了工序,降低了制作难度。 Thereby, a through hole 31 in the adapter plate 3 is formed only simplifies the procedure, reduce the difficulty of production. 作为一种可替换实施方式,通孔31的数量也可以与焊点32的数量相同,如图4所示,每个焊点32各自位于与其对应的通孔31内,S卩,焊点32与通孔31—一对应,由此,打线过程中,有利于键合线与焊点32 的对位,避免键合线连接到其他焊点32上而造成连线的杂乱。 As an alternative embodiment, the number of through holes 31 may be the same as the number of solder joints 32, shown in Figure 4, each pad 32 are each positioned within its corresponding through hole 31, S Jie, solder 32 31- with a corresponding through-hole, whereby the wire during bonding wire and facilitate the alignment pad 32, avoiding the bonding wires 32 are connected to other pads on the connection caused by clutter.

[0054]作为另一种可替换实施方式,如图5所示,通孔31的数量是焊点32数量的二分之一,每两个焊点32共用一个通孔31。 [0054] As another alternative embodiment, shown in FIG. 5, the number of the through-hole 31 is one-half the number of solder joints 32, each of the two pads 32 sharing a through hole 31. 可以是沿x轴方向上两个相邻的焊点32共用一个通孔31,也可以是沿Y轴方向上两个相邻的焊点犯共用一个通孔31,均属于本发明的保护范围。 It may be the x-axis direction of two adjacent pads 32 sharing a through hole 31 may be a Y-axis direction on two adjacent pads share a through hole 31 made, all fall within the scope of the present invention . 另外,也可以是三个焊点32共用一个通孔3丨或四个焊点a共用一个通孔31等均可以实现本发明的目的。 Further, three pads 32 may be a through-hole 3 Shu share or share a four pads 31 a through hole etc. The present invention may be implemented.

[0055]作为本发明的一种优选实施方式,转接板3的棱角为平滑的圆弧角。 [0055] As a preferred embodiment of the present invention, the adapter plate 3 is smoothed edges of the arc angle. 由于第一键合线4和第二键合线5会接触到转接板3侧面的棱角,如果棱角太尖锐,有可能会磨损第一键合线4和第二键合线5,从而造成键合线的破损,影响导电性能。 4 since the first bonding wire and the second bonding wire 5 come into contact with the side edges of the adapter plate 3, if the edges are too sharp, it may become worn first bond wire 4 and the second bonding wire 5, thereby causing bond wire damage, reduce the conductivity. 本发明实施例将转接板3的棱角设置为平滑的圆弧角,有利于避免第一键合线4和第二键合线5被尖锐的棱角所磨损。 Example embodiments of the present invention, the adapter plate 3 is provided to smooth edges of the arc angle, it is advantageous to avoid the first bond wire 4 and a second bonding wire 5 are worn sharp corners. [0056]作为本发明的一种优选实施方式,焊点32与通孔31孔壁之间的距离不小于50wn。 [0056] As a preferred embodiment of the present invention, the distance between the wall of the hole 31 and through hole pads 32 is not less than 50wn. 即,为后期打线工艺提供了一定的安全距离,保证第一键合线4可顺利连接到芯片2焊点32 上,而不会因空间过小而难以操作。 That is, for the latter to provide a wire bonding process of a safe distance, to ensure that the first bonding wire 4 can be smoothly connected to the chip pads 32 2, and the space is too small will not be difficult to handle.

[0057]本实施例中,转接板3的厚度可以小于等于l〇〇ym。 [0057] In this embodiment, the thickness of the adapter plate 3 may be less l〇〇ym. 转接板3厚度在此数值范围内时,转接板3对整个芯片封装厚度的影响较小。 The thickness of the adapter plate 3 is within this numerical range, the adapter plate smaller chip package affects the entire thickness of 3 pairs.

[0058] 实施例2 [0058] Example 2

[0059]本发明实施例公开了一种芯片封装方法,包括以下步骤: [0059] Embodiments of the present invention discloses a method of chip package, comprising the steps of:

[0060]步骤S21、提供一带有通孔31的转接板3。 [0060] step S21, the adapter providing a plate 31 with through holes 3. 其中,通孔31的数量至少为一个,转接板3 的厚度可以小于等于100M1,转接板3可以为硅板或玻璃板或高分子材料板中的至少一种或多种层叠组合。 Wherein the number of the through-hole 31 is at least a thickness of the adapter plate 3 may be less than or equal 100m1, the adapter plate 3 may be at least one or more combinations of a silicon plate or a laminated glass plate or a polymeric material.

[0061] 步骤S22、在转接板3表面布线,形成导电线路33。 [0061] Step S22, the transfer surface of the wiring board 3, the conductive line 33 is formed.

[0062]需要说明的是,导电线路33也可以预先形成在转接板3的内部。 [0062] Incidentally, the conductive lines 33 may be previously formed inside the adapter plate 3.

[0063]步骤S23、将转接板3设置在芯片2表面,并使得芯片2上的焊点32位于通孔31内露出。 [0063] Step S23, the adapter plate 3 is provided on the surface of the chip 2, and so that the pads on the chip 232 is located within through-hole 31 is exposed.

[0064] 步骤S24、通过第一键合线4连接焊点32与导电线路33,通过第二键合线5连接导电线路33与基板1连接。 [0064] Step S24, the connection pads 32 to conductive traces 33 via a first bonding wire 4, the conductive line 33 is connected to the substrate 1 via a second bonding wire 5. 其中,第一键合线4和第二键合线5可以为金线、银线或铜线等。 Wherein the first bonding lines 4 and 5 may be the second bond wire as the gold, silver or copper.

[0065] 通过该芯片封装方法,通过第一键合线4将芯片2上的信号引至转接板3上,再经由转接板3上预先设置好的导电线路33以及第二键合线5,将信号引至基板1,实现信号的互联。 [0065] By this method of chip packaging, bonding the first 4-chip signal on the line lead 2 to the adapter plate 3, and then through the adapter plate 3 is set in advance on a good conductive trace 33 and the second bond wire 5, the signal primer to the substrate 1, interconnected signal. 由此,无需通过大跨度打引线的方式将芯片2上的信号引至基板1上,降低了工艺的复杂性,提高了成品率,降低了成本。 Thus, the leads by way of Long Span without beat signal lead on the chip 2 onto the substrate 1, reducing the complexity of the process, improve the yield, reducing the cost. 同时,由于该结构中的键合线跨度较小,可以更好的管控信号的阻抗,提高了产品的电性能。 Meanwhile, since the structure of the narrow span of the bonding wires, impedance control signals can better improve the electrical properties of the product.

[0066] 显然,上述实施例仅仅是为清楚地说明所作的举例,而并非对实施方式的限定。 [0066] Clearly, the above-described embodiments are merely made to clearly illustrate example, and not limited to the embodiment. 对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。 Those of ordinary skill in the art, on the basis of the above described variations or changes may be made in various other forms. 这里无需也无法对所有的实施方式予以穷举。 It is unnecessary and can not be exhaustive of all embodiments. 而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。 The obvious changes or variations therefrom corollary is still in the scope of the inventions.

Claims (10)

1.一种芯片封装结构,其特征在于,包括: 基板(1),用于装载芯片(2); 转接板(3),具有至少一个穿透表面的通孔(31),设置于所述芯片(2)上,所述芯片(2) 上的若干焊点(32)位于所述通孔(31)内; 所述转接板(3)具有导电线路(33),所述焊点(32)通过第一键合线(4)与所述导电线路(33)连接,所述导电线路(33)通过第二键合线(5)与所述基板(1)连接。 1. A chip package structure, comprising: a substrate (1), for loading chip (2); the adapter plate (3) having a through hole (31) penetrating the at least one surface is provided to the on said chip (2), a plurality of chip pads (32) (2) located within the through hole (31); said adapter plate (3) having a conductive trace (33), said welds (32) is connected via a first bonding wire (4) and the conductive line (33), said conductive trace (33) connected by a second bonding wire (5) and the substrate (1).
2. 根据权利要求1所述的芯片封装结构,其特征在于,所述导电线路(3¾设置于所述转接板⑶的表面或者内部。 2. The chip package structure according to claim 1, wherein said electrically conductive line (3¾ adapter disposed on the surface or the interior panel ⑶.
3. 根据权利要求1所述的芯片封装结构,其特征在于,所述导电线路(33)的数量与所述焊点(32)的数量相同,且所述导电线路(33)的两端均设置有暴露在所述转接板(3)上表面的焊盘(34),同一所述导电线路(33)两端的所述焊盘(34)分别通过所述键合线连接所述焊点(32)和所述基板(1)。 The chip package structure according to claim 1, characterized in that the same number of said conductive trace (33) and said pad (32), and both ends of the conductive traces (33) are is provided with a pad (34) exposed at the adapter plate (3) on the surface of the pad of the same conductive line (34) (33) are connected to the two ends of said pads through bonding wires (32) and the substrate (1).
4. 根据权利要求1所述的芯片封装结构,其特征在于,所述通孔(31)的数量为一个,所述焊点(32)均位于所述通孔(31)内。 4. The chip package structure according to claim 1, wherein the number of said through hole (31) is one of a solder joint (32) are located in the through hole (31).
5. 根据权利要求1所述的芯片封装结构,其特征在于,所述通孔(31)数量与所述焊点(32)的数量相同,每个所述焊点(32)各自位于与其对应的所述通孔(31)内。 The chip package structure as claimed in claim 1, characterized in that the same number of the pads (32) of said through hole (31), each of said pads (32) are each located in its corresponding within the through hole (31).
6. 根据权利要求1所述的芯片封装结构,其特征在于,所述转接板(3)为硅板或玻璃板或高分子材料板中的至少一种或多种层叠组合。 6. The chip package structure as claimed in claim 1, wherein the adapter plate (3) at least one or more of the laminated combination of a silicon plate or a glass plate or a polymeric material.
7. 根据权利要求1所述的芯片封装结构,其特征在于,所述转接板(3)的棱角为平滑的圆弧角。 7. The chip package structure according to claim 1, wherein the adapter plate (3) is a smooth arc angle corners.
8. 根据权利要求1所述的芯片封装结构,其特征在于,所述转接板(3)通过焊接或贴装或粘合连接于所述芯片(2)上。 8. The chip package structure according to claim 1, wherein the adapter plate (3) by welding or adhesive connection or mounted to the chip (2).
9. 根据权利要求1所述的芯片封装结构,其特征在于,所述焊点(32)与所述通孔(31)孔壁之间的距离不小于5〇Mi。 9. The chip packaging structure according to claim 1, wherein said pad (32) with the through hole (31) the distance between the hole wall is not less than 5〇Mi.
10. —种芯片封装方法,其特征在于,包括以下步骤: 提供一带有通孔(31)的转接板(3); 在所述转接板⑶表面布线,形成导电线路(33); 将转接板(3)设置在芯片(2)表面,并使得所述芯片(2)上的焊点(32)位于所述通孔(31)内露出; 通过第一键合线(4)连接所述焊点(32)与所述导电线路(33),通过第二键合线(5)连接所述导电线路(33)与所述基板(1)连接。 10. - kind of chip packaging method comprising the steps of: providing an adapter plate (3) with through holes (31); ⑶ surface of the wiring in the adapter plate, forming a conductive line (33); and the adapter plate (3) provided in the chip (2) surface, and such that the die pad (32) (2) located in said through-hole (31) is exposed; connected by a first bonding wire (4) the pad (32) and said conductive line (33), said electrically conductive connection line (33) of the substrate (1) via a second bonding wire (5).
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040164413A1 (en) * 2002-07-08 2004-08-26 Hall Frank L. Underfilled, encapsulated semiconductor die assemblies and methods of fabrication
CN104054172A (en) * 2011-11-29 2014-09-17 考文森智财管理公司 Interposer For Stacked Semiconductor Devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040164413A1 (en) * 2002-07-08 2004-08-26 Hall Frank L. Underfilled, encapsulated semiconductor die assemblies and methods of fabrication
CN104054172A (en) * 2011-11-29 2014-09-17 考文森智财管理公司 Interposer For Stacked Semiconductor Devices

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