CN108550565A - Chip-packaging structure and packaging method - Google Patents

Chip-packaging structure and packaging method Download PDF

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Publication number
CN108550565A
CN108550565A CN201810303905.4A CN201810303905A CN108550565A CN 108550565 A CN108550565 A CN 108550565A CN 201810303905 A CN201810303905 A CN 201810303905A CN 108550565 A CN108550565 A CN 108550565A
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China
Prior art keywords
chip
substrate
pads
hole
interposer
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CN201810303905.4A
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Chinese (zh)
Inventor
徐健
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN201810303905.4A priority Critical patent/CN108550565A/en
Publication of CN108550565A publication Critical patent/CN108550565A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H01L2224/49052—Different loop heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The present invention relates to technical field of semiconductors, a kind of chip-packaging structure and method are disclosed, structure includes substrate, for loading chip；Pinboard has at least one through-hole for penetrating surface, is set on chip, several solder joints on chip are located in through-hole；There is pinboard conducting wire, solder joint to be connect with conducting wire by the first bonding line, and conducting wire passes through the second bonding line and substrate connection.In the chip-packaging structure, the signal on chip is led on pinboard by the first bonding line, then via the conducting wire pre-set on pinboard and the second bonding line, signal is led into substrate, realize the interconnection of signal.It is not necessarily to lead to the signal on chip on substrate in such a way that large span plays lead as a result, reduces the complexity of technique, improve yield rate, reduce cost.Simultaneously as the bonding line span in the structure is smaller, can better management and control signal impedance, improve the electrical property of product.

Description

Chip packaging structure and packaging method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip packaging structure and a chip packaging method.
Background
With the continuous development of science and technology and the improvement of the requirements of consumers on electronic products, consumer electronic products such as mobile phones and the like are rapidly developed towards continuous diversification and high performance; the size also tends to be light, thin, short, and small. Therefore, higher demands are also placed on integrated circuits in electronic products.
In the prior art, the integrated circuit usually reduces the volume and weight of the product by two ways: the first is SOC (System On Chip), i.e. System On Chip, in which a memory, a processor, an analog circuit, a digital circuit, an interface circuit, etc. are integrated On one Chip to realize the functions of voice, image, data processing, etc.; the second type is SIP (System in package), which is a System in package, and combines integrated circuit chips having various functions in one package to realize the same function as the SOC.
Compared with the SOC, the SIP is widely used due to its features of high flexibility, high integration level, short design cycle, low development cost, etc. However, since various chips adopt different package structures at the beginning of design, and the signal Pad distribution on the chip surface is different, when an SIP package module is adopted for processing at a later stage, the package structure of the original chip cannot be satisfied, so that the process difficulty is greatly increased, and the yield of products is greatly reduced.
For example: in many DRAM products, a WBGA package structure is adopted at the beginning of design, and a signal Pad of a chip is distributed in the middle of the chip. If the SIP packaging structure is adopted in the later stage, the cavity hole digging operation can not be carried out on the surface layer of the substrate, and the signal can only be led to the substrate through the lead wire punching operation with large span. By doing so, the lead span is large and the process risk is large, with a concomitant low yield.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is that in the prior art, when the SIP packaging chip is adopted, the lead span is large, the process risk is high and the yield is low.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
according to a first aspect, an embodiment of the present invention provides a chip packaging structure, including:
a substrate for loading a chip;
the adapter plate is provided with at least one through hole penetrating through the surface and arranged on the chip, and a plurality of welding spots on the chip are positioned in the through hole;
the adapter plate is provided with a conductive circuit, the welding spot is connected with the conductive circuit through a first bonding wire, and the conductive circuit is connected with the substrate through a second bonding wire.
Optionally, the conductive circuit is disposed on a surface or inside of the interposer.
Optionally, the number of the conductive traces is the same as that of the solder joints, pads exposed on the upper surface of the interposer are disposed at both ends of the conductive traces, and the pads at both ends of the same conductive trace are respectively connected to the solder joints and the substrate through the bonding wires.
Optionally, the number of the through holes is one, and the welding points are all located in the through holes.
Optionally, the number of the through holes is the same as the number of the welding spots, and each welding spot is respectively located in the through hole corresponding to the welding spot.
Optionally, the interposer is at least one or more stacked combinations of a silicon plate, a glass plate, or a polymer material plate.
Optionally, the edge angle of the adapter plate is a smooth arc angle.
Optionally, the interposer is attached to the chip by soldering or mounting or gluing.
Optionally, the distance between the solder joint and the wall of the through hole is not less than 50 μm.
According to a second aspect, an embodiment of the present invention provides a chip packaging method, including the following steps:
providing an adapter plate with a through hole;
wiring on the surface of the adapter plate to form a conductive circuit;
arranging an adapter plate on the surface of a chip, and enabling a welding spot on the chip to be positioned in the through hole and exposed;
and the welding points are connected with the conducting circuit through first bonding wires, and the conducting circuit is connected with the substrate through second bonding wires.
The technical scheme of the invention has the following advantages:
according to a first aspect, in the chip package structure provided in the embodiments of the present invention, a chip is mounted on a substrate, an interposer is disposed on the chip, a through hole penetrating through a surface of the interposer is formed in the interposer, a plurality of pads on the chip are all located in the through hole, a conductive trace is disposed on the interposer, the pads on the chip can be connected to the conductive trace through a first bonding wire, and the conductive trace can be connected to the substrate through a second bonding wire. That is to say, in the chip packaging structure, a signal on the chip is led to the adapter plate through the first bonding wire, and then the signal is led to the substrate through the conductive circuit and the second bonding wire which are preset on the adapter plate, so that the interconnection of the signal is realized. Therefore, signals on the chip are led to the substrate without a large-span lead wire bonding mode, process complexity is reduced, yield is improved, and cost is reduced. Meanwhile, because the span of the bonding wire in the structure is small, the impedance of a control signal can be better, and the electrical property of a product is improved.
According to a first aspect, in the chip package structure provided in the embodiments of the present invention, the conductive traces may be disposed on a surface of the interposer or disposed inside the interposer. When the conducting circuit is arranged on the surface of the adapter plate, the process difficulty is low, and the operability is strong; when the conducting circuit is arranged inside the adapter plate, the conducting circuit is protected from being damaged by the outside. The user can set the position of conducting wire according to actual demand, and the alternative is high.
According to a first aspect, in the chip package structure provided in the embodiments of the present invention, the number of the conductive traces is the same as the number of the pads, each pad on the chip has a conductive trace corresponding to the pad, pads are disposed at two ends of the conductive trace, two ends of the first bonding wire are respectively connected to the pad on the chip and the pad at one end of the conductive trace corresponding to the pad, and the pad at the other end is connected to the substrate. Therefore, the orderly connection of the bonding wires is facilitated, and the disorder of the circuit is avoided.
According to the first aspect, in the chip packaging structure provided by the embodiment of the invention, only one through hole is provided, and the welding spots are all positioned in the through holes, so that only one through hole is formed on the adapter plate, the process is simplified, and the manufacturing difficulty is reduced; in addition, the number of the through holes can be the same as that of the welding spots, and each welding spot is respectively positioned in the through hole corresponding to the welding spot, namely, the welding spots and the through holes are in one-to-one correspondence, so that the alignment of the bonding wire and the welding spots is facilitated in the routing process, and the disorder of connection caused by the fact that the bonding wire is connected to other welding spots is avoided.
According to a first aspect, in the chip package structure provided in the embodiments of the present invention, the corner angle of the interposer is a smooth arc angle. Because the first bonding wire and the second bonding wire can contact the edge angle of the side face of the adapter plate, if the edge angle is too sharp, the first bonding wire and the second bonding wire can be abraded possibly, so that the damage of the bonding wires is caused, and the conductivity is influenced. According to the embodiment of the invention, the edge angle of the adapter plate is set to be a smooth arc angle, so that the first bonding line and the second bonding line are prevented from being worn by sharp edge angles.
According to the first aspect, in the chip package structure provided by the embodiment of the invention, the distance between the solder joint and the wall of the through hole is not less than 50 μm. Namely, a certain safety distance is provided for the later routing process, and the first bonding wire can be smoothly connected to a chip welding spot, so that the situation that the operation is difficult due to the small space is avoided.
According to a second aspect, an embodiment of the present invention provides a chip packaging method, including the following steps: providing an adapter plate with a through hole; wiring on the surface of the adapter plate to form a conductive circuit; arranging the adapter plate on the surface of the chip, and enabling the welding spots on the chip to be positioned in the through holes and exposed; the welding point and the conducting circuit are connected through the first bonding wire, and the conducting circuit is connected with the substrate through the second bonding wire. According to the chip packaging method, signals on the chip are led to the adapter plate through the first bonding wire, and then are led to the substrate through the conductive circuit and the second bonding wire which are preset on the adapter plate, so that signal interconnection is achieved. Therefore, signals on the chip are led to the substrate without a large-span lead wire bonding mode, process complexity is reduced, yield is improved, and cost is reduced. Meanwhile, because the span of the bonding wire in the structure is small, the impedance of a control signal can be better, and the electrical property of a product is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a top view of a chip package structure provided in embodiment 1 of the present invention;
fig. 2 is a cross-sectional view of a chip package structure provided in embodiment 1 of the present invention;
fig. 3 is a schematic structural diagram of a transfer board in the chip packaging structure according to embodiment 1 of the present invention;
fig. 4 is a schematic structural diagram of another embodiment of a chip package structure according to embodiment 1 of the present invention;
fig. 5 is a schematic structural diagram of a chip package structure according to still another embodiment of the present invention in example 1;
reference numerals:
1-a substrate; 2-chip; 3-a patch panel; 31-a through hole; 32-welding points; 33-conductive lines; 34-a pad; 4-a first bond wire; 5-a second bond wire.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
The embodiment of the invention discloses a chip packaging structure, which comprises a substrate 1, a chip 2 and an adapter plate 3 as shown in figure 1. Wherein,
the substrate 1 is used for mounting the chip 2, and generally, the chip 2 may be mounted on the substrate 1.
The interposer 3 is disposed on the chip 2 and has at least one through hole 31 penetrating through the surface, and a plurality of pads 32 on the chip 2 are disposed in the through hole 31. Generally, the interposer 3 may be connected to the chip 2 by soldering, or may be connected to the chip 2 by mounting or bonding, which is not limited herein.
In a preferred embodiment of the present invention, the interposer 3 is at least one or more stacked combinations of silicon plates, glass plates, or polymer material plates. The user can select the material and the type of the adapter plate according to the actual requirement, and the limitation is not made herein.
As shown in fig. 1 to 3, the interposer 3 has a conductive trace 33, the pad 32 is connected to the conductive trace 33 through a first bonding wire 4, and the conductive trace 33 is connected to the substrate 1 through a second bonding wire 5. The first bonding wire 4 and the second bonding wire 5 may be gold wires, silver wires, copper wires, or the like.
In the chip packaging structure, signals on a chip 2 are led to a transfer board 3 through a first bonding wire 4, and then are led to a substrate 1 through a conductive circuit 33 and a second bonding wire 5 which are preset on the transfer board 3, so that the interconnection of the signals is realized. Therefore, signals on the chip 2 are not required to be led to the substrate 1 in a large-span lead bonding mode, the complexity of the process is reduced, the yield is improved, and the cost is reduced. Meanwhile, because the span of the bonding wire in the structure is small, the impedance of a control signal can be better, and the electrical property of a product is improved.
In a preferred embodiment of the present invention, the conductive traces 33 are disposed on the surface of the interposer 3. Therefore, the process difficulty is low, and the operability is strong. As an alternative embodiment, the conductive traces 33 are disposed inside the interposer 3, which is beneficial for protecting the conductive traces 33 from external damage. The user can set the position of the conductive circuit 33 according to actual requirements, and the device has the advantages of selectivity and high flexibility.
As a preferred embodiment of the present invention, the number of the conductive traces 33 is the same as the number of the pads 32, and both ends of the conductive trace 33 are provided with pads 34 exposed on the upper surface of the interposer 3, and the pads 34 at both ends of the same conductive trace 33 are connected to the pads 32 and the substrate 1 through bonding wires, respectively. That is, each pad 32 on the chip 2 has a corresponding conductive trace 33, and the two ends of the first bonding wire 4 are connected to the pad 32 on the chip 2 and the pad 34 at one end of the corresponding conductive trace 33, and the pad 34 at the other end is connected to the substrate 1. Therefore, the orderly connection of the bonding wires is facilitated, and the disorder of the circuit is avoided.
In a preferred embodiment of the present invention, the number of the through holes 31 is one, and the solder points 32 are all located in the through holes 31. Therefore, only one through hole 31 needs to be formed in the adapter plate 3, the process is simplified, and the manufacturing difficulty is reduced. As an alternative embodiment, the number of the through holes 31 may also be the same as the number of the pads 32, as shown in fig. 4, each pad 32 is located in its corresponding through hole 31, that is, the pads 32 correspond to the through holes 31 one by one, thereby facilitating alignment between the bonding wire and the pads 32 during the wire bonding process and avoiding disorder of the connection caused by connection of the bonding wire to other pads 32.
As another alternative, as shown in fig. 5, the number of through holes 31 is one-half of the number of pads 32, and each two pads 32 share one through hole 31. Two adjacent welding spots 32 along the X-axis may share one through hole 31, or two adjacent welding spots 32 along the Y-axis may share one through hole 31, which all belong to the protection scope of the present invention. In addition, the purpose of the present invention can be achieved by using three pads 32 sharing one through hole 31, or four pads 32 sharing one through hole 31.
In a preferred embodiment of the present invention, the corner angle of the interposer 3 is a smooth arc angle. Because the first bonding wire 4 and the second bonding wire 5 contact the edge of the side surface of the adapter plate 3, if the edge is too sharp, the first bonding wire 4 and the second bonding wire 5 may be worn, so that the bonding wires are damaged, and the conductivity is affected. The edge angle of the adapter plate 3 is set to be a smooth arc angle, so that the first bonding wire 4 and the second bonding wire 5 are prevented from being worn by sharp edge angles.
In a preferred embodiment of the present invention, the distance between the solder 32 and the wall of the through hole 31 is not less than 50 μm. That is, a certain safety distance is provided for the later stage wire bonding process, and it is ensured that the first bonding wire 4 can be smoothly connected to the welding point 32 of the chip 2, and the operation is not difficult due to too small space.
In this embodiment, the thickness of the interposer 3 may be less than or equal to 100 μm. When the thickness of the interposer 3 is within the value range, the influence of the interposer 3 on the thickness of the whole chip package is small.
Example 2
The embodiment of the invention discloses a chip packaging method, which comprises the following steps:
step S21, providing the interposer 3 with the through hole 31. The number of the through holes 31 is at least one, the thickness of the interposer 3 can be less than or equal to 100 μm, and the interposer 3 can be at least one or more stacked combinations of a silicon plate, a glass plate or a polymer material plate.
In step S22, wiring is performed on the surface of the interposer 3 to form the conductive traces 33.
The conductive path 33 may be formed in advance inside the interposer 3.
Step S23 is to dispose the interposer 3 on the surface of the chip 2 such that the pads 32 on the chip 2 are exposed in the through holes 31.
Step S24 connects the pad 32 and the conductive trace 33 via the first bonding wire 4, and connects the conductive trace 33 and the substrate 1 via the second bonding wire 5. The first bonding wire 4 and the second bonding wire 5 may be gold wires, silver wires, copper wires, or the like.
According to the chip packaging method, signals on the chip 2 are led to the adapter plate 3 through the first bonding wires 4, and then are led to the substrate 1 through the conductive circuit 33 and the second bonding wires 5 which are preset on the adapter plate 3, so that signal interconnection is achieved. Therefore, signals on the chip 2 are not required to be led to the substrate 1 in a large-span lead bonding mode, the complexity of the process is reduced, the yield is improved, and the cost is reduced. Meanwhile, because the span of the bonding wire in the structure is small, the impedance of a control signal can be better, and the electrical property of a product is improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (10)

1. A chip package structure, comprising:
a substrate (1) for loading a chip (2);
the adapter plate (3) is provided with at least one through hole (31) penetrating through the surface and arranged on the chip (2), and a plurality of welding points (32) on the chip (2) are positioned in the through hole (31);
the adapter plate (3) is provided with a conductive circuit (33), the welding spot (32) is connected with the conductive circuit (33) through a first bonding wire (4), and the conductive circuit (33) is connected with the substrate (1) through a second bonding wire (5).
2. The chip package structure according to claim 1, wherein the conductive traces (33) are disposed on a surface of or inside the interposer (3).
3. The chip packaging structure according to claim 1, wherein the number of the conductive traces (33) is the same as the number of the pads (32), and both ends of the conductive traces (33) are provided with pads (34) exposed on the upper surface of the interposer (3), and the pads (34) at both ends of the same conductive trace (33) are respectively connected with the pads (32) and the substrate (1) through the bonding wires.
4. The chip packaging structure according to claim 1, wherein the number of the through holes (31) is one, and the pads (32) are all located in the through holes (31).
5. The chip packaging structure according to claim 1, wherein the number of the through holes (31) is the same as the number of the pads (32), and each of the pads (32) is located in the through hole (31) corresponding thereto.
6. The chip package structure according to claim 1, wherein the interposer (3) is at least one or more stacked combinations of a silicon plate or a glass plate or a polymer material plate.
7. The chip packaging structure according to claim 1, wherein the corners of the interposer (3) are smooth rounded corners.
8. Chip packaging arrangement according to claim 1, characterized in that the interposer (3) is connected to the chip (2) by soldering or mounting or gluing.
9. The chip packaging structure according to claim 1, wherein a distance between the solder joint (32) and a wall of the through hole (31) is not less than 50 μm.
10. A chip packaging method is characterized by comprising the following steps:
providing an adapter plate (3) with a through hole (31);
wiring is carried out on the surface of the adapter plate (3) to form a conductive circuit (33);
arranging the adapter plate (3) on the surface of the chip (2), and enabling the welding points (32) on the chip (2) to be positioned in the through holes (31) and exposed;
the welding point (32) and the conducting circuit (33) are connected through a first bonding wire (4), and the conducting circuit (33) and the substrate (1) are connected through a second bonding wire (5).
CN201810303905.4A 2018-04-04 2018-04-04 Chip-packaging structure and packaging method Pending CN108550565A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109473363A (en) * 2018-11-12 2019-03-15 深圳市江波龙电子股份有限公司 System-in-package structure and production method
CN110879444A (en) * 2019-11-30 2020-03-13 光为科技(广州)有限公司 Optical module and communication device

Citations (2)

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Publication number Priority date Publication date Assignee Title
US20040164413A1 (en) * 2002-07-08 2004-08-26 Hall Frank L. Underfilled, encapsulated semiconductor die assemblies and methods of fabrication
CN104054172A (en) * 2011-11-29 2014-09-17 考文森智财管理公司 Interposer For Stacked Semiconductor Devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040164413A1 (en) * 2002-07-08 2004-08-26 Hall Frank L. Underfilled, encapsulated semiconductor die assemblies and methods of fabrication
CN104054172A (en) * 2011-11-29 2014-09-17 考文森智财管理公司 Interposer For Stacked Semiconductor Devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109473363A (en) * 2018-11-12 2019-03-15 深圳市江波龙电子股份有限公司 System-in-package structure and production method
CN109473363B (en) * 2018-11-12 2024-09-06 深圳市江波龙电子股份有限公司 System-in-package structure and production method
CN110879444A (en) * 2019-11-30 2020-03-13 光为科技(广州)有限公司 Optical module and communication device

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