JP2000332159A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000332159A JP2000332159A JP11139398A JP13939899A JP2000332159A JP 2000332159 A JP2000332159 A JP 2000332159A JP 11139398 A JP11139398 A JP 11139398A JP 13939899 A JP13939899 A JP 13939899A JP 2000332159 A JP2000332159 A JP 2000332159A
- Authority
- JP
- Japan
- Prior art keywords
- package
- cavity
- semiconductor device
- sealing resin
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パッケージのキャ
ビティ内に半導体チップを搭載し、前記半導体チップを
封止樹脂で封止してなる半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip mounted in a cavity of a package and sealing the semiconductor chip with a sealing resin.
【０００２】[0002]
【従来の技術】従来、この種の半導体装置は図２に示す
ように、放熱板１に基板２が接合され、キャビティ３が
基板２を貫通して放熱板１に至る凹部として形成され、
半導体チップ５が放熱板１に接着剤７で接合されキャビ
ティ３内に搭載されている。2. Description of the Related Art Conventionally, in this type of semiconductor device, as shown in FIG. 2, a substrate 2 is joined to a heat sink 1 and a cavity 3 is formed as a recess penetrating through the substrate 2 and reaching the heat sink 1.
A semiconductor chip 5 is bonded to the heat sink 1 with an adhesive 7 and is mounted in the cavity 3.
【０００３】さらにキャビティ３の開口縁に隣接してパ
ッケージの端面に樹脂ダム８が設けられ、樹脂ダム８よ
り内側でキャビティ３内に封止樹脂９が充填され、半導
体チップ５が封止樹脂９で封止されている。Further, a resin dam 8 is provided on the end face of the package adjacent to the opening edge of the cavity 3, the cavity 3 is filled with the sealing resin 9 inside the resin dam 8, and the semiconductor chip 5 is sealed with the sealing resin 9. It is sealed with.
【０００４】また半田ボール１０が樹脂ダム８より外側
のパッケージ端面に設けられた構造になっている。Further, the structure is such that a solder ball 10 is provided on an end face of the package outside the resin dam 8.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、図２に
示す従来の半導体装置は、パッケージ端面の外側に半田
ボール１０が形成され、それより内側に樹脂ダム８が形
成されるため、搭載すべき半導体チップ５のサイズを大
きくする場合には、パッケージのサイズを大型化する必
要があり、パッケージのサイズをそのままで半導体チッ
プ５のサイズを大型化することはできないという問題が
ある。However, in the conventional semiconductor device shown in FIG. 2, the solder ball 10 is formed outside the end face of the package, and the resin dam 8 is formed inside the solder ball 10. When increasing the size of the chip 5, it is necessary to increase the size of the package, and there is a problem that the size of the semiconductor chip 5 cannot be increased without changing the size of the package.
【０００６】この種の半導体装置は、水分が存在する環
境で使用される場合が多く、その水分は、封止樹脂９と
基板２上のソルダーレジスト、又は基板１上の配線とソ
ルダーレジスト間からパッケージ内に侵入することとな
る。[0006] This type of semiconductor device is often used in an environment where moisture exists, and the moisture is transmitted from the sealing resin 9 and the solder resist on the substrate 2 or between the wiring on the substrate 1 and the solder resist. It will break into the package.
【０００７】しかしながら、図２に示す従来の半導体装
置は、樹脂ダム８がキャビティ３の開口縁に隣接してパ
ッケージの端面に設けられているため、封止樹脂９と基
板２との間を通してキャビティ３に至る水分の侵入経路
Ｌ2が短く、水分がパッケージ内に侵入する際の抵抗が
小さくなり、水分がパッケージ内に容易に侵入すること
となり、信頼性の問題がある。However, in the conventional semiconductor device shown in FIG. 2, since the resin dam 8 is provided on the end face of the package adjacent to the opening edge of the cavity 3, the cavity is formed between the sealing resin 9 and the substrate 2. 3 is short, the resistance when moisture enters the package is reduced, and the moisture easily enters the package, and there is a problem of reliability.
【０００８】また半田ボールが剥き出して搭載されてい
るため、パッケージとの接合強度不足を招きやすく、実
装後の装置電源のオンオフによるヒートサイクルによ
り、クラックが入り実装信頼性を低下させるという問題
がある。Further, since the solder balls are barely mounted, there is a problem that the bonding strength with the package is apt to be insufficient, and cracks occur due to a heat cycle caused by turning on and off the power supply of the device after mounting, which lowers mounting reliability. .
【０００９】また特開平１１−２６６４２号公報には、
パッケージを用いずに、電極板に半導体チップを搭載し
て、その外周を封止樹脂で封止した構造のものが開示さ
れている。Japanese Patent Application Laid-Open No. 11-26642 discloses that
There is disclosed a structure in which a semiconductor chip is mounted on an electrode plate without using a package, and the outer periphery thereof is sealed with a sealing resin.
【００１０】しかしながら特開平１１−２６６４２号公
報に開示された半導体装置は、図２に示すものと同様
に、水分が侵入する際の抵抗が小さく、水分がパッケー
ジ内に容易に侵入し易く、信頼性の問題がある。However, the semiconductor device disclosed in Japanese Patent Application Laid-Open No. H11-26642 has a low resistance when water enters, and easily penetrates into the package, as shown in FIG. There is a problem of sex.
【００１１】本発明の目的は、パッケージの大きさをそ
のままにして、半導体チップのサイズを大型化し、かつ
水分の侵入を抑制するようにした半導体チップを提供す
ることにある。An object of the present invention is to provide a semiconductor chip in which the size of the semiconductor chip is increased while the size of the package is not changed, and the penetration of moisture is suppressed.
【００１２】[0012]
【課題を解決しようとする課題】前記目的を達成するた
め、本発明に係る半導体装置は、パッケージのキャビテ
ィ内に半導体チップを搭載し、前記半導体チップを封止
樹脂で封止してなる半導体装置であって、前記パッケー
ジのキャビティから前記パッケージの端縁に至る範囲に
前記封止樹脂を形成したものである。In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor chip mounted in a cavity of a package, and the semiconductor chip is sealed with a sealing resin. The sealing resin is formed in a range from a cavity of the package to an edge of the package.
【００１３】また前記パッケージの端縁は、樹脂封止さ
れた前記半導体チップを個片に切出す切出し線に沿うも
のである。The edge of the package is along a cut line for cutting the resin-sealed semiconductor chip into individual pieces.
【００１４】また前記封止樹脂が形成された前記パッケ
ージの端面に半田ボールを有し、前記半田ボールは、前
記パッケージの端面に接合する基部が前記封止樹脂内に
埋没している。[0014] Further, a solder ball is provided on an end face of the package on which the sealing resin is formed, and a base of the solder ball which is joined to an end face of the package is buried in the sealing resin.
【００１５】また前記半田ボールは、全高の１／３程度
が露出して前記封止樹脂に埋没している。Further, the solder ball is buried in the sealing resin with about one third of the total height being exposed.
【００１６】また前記パッケージのキャビティから前記
パッケージの端縁に至る範囲に前記封止樹脂を形成する
ことにより、外部から前記キャビティ内への水分の侵入
経路を拡張させたものである。Further, the sealing resin is formed in a range from the cavity of the package to the edge of the package, so that a path of moisture from the outside into the cavity is extended.
【００１７】また前記パッケージは、放熱板と、該放熱
板に接合した基板とを含み、前記キャビティは、前記基
板を貫通して前記放熱板に至る凹部として形成され、前
記半導体チップは、前記放熱板に接合されて前記キャビ
ティ内に搭載されたものである。The package includes a radiator plate and a substrate joined to the radiator plate, the cavity is formed as a recess penetrating through the substrate and reaching the radiator plate, and the semiconductor chip is provided with the radiator plate. It is bonded to a plate and mounted in the cavity.
【００１８】[0018]
【発明の実施の形態】以下、本発明の実施の形態を図に
より説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.
【００１９】図１は、本発明の一実施形態に係る半導体
装置を示す断面図である。FIG. 1 is a sectional view showing a semiconductor device according to one embodiment of the present invention.
【００２０】図１に示す本発明の一実施形態に係る半導
体装置は、パッケージのキャビティ３内に半導体チップ
５を搭載し、半導体チップ５を封止樹脂で封止してなる
半導体装置を対象とするものであり、パッケージのキャ
ビティ３からパッケージの端縁２ａに至る範囲に封止樹
脂９を形成したことを特徴とするものである。The semiconductor device according to one embodiment of the present invention shown in FIG. 1 is intended for a semiconductor device in which a semiconductor chip 5 is mounted in a cavity 3 of a package and the semiconductor chip 5 is sealed with a sealing resin. The sealing resin 9 is formed in a range from the cavity 3 of the package to the edge 2a of the package.
【００２１】本発明の一実施形態に係る半導体装置で
は、パッケージのキャビティ３からパッケージの端縁２
ａに至る範囲に封止樹脂９を形成することにより、外部
からキャビティ３への水分の侵入経路Ｌ2を拡張させて
いる。In the semiconductor device according to one embodiment of the present invention, the package edge 3 is moved from the package cavity 3 to the package edge 2.
By forming the sealing resin 9 in the range up to "a", the path L2 from which moisture enters the cavity 3 from the outside is expanded.
【００２２】図１に示す実施形態でのパッケージは、放
熱板（ヒートスプレッダー）１と、放熱板１に接合した
基板２とを含み、キャビティ３は、基板２を貫通して放
熱板１に至る凹部として形成され、半導体チップ５は、
放熱板１に接着剤７で接合されてキャビティ３内に搭載
された構造となっている。The package according to the embodiment shown in FIG. 1 includes a radiator plate (heat spreader) 1 and a substrate 2 bonded to the radiator plate 1, and the cavity 3 penetrates through the substrate 2 to reach the radiator plate 1. The semiconductor chip 5 is formed as a recess,
It has a structure in which it is bonded to the heat sink 1 with an adhesive 7 and mounted in the cavity 3.
【００２３】またパッケージ（基板２の外縁）端縁２ａ
は、樹脂封止された半導体チップ５を個片に切出す切出
し線４に沿うものである。The package (outer edge of the substrate 2) edge 2a
Is along the cutout line 4 for cutting the resin-sealed semiconductor chip 5 into individual pieces.
【００２４】また封止樹脂９が形成されたパッケージの
端面（基板２の板面）に半田ボール１０を有しており、
半田ボール１０は、パッケージの端面に接合する基部１
０ａが封止樹脂９内に埋没しており、また半田ボール１
０は、全高の１／３程度が露出して封止樹脂９に埋没し
ている。A solder ball 10 is provided on the end surface (the plate surface of the substrate 2) of the package on which the sealing resin 9 is formed.
The solder ball 10 is connected to the base 1 to be joined to the end face of the package.
0a is embedded in the sealing resin 9 and the solder ball 1
In the case of 0, about の of the total height is exposed and buried in the sealing resin 9.
【００２５】またキャビティ３に搭載した半導体チップ
５の図示しない電極と、基板２の板面に形成した図示し
ない配線とは、金属細線１１により電気的に接続されて
おり、半導体チップ５及び金属細線１１並びに半田ボー
ル１０の基部１０ａを含めて封止樹脂９で被覆され、か
つ封止樹脂９は基板２上に一定の膜厚に塗布形成されて
いる。封止樹脂９の形成範囲は、パッケージのキャビテ
ィ３からパッケージの端縁２ａに至る範囲に及んでい
る。The electrodes (not shown) of the semiconductor chip 5 mounted in the cavity 3 and the wires (not shown) formed on the plate surface of the substrate 2 are electrically connected by the thin metal wires 11, and the semiconductor chip 5 and the thin metal wires The sealing resin 9 including the base 11 a and the solder ball 10 is covered with the sealing resin 9, and the sealing resin 9 is formed on the substrate 2 by applying a predetermined thickness. The forming range of the sealing resin 9 extends from the cavity 3 of the package to the edge 2a of the package.
【００２６】また封止樹脂９は、パッケージにポッティ
ング又は印刷等の方法により形成されている。The sealing resin 9 is formed on the package by a method such as potting or printing.
【００２７】次に図１に示す本発明の一実施形態に係る
半導体装置を組立てる場合について説明する。Next, the case of assembling the semiconductor device according to one embodiment of the present invention shown in FIG. 1 will be described.
【００２８】まず広い面積をもつ放熱板１に、キャビテ
ィ３をマトリクス状に配置した基板２を張付けてパッケ
ージを構成する。First, a package is formed by attaching a substrate 2 having cavities 3 arranged in a matrix to a heat sink 1 having a large area.
【００２９】そのパッケージの各キャビティ３内に半導
体チップ５をそれぞれ搭載し、キャビティ３内の半導体
チップ５の電極と、基板２上の配線とを金属細線１１に
より電気的に接続し、次に基板２の全面に封止樹脂９を
形成する。The semiconductor chip 5 is mounted in each cavity 3 of the package, and the electrodes of the semiconductor chip 5 in the cavity 3 are electrically connected to the wiring on the substrate 2 by the thin metal wires 11. The sealing resin 9 is formed on the entire surface of the substrate 2.
【００３０】パッケージ（特に基板２）には予め半田ボ
ール１０を搭載しておき、基板２上での封止樹脂９の膜
厚が、半田ボール１０の高さの１／３程度になるように
コントロールする。A solder ball 10 is mounted on a package (particularly, the substrate 2) in advance, and the thickness of the sealing resin 9 on the substrate 2 is set to about １ ／ of the height of the solder ball 10. Control.
【００３１】最後に封止樹脂９をキュアした後、樹脂封
止された半導体チップ５を個片に切出す切出し線Ｓに沿
ってダイシング等を行い、半導体チップ５の個片化を行
う。Finally, after the sealing resin 9 is cured, dicing or the like is performed along a cutout line S for cutting the resin-sealed semiconductor chip 5 into individual pieces, thereby dividing the semiconductor chip 5 into individual pieces.
【００３２】パッケージのキャビティ３からパッケージ
の端縁２ａに至る範囲に封止樹脂９が形成された状態で
半導体チップ５の個片化を行なわれる。The semiconductor chip 5 is singulated while the sealing resin 9 is formed in a range from the cavity 3 of the package to the edge 2a of the package.
【００３３】ここで、封止樹脂９の形成は、印刷にて実
施することも可能であり、半田ボール１０の搭載領域に
封止樹脂９が印刷されないマスクにて樹脂印刷し、キュ
ア後に半田ボール１０を搭載するようにしてもよい。Here, the formation of the sealing resin 9 can be carried out by printing. The resin is printed on a mounting area of the solder ball 10 with a mask on which the sealing resin 9 is not printed, and after the curing, the solder ball 9 is formed. 10 may be mounted.
【００３４】[0034]
【発明の効果】以上説明したように本発明によれば、パ
ッケージのキャビティからパッケージの端縁に至る範囲
に封止樹脂を形成することにより、外部からキャビティ
への水分の侵入経路を拡張させているため、水分の侵入
を抑えることができ、信頼性を向上することができる。As described above, according to the present invention, the sealing resin is formed in a range from the cavity of the package to the edge of the package, so that the path of moisture from the outside to the cavity can be expanded. Therefore, intrusion of moisture can be suppressed, and reliability can be improved.
【００３５】さらに樹脂ダム部の存在によりパッケージ
に搭載する半導体チップのサイズが制限を受けることが
なく、パッケージのサイズを変更することなく、半導体
チップのサイズを拡大することができる。Further, the size of the semiconductor chip mounted on the package is not restricted by the presence of the resin dam portion, and the size of the semiconductor chip can be increased without changing the size of the package.
【００３６】さらに半田ボールの基部側を封止樹脂内に
埋設することにより、半田ボールをパッケージに確実に
固定して、実装信頼性を向上することができる。Further, by embedding the base side of the solder ball in the sealing resin, the solder ball can be securely fixed to the package and the mounting reliability can be improved.
【図１】本発明の一実施形態に係る半導体装置を示す断
面図である。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【図２】従来例に係る半導体装置を示す断面図である。FIG. 2 is a sectional view showing a semiconductor device according to a conventional example.
２ａ パッケージの端縁 ３ パッケージのキャビティ ５ 半導体チップ ９ 封止樹脂 Ｌ2 水分の侵入経路 2a Package edge 3 Package cavity 5 Semiconductor chip 9 Sealing resin L2 Water entry path
Claims (6)
プを搭載し、前記半導体チップを封止樹脂で封止してな
る半導体装置であって、 前記パッケージのキャビティから前記パッケージの端縁
に至る範囲に前記封止樹脂を形成したことを特徴とする
半導体装置。1. A semiconductor device having a semiconductor chip mounted in a cavity of a package and sealing the semiconductor chip with a sealing resin, wherein the semiconductor device is provided in a range from a cavity of the package to an edge of the package. A semiconductor device comprising a sealing resin.
た前記半導体チップを個片に切出す切出し線に沿うもの
であることを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein an edge of the package is along a cutting line that cuts the resin-sealed semiconductor chip into individual pieces.
ジの端面に半田ボールを有し、 前記半田ボールは、前記パッケージの端面に接合する基
部が前記封止樹脂内に埋没していることを特徴とする請
求項１又は２に記載の半導体装置。3. The package according to claim 1, further comprising a solder ball on an end face of the package on which the sealing resin is formed, wherein the solder ball has a base bonded to an end face of the package embedded in the sealing resin. The semiconductor device according to claim 1, wherein:
露出して前記封止樹脂に埋没していることを特徴と請求
項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein the solder ball is buried in the sealing resin with about one third of the total height being exposed.
ッケージの端縁に至る範囲に前記封止樹脂を形成するこ
とにより、外部から前記キャビティ内への水分の侵入経
路を拡張させたことを特徴とする請求項１に記載の半導
体装置。5. The method according to claim 1, wherein the sealing resin is formed in a range from a cavity of the package to an edge of the package, so that a path of moisture from the outside into the cavity is extended. Item 2. The semiconductor device according to item 1.
に接合した基板とを含み、 前記キャビティは、前記基板を貫通して前記放熱板に至
る凹部として形成され、 前記半導体チップは、前記放熱板に接合されて前記キャ
ビティ内に搭載されたものであることを特徴とする請求
項１に記載の半導体装置。6. The package includes a radiator plate and a substrate bonded to the radiator plate, the cavity is formed as a recess penetrating through the substrate to reach the radiator plate, and the semiconductor chip includes: 2. The semiconductor device according to claim 1, wherein the semiconductor device is mounted in the cavity by being joined to a heat sink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11139398A JP2000332159A (en) | 1999-05-20 | 1999-05-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11139398A JP2000332159A (en) | 1999-05-20 | 1999-05-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000332159A true JP2000332159A (en) | 2000-11-30 |
Family
ID=15244361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11139398A Pending JP2000332159A (en) | 1999-05-20 | 1999-05-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000332159A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017120203A (en) * | 2015-12-28 | 2017-07-06 | ローム株式会社 | Magnetic sensor module |
-
1999
- 1999-05-20 JP JP11139398A patent/JP2000332159A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017120203A (en) * | 2015-12-28 | 2017-07-06 | ローム株式会社 | Magnetic sensor module |
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