JP2000003985A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

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Publication number
JP2000003985A
JP2000003985A JP10181565A JP18156598A JP2000003985A JP 2000003985 A JP2000003985 A JP 2000003985A JP 10181565 A JP10181565 A JP 10181565A JP 18156598 A JP18156598 A JP 18156598A JP 2000003985 A JP2000003985 A JP 2000003985A
Authority
JP
Japan
Prior art keywords
wafer
chip
semiconductor device
polyimide substrate
surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10181565A
Other languages
Japanese (ja)
Inventor
Takashi Nakajima
高士 中島
Original Assignee
Mitsui High Tec Inc
株式会社三井ハイテック
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc, 株式会社三井ハイテック filed Critical Mitsui High Tec Inc
Priority to JP10181565A priority Critical patent/JP2000003985A/en
Publication of JP2000003985A publication Critical patent/JP2000003985A/en
Application status is Pending legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PROBLEM TO BE SOLVED: To fit a heat sink for a plurality of semiconductor chips in one step, by a method wherein fitting of the heat sink on a rear face side of the semiconductor chip is performed prior to a step of dividing the chip into sections.
SOLUTION: An elastic resin 4 is mounted in a region excluding an electrode 3 provided in unit of a chip 2 on one face of a wafer 9. Next, a polyimide substrate 5 forming conductive patterns on one face is fitted on a surface of this elastic resin 4. And, the conductive pattern of this polyimide substrate 5 is processed to form a lead 6, which is connected to the electrode 3 of the semiconductor chip 2, and further an opening part H is formed at a position corresponding to the conductive pattern on a surface of the polyimide substrate 5. Further, a periphery of the lead 6 is sealed with a encapsulation resin 7, and a solder ball 8 is mounted in the opening part H of the polyimide substrate 5. Thereafter, a wafer 9 is divided in unit of each semiconductor chip 2 by a dicing sow of a dicing machine.
COPYRIGHT: (C)2000,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は半導体装置の製造方法に係り、特に半導体チップのアセンブリ面の裏面側に放熱板を装着してなるCSPタイプの半導体装置の製造方法に関するものである。 The present invention relates relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a CSP-type semiconductor device formed by mounting the heat dissipation plate on the back side of the assembly surface of the semiconductor chip.

【0002】 [0002]

【従来の技術】近年、携帯電話などの携帯用電子機器の普及に伴って、それらに使用される半導体装置もより一層の小型化が要求されている。 Recently, with the spread of portable electronic devices such as cellular phones, further downsizing is also a semiconductor device that is used they are required. この要求を満たすものとして、CSP(Chip Size Package)と呼称される半導体装置が各社から提案されている。 As meeting this requirement, a semiconductor device called a CSP (Chip Size Package) it has been proposed by various companies.

【0003】図5(a)にCSPタイプの半導体装置の一例を示す。 [0003] FIGS. 5 (a) shows an example of a CSP type semiconductor device. ここで示す半導体装置1は、半導体チップ2と、半導体チップ2の一面に設けられた電極3と、この電極3を除く領域に形成された弾性樹脂層4と、弾性樹脂層4の表面に貼付された、一面に導体パターンを有するポリイミド基板5と、ポリイミド基板5の導体パターンを加工することにより形成され、半導体チップ2の電極3と接続されるリード6と、このリード6の周囲を封止する封止樹脂7と、ポリイミド基板5に形成された開口部H上に装着され、外部接続端子として機能する半田ボール8とから構成されている。 The semiconductor device 1 shown here includes a semiconductor chip 2, the electrodes 3 provided on one surface of the semiconductor chip 2, the elastic resin layer 4 formed in a region excluding the electrode 3, stuck to the surface of the elastic resin layer 4 sealing a polyimide substrate 5 having been conductor pattern on one surface, are formed by processing a conductor pattern of a polyimide substrate 5, a lead 6 is connected to the electrode 3 of the semiconductor chip 2, the periphery of the lead 6 the sealing resin 7 which is mounted on the opening H formed in the polyimide substrate 5, and a solder ball 8 which functions as an external connection terminal.

【0004】図3、図4にこのような半導体装置の製造方法を示す。 [0004] Figure 3, Figure 4 illustrates a method of manufacturing such a semiconductor device. 図4に示すように、まず図示しないシリコンインゴットからウエハー9を切り出す。 As shown in FIG. 4, cut out wafer 9 from a silicon ingot is first not shown. ウエハー9は表面を研磨された後、既存の方法により不純物注入、薄膜形成、フォトエッチングを繰り返すことによりトランジスタや配線などを形成し、その後スパッタリングなどによって各チップ単位に電極3を形成する。 After the wafer 9 that has been polished surface, impurity implantation by an existing method, thin film formation, to form a transistor or the wiring by repeating the photo-etching to form an electrode 3 on the chip unit, such as by subsequently sputtering. そして、この電極3形成面がアセンブリ面となる。 Then, the electrode 3 formed surface is assembly surface. なお、通常は1 It should be noted, it is usually 1
枚のウエハー9から100〜1000個の半導体チップ2が形成される。 Like the semiconductor chip 2 from the wafer 9 of 100 to 1000 is formed. このウエハー9は、ウエハーリング1 The wafer 9, the wafer ring 1
0に装着されたフィルム11にアセンブリ面の裏面側が取り付けられ、その後アセンブリ面にアセンブリがなされる。 0 backside of the assembly surface is attached to the film 11 mounted on the assembly is made in the subsequent assembly surface.

【0005】図3はウエハー9へのアセンブリ工程を示す図である。 [0005] FIG. 3 is a diagram showing the assembly process of the wafer 9. アセンブリは、図3(a)に示すようにウエハーリング10に装着されたフィルム11に取り付けられたウエハー9のチップ2単位で行われる。 Assembly is performed in the chip 2 units of the wafer 9 which is attached to the film 11 attached to the wafer ring 10 as shown in FIG. 3 (a). まず図3 First, FIG. 3
(b)に示すように、ウエハー9のアセンブリ面にチップ2単位に設けられた電極3を除く領域に弾性樹脂4を装着する。 (B), the mounting elastic resin 4 in a region excluding the electrode 3 provided on the chip 2 units in the assembly surface of the wafer 9. 次に、この弾性樹脂4の表面に、一面に導体パターンが形成されたポリイミド基板5を取り付ける。 Next, the surface of the elastic resin 4, attaching the polyimide substrate 5 on which the conductor pattern is formed on one surface.
それからこのポリイミド基板5の導体パターンを加工しリード6とした上で半導体チップ2の電極3に接続し、 And then attach the conductor pattern of the polyimide substrate 5 processed to the electrode 3 of the semiconductor chip 2 on which a lead 6,
またポリイミド基板5の表面の導体パターンに対応する箇所には開口部Hを形成する。 Also at a position corresponding to the conductor pattern of the surface of the polyimide substrate 5 to form an opening H.

【0006】更に、図3(c)に示すように、リード6 Furthermore, as shown in FIG. 3 (c), the lead 6
の周囲を封止樹脂7によって封止して、ポリイミド基板5の開口部Hに半田ボール8を装着する。 Ambient sealed by the sealing resin 7 of, mounting the solder balls 8 in the opening H of the polyimide substrate 5. その後図3 Then Figure 3
(d)に示すように、ダイシングマシンのダイシングソー12によってウエハー9を各半導体チップ2単位に分断することにより、図5(a)に示すような半導体装置1が得られる。 As shown in (d), the severing a wafer 9 by a dicing saw 12 in a dicing machine to the semiconductor chip 2 units, the semiconductor device 1 as shown in FIG. 5 (a) is obtained.

【0007】このように製造された半導体装置1は、外径がチップサイズと同等であるため従来の半導体装置と比較して非常に小型に形成できる。 [0007] The semiconductor device 1 manufactured in this way, the outer diameter can be formed in a very small as compared with the conventional semiconductor device for an equivalent chip size. また半導体チップ2 The semiconductor chip 2
のアセンブリ面以外はむき出しになっているため、放熱性も比較的良好である。 Except the assembly surface for which is exposed, heat dissipation is relatively good.

【0008】 [0008]

【発明が解決しようとする課題】前述したように、このような半導体装置1は比較的放熱性は良好であるが、通常よりもハイパワーなチップを使用した場合には、従来の構成では対応できないため、図5(b)に示すように、チップ2のアセンブリ面の裏面側に、接着剤13を介して放熱板14を取り付けることによって半導体チップ2の発熱を放散する場合がある。 [SUMMARY OF THE INVENTION] As described above, although the semiconductor device 1 is relatively heat dissipation is good, when using high-power chip than normal, corresponding in the conventional configuration It can not be, as shown in FIG. 5 (b), on the back side of the assembly surface of the chip 2, there is a case to dissipate heat generated by the semiconductor chip 2 by attaching a heat radiating plate 14 via the adhesive 13. しかし、従来はこの放熱板14の取り付けは、各半導体装置を個別に分断した後に、個々の半導体装置に対して行っていたので、作業効率が非常に悪かった。 However, conventional attachment of the heat radiating plate 14, the semiconductor devices after cutting individually so has been performed for each semiconductor device, the work efficiency is very poor.

【0009】 [0009]

【課題を解決するための手段】上記の問題点を解決するために、本発明は、半導体チップ裏面側への放熱板の取り付けを、チップを分断する工程より以前に行うようにしている。 In order to solve the above problems SUMMARY OF THE INVENTION The present invention provides a mounting of the heat sink to the semiconductor chip rear surface side, and to perform before the step of dividing the chip.

【0010】 [0010]

【発明の実施の形態】本発明は、ウエハーのアセンブリ面の裏面側に、接着剤を介して金属板を取り付け、その状態でウエハーのアセンブリ面に各半導体チップ単位でアセンブリを行い、その後ウエハーを各半導体チップ単位に分断するようにしている。 DETAILED DESCRIPTION OF THE INVENTION The present invention, on the back side of the assembly surface of the wafer, attaching a metal plate through an adhesive, carried out assembly on each semiconductor chip unit in the assembly surface of the wafer in this state, then the wafer It is to be divided into each semiconductor chip unit.

【0011】放熱板となる金属板としては、Al板あるいはCu板などが適用できる。 [0011] As the metal plate serving as a radiator plate, can be applied, such as Al plate or Cu plate. また接着剤の材質は、シリコンベースであることが望ましい。 The material of the adhesive is preferably a silicon-based. 更に金属板の外径は、ウエハーの外径とほぼ同じであることが好ましい。 Furthermore the outer diameter of the metal plate is preferably the outer diameter of the wafer is substantially the same.

【0012】 [0012]

【実施例】以下、本発明の半導体装置の製造方法について、図面を参照して説明する。 EXAMPLES Hereinafter, a method for fabricating a semiconductor device of the present invention will be described with reference to the drawings. なお、従来と同一の箇所については同一の符号を使用して説明する。 Note that the conventional same position will be described using the same reference numerals. まず、図1 First, as shown in FIG. 1
に示すように、図示しないシリコンインゴットからウエハー9を切り出す。 As shown in, it cuts out wafer 9 from a silicon ingot (not shown). ウエハー9は表面を研磨された後、 After the wafer 9 that has been polished surface,
既存の方法により不純物注入、薄膜形成、フォトエッチングを繰り返すことによりトランジスタや配線などを形成し、その後スパッタリングなどによって各チップ単位に電極3を形成する。 Impurity implantation by an existing method, thin film formation, such as transistors and wiring are formed by repeating photoetching, then forming the electrodes 3 on the chip unit by sputtering.

【0013】ここで本実施例においては、ウエハー9の電極3が形成されたアセンブリ面の裏面側に、シリコンベースの接着剤13aを介して、ウエハー9の外径と同一に形成されたAlからなる金属板14aを取り付ける。 [0013] In this embodiment, where the backside of the assembly surface of the electrode 3 is formed of the wafer 9 through the silicon-based adhesive 13a, an Al formed equal to the outer diameter of the wafer 9 mounting the composed metal plate 14a. そしてこの金属板14a側を、ウエハーリング10 Then the metal plate 14a side, the wafer ring 10
に装着されたフィルム11に取り付ける。 Attached to the film 11 attached to.

【0014】図2はウエハーへのアセンブリ工程を示す図である。 [0014] FIG. 2 is a diagram showing the assembly process of the wafer. アセンブリは、従来同様に、図2(a)に示すようにウエハーリング10に装着されたフィルム11 Assembly is likewise conventional, a film 11 attached to the wafer ring 10, as shown in FIG. 2 (a)
に取り付けられたウエハー9のチップ2単位で行われる。 It takes place in the chip 2 units of the wafer 9 which is attached to. まず図2(b)に示すように、ウエハー9の一面にチップ2単位に設けられた電極3を除く領域に弾性樹脂4を装着する。 First, as shown in FIG. 2 (b), attaching the elastic resin 4 in a region excluding the electrode 3 provided on the chip 2 units on one side of the wafer 9. 次に、この弾性樹脂4の表面に、一面に導体パターンが形成されたポリイミド基板5を取り付ける。 Next, the surface of the elastic resin 4, attaching the polyimide substrate 5 on which the conductor pattern is formed on one surface. それからこのポリイミド基板5の導体パターンを加工しリード6とした上で半導体チップ2の電極3に接続し、またポリイミド基板5の表面の導体パターンに対応する箇所には開口部Hを形成する。 Then the conductor pattern of the polyimide substrate 5 is processed to connect to the electrodes 3 of the semiconductor chip 2 on which a lead 6 and at positions corresponding to the conductor pattern of the surface of the polyimide substrate 5 to form an opening H.

【0015】更に、図2(c)に示すように、リード6 Furthermore, as shown in FIG. 2 (c), the lead 6
の周囲を封止樹脂7によって封止して、ポリイミド基板5の開口部Hに半田ボール8を装着する。 Ambient sealed by the sealing resin 7 of, mounting the solder balls 8 in the opening H of the polyimide substrate 5. その後図3 Then Figure 3
(d)に示すように、ダイシングマシンのダイシングソー12によってウエハー9を各半導体チップ2単位に分断する。 (D), the a dicing saw 12 in a dicing machine for cutting the wafer 9 to the semiconductor chip 2 units. なお、このときウエハー9のアセンブリ面の裏面に取り付けられた金属板14aも同時に分断する。 At this time the metal plate 14a which is attached to the rear surface of the assembly surface of the wafer 9 is also divided at the same time.

【0016】以上の工程により、図5(b)に示すような、半導体チップ2のアセンブリ面の裏面側に放熱板1 [0016] Through the above process, as shown in FIG. 5 (b), the heat radiating plate 1 on the back side of the assembly surface of the semiconductor chip 2
4を装着した半導体装置1aが得られる。 4 the semiconductor device 1a can be obtained fitted with.

【0017】 [0017]

【発明の効果】本発明は、以上説明したような形態で実施され、以下に記載されるような効果を奏する。 According to the present invention, it is implemented in the form as described above, an effect as described below.

【0018】半導体チップ裏面側への放熱板の取り付けを、各半導体チップを個別に分断する工程より以前に行うようにしたので、多数の半導体チップに1工程で放熱板を取り付けることができ、その結果従来と比較して作業効率が大幅に向上する。 [0018] The mounting of the heat sink to the semiconductor chip back side, since each of the semiconductor chip to perform before the step of cutting separately, it is possible to attach a heat sink in one step to a large number of semiconductor chips, the work efficiency compared to the results prior is greatly improved.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の半導体装置の製造方法を示す図。 Diagrams showing a method of manufacturing a semiconductor device of the present invention; FIG.

【図2】本発明の半導体装置の製造方法を示す断面図。 Cross-sectional view showing a manufacturing method of a semiconductor device of the present invention; FIG.

【図3】従来の半導体装置の製造方法を示す断面図。 3 is a cross-sectional view illustrating a conventional method of manufacturing a semiconductor device.

【図4】従来の半導体装置の製造方法を示す図。 4 is a diagram showing a conventional method of manufacturing a semiconductor device.

【図5】半導体装置を示す断面図。 5 is a sectional view showing a semiconductor device.

【符号の説明】 DESCRIPTION OF SYMBOLS

1、1a 半導体装置 2 半導体チップ 3 電極 4 弾性樹脂層 5 ポリイミド基板 6 リード 7 封止樹脂 8 半田ボール 9 ウエハー 10 ウエハーリング 11 フィルム 12 ダイシングソー 13、13a 接着剤層 14 放熱板 14a 金属板 1,1a semiconductor device 2 semiconductor chip 3 electrode 4 elastic resin layer 5 polyimide substrate 6 leads 7 sealing resin 8 solder balls 9 wafer 10 wafer ring 11 film 12 dicing saw 13,13a adhesive layer 14 heat dissipation plate 14a metal plate

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体チップのアセンブリ面の裏面側に放熱板を取り付けてなる半導体装置の製造方法において、ウエハーのアセンブリ面の裏面側に接着剤を介して金属板を貼り付ける工程と、ウエハーのアセンブリ面に各チップ単位でアセンブリを行う工程と、ウエハーを各チップ単位に分断する工程とを含むことを特徴とする半導体装置の製造方法。 1. A method of manufacturing a semiconductor chip assembly faces the semiconductor device made by attaching the back side heat sink of a step of attaching a metal plate via an adhesive on the back side of the assembly surface of the wafer, the wafer the method of manufacturing a semiconductor device comprising the steps of performing assembly at each chip unit in the assembly plane, to include the step of dividing the wafer into each chip unit.
  2. 【請求項2】 前記金属板の外径は、ウエハーの外径とほぼ同じであることを特徴とする請求項1に記載の半導体装置の製造方法。 The outer diameter of wherein said metal plate, a method of manufacturing a semiconductor device according to claim 1, characterized in that the outer diameter of the wafer is substantially the same.
JP10181565A 1998-06-12 1998-06-12 Manufacture for semiconductor device Pending JP2000003985A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10181565A JP2000003985A (en) 1998-06-12 1998-06-12 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10181565A JP2000003985A (en) 1998-06-12 1998-06-12 Manufacture for semiconductor device

Publications (1)

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JP2000003985A true JP2000003985A (en) 2000-01-07

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6797530B2 (en) 2001-09-25 2004-09-28 Kabushiki Kaisha Toshiba Semiconductor device-manufacturing method for manufacturing semiconductor devices with improved heat radiating efficiency and similar in size to semiconductor elements
US8426982B2 (en) 2001-03-30 2013-04-23 Megica Corporation Structure and manufacturing method of chip scale package
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US9030029B2 (en) * 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8426982B2 (en) 2001-03-30 2013-04-23 Megica Corporation Structure and manufacturing method of chip scale package
US9018774B2 (en) 2001-03-30 2015-04-28 Qualcomm Incorporated Chip package
US8748227B2 (en) 2001-03-30 2014-06-10 Megit Acquisition Corp. Method of fabricating chip package
US8912666B2 (en) 2001-03-30 2014-12-16 Qualcomm Incorporated Structure and manufacturing method of chip scale package
US6797530B2 (en) 2001-09-25 2004-09-28 Kabushiki Kaisha Toshiba Semiconductor device-manufacturing method for manufacturing semiconductor devices with improved heat radiating efficiency and similar in size to semiconductor elements
US9030029B2 (en) * 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US8835221B2 (en) 2001-12-31 2014-09-16 Qualcomm Incorporated Integrated chip package structure using ceramic substrate and method of manufacturing the same
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US9136246B2 (en) 2001-12-31 2015-09-15 Qualcomm Incorporated Integrated chip package structure using silicon substrate and method of manufacturing the same
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers

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