JP2515036B2 - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JP2515036B2
JP2515036B2 JP2117741A JP11774190A JP2515036B2 JP 2515036 B2 JP2515036 B2 JP 2515036B2 JP 2117741 A JP2117741 A JP 2117741A JP 11774190 A JP11774190 A JP 11774190A JP 2515036 B2 JP2515036 B2 JP 2515036B2
Authority
JP
Japan
Prior art keywords
bed
resin
semiconductor device
lead portion
resin body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2117741A
Other languages
Japanese (ja)
Other versions
JPH0415945A (en
Inventor
和人 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP2117741A priority Critical patent/JP2515036B2/en
Priority to KR1019910007417A priority patent/KR950003234B1/en
Publication of JPH0415945A publication Critical patent/JPH0415945A/en
Priority to US07/873,689 priority patent/US5175610A/en
Application granted granted Critical
Publication of JP2515036B2 publication Critical patent/JP2515036B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、樹脂封止型半導体装置に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a resin-encapsulated semiconductor device.

(従来の技術) 従来の樹脂封止型半導体装置、例えば、面実装のSOJ
(Small Outline J lead)パッケージタイプを第4図に
示す。
(Prior Art) Conventional resin-encapsulated semiconductor device, for example, surface-mounted SOJ
(Small Outline J lead) Package type is shown in Fig. 4.

第4図(a)は、リードフレームを示す平面図,同図
(b)は、樹脂封止型半導体装置の断面図である。
4A is a plan view showing the lead frame, and FIG. 4B is a sectional view of the resin-sealed semiconductor device.

第4図(a)に示すリードフレームのベット14の上面
に、エポキシ等の接着剤4を用いて半導体チップ5を接
着しており、半導体チップ5の電極部6と、リードのイ
ンナーリード部8とは、ボンディングワイヤー7により
接続している。そして、前記ベット14,半導体チップ5,
及びインナーリード部8を樹脂体10で封止している。
The semiconductor chip 5 is adhered to the upper surface of the bed 14 of the lead frame shown in FIG. 4 (a) using an adhesive 4 such as epoxy, and the electrode portion 6 of the semiconductor chip 5 and the inner lead portion 8 of the lead are attached. Are connected by a bonding wire 7. Then, the bet 14, the semiconductor chip 5,
Also, the inner lead portion 8 is sealed with the resin body 10.

このような従来装置においては、樹脂体10が大気中か
ら水分を吸湿し、その水分11が、ベット14及び、インナ
ーリード部8の各界面に溜まる。そのため、ヒートショ
ック(装置を実装する際、半田浴槽につける等)後、第
5図に示すように、各界面に溜った水分11が気化膨張
し、樹脂体10を押し上げるので装置の外形の変化やクラ
ック15が発生しやすい。クラック15が発生した場合、ボ
ンディングワイヤー7を切断する恐れがあり、また、そ
のクラック15より、水や汚染物が侵入し、半導体チップ
5の電極部6のコロージョン(腐食)が発生する恐れも
ある。
In such a conventional device, the resin body 10 absorbs moisture from the atmosphere, and the moisture 11 accumulates at the interfaces of the bed 14 and the inner lead portion 8. Therefore, after heat shock (when mounting the device in a solder bath, etc.), as shown in FIG. 5, the water 11 accumulated at each interface vaporizes and expands, pushing up the resin body 10 and changing the external shape of the device. And cracks 15 are likely to occur. When the crack 15 occurs, the bonding wire 7 may be cut off, and water or contaminants may enter through the crack 15 to cause corrosion (corrosion) of the electrode portion 6 of the semiconductor chip 5. .

このクラックは、装置の外形に使用される樹脂の材
料,材料の特性,半導体チップサイズ等に大きく依存
し、特に、パッケージ中に占める半導体チップの割合が
大きくなるにつれて、クラックは発生しやすい。
This crack largely depends on the material of the resin used for the outer shape of the device, the characteristics of the material, the size of the semiconductor chip, etc. In particular, the crack easily occurs as the proportion of the semiconductor chip in the package increases.

また、クラックが発生すると同時に、ベット14の下面
が平坦面であり、樹脂体10とは密着性が悪いため、樹脂
体10を押し上げる力によってベッド14の下面と樹脂体10
とが剥れやすい。そのため、装置の信頼性が劣化する。
Further, at the same time when a crack is generated, the lower surface of the bed 14 is a flat surface and has poor adhesion to the resin body 10, so the lower surface of the bed 14 and the resin body 10 are pushed by the force pushing up the resin body 10.
Easy to peel off. Therefore, the reliability of the device deteriorates.

(発明が解決しようとする課題) 本発明は、上記のような従来技術の欠点を除去し、ヒ
ートショックによるパッケージクラックの発生の抑制
と、ベットの下面と樹脂との密着性を向上させることを
目的とする。
(Problems to be Solved by the Invention) The present invention aims to eliminate the above-mentioned drawbacks of the prior art, suppress the generation of package cracks due to heat shock, and improve the adhesion between the lower surface of the bed and the resin. To aim.

[発明の構成] (課題を解決するための手段) 上記目的を達成するために、本発明においては、上面
に半導体チップが載置されたベットと、このベットの下
面に接続され、かつ、このベット面内の任意の方向に沿
った長辺を備えた形状を有する、空間を介して下方に突
出された第一の突出部材と、この任意の方向と異なる前
記ベット面内の方向に沿った長辺を備えた形状を有す
る、空間を介して下方に突出された第二の突出部材と、
インナーリード部とアウターリード部を有するリード
と、前記ベット、第一の突出部材、第二の突出部材、半
導体チップ及び、インナーリード部とが封止される樹脂
体とを備えていることを特徴とする樹脂封止型半導体装
置を提供し、又、前記突出部材がベットを抜き打ち加工
して形成されてなることを特徴とする前記樹脂封止型半
導体装置を提供し、さらに、前記突出部材が、ベットと
別個に形成され、前記ベットの下面に取り付けられてな
ることを特徴とする前記樹脂封止型半導体装置を提供す
る。
[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, in the present invention, a bed on which a semiconductor chip is mounted, and a bottom surface of the bed, which is connected to the bed, A first projecting member having a shape with long sides extending in an arbitrary direction in the bed surface and protruding downward through a space; and a direction in the bed surface different from the arbitrary direction. A second protruding member having a shape with a long side and protruding downward through a space;
It is provided with a lead having an inner lead portion and an outer lead portion, a resin body for sealing the bed, the first protruding member, the second protruding member, the semiconductor chip, and the inner lead portion. And a resin-encapsulated semiconductor device, wherein the protruding member is formed by punching a bed. The resin-encapsulated semiconductor device is provided separately from the bed and attached to the lower surface of the bed.

(作用) このように構成されたものにおいては、ベット部の下
面に空間を介して下方に突出する突出部材を設けること
によって、樹脂封止型半導体装置のパッケージ内に溜ま
る水分を分散することができ、ヒートショックによる熱
応力による樹脂体を押し上げる力も分散できるので、ク
ラックの発生を抑制することができ、また、突出部材に
よる空間の中に樹脂体を充填しているので、ベットの下
面と樹脂体との密着性を向上させることが可能となる。
(Operation) In the case of such a configuration, by providing a projecting member projecting downward through the space on the lower surface of the bed portion, it is possible to disperse the water accumulated in the package of the resin-sealed semiconductor device. Since it is possible to disperse the force that pushes up the resin body due to the thermal stress due to the heat shock, it is possible to suppress the occurrence of cracks. Also, since the resin body is filled in the space by the protruding member, the lower surface of the bed and the resin It is possible to improve the adhesion to the body.

(実施例) 以下、本発明の第1の実施例を第1図を参照して説明
する。同図(a)はベット1の斜視図,同図(b)は、
同図(a)のA−A′線に沿う断面図,同図(c)は、
一実施例による樹脂封止型半導体装置で、同図(a)の
ベット1のB−B′線に沿って切断した断面図である。
まず、同図(a)(b)に示すようにリードフレームの
ベット1は、その下面に複数個の突出部材2を形成して
いる。この突出部材2は、平板上のベット1の所定部材
を打ち抜き加工して、ベット1下面の下方に空間を介し
て突出する形状に形成している。そして、ベット1の上
面に、エポキシ樹脂等の接着剤4を介して、半導体チッ
プ5の各電極部6とインナーリード部8とをボンディン
グワイヤー7で接続し、その後、ベット1,インナーリー
ド部8,及び半導体チップ5を樹脂体10で封止する。ここ
で、突出部材2の空間3の部分にも、前記と同様の樹脂
体10を充填させる。なお、図面の9は、アウターリード
部である。
(Example) Hereinafter, a first example of the present invention will be described with reference to FIG. The figure (a) is a perspective view of the bed 1, and the figure (b) is
A sectional view taken along the line AA ′ of FIG.
FIG. 6 is a cross-sectional view of the resin-sealed semiconductor device according to the embodiment, taken along the line BB ′ of the bed 1 in FIG.
First, as shown in FIGS. 1A and 1B, a lead frame bed 1 has a plurality of protruding members 2 formed on the lower surface thereof. The protruding member 2 is formed by punching out a predetermined member of the bed 1 on a flat plate and protruding below the lower surface of the bed 1 through a space. Then, each electrode portion 6 of the semiconductor chip 5 and the inner lead portion 8 are connected to the upper surface of the bed 1 via a bonding wire 7 via an adhesive 4 such as an epoxy resin, and then the bed 1 and the inner lead portion 8 are connected. , And the semiconductor chip 5 is sealed with the resin body 10. Here, the space 3 of the protruding member 2 is also filled with the same resin body 10 as described above. Incidentally, 9 in the drawing is an outer lead portion.

本実施例によれば、ベット1の下面に突出部材2を設
けた構造になっているため、装置内の各界面に溜まる水
分11が分散し、ヒートショックの熱応力によるベット1
下部の樹脂体を押し上げる力を分散することができる。
According to the present embodiment, since the protruding member 2 is provided on the lower surface of the bed 1, the water 11 accumulated at each interface in the apparatus is dispersed, and the bed 1 due to the thermal stress of the heat shock is dispersed.
It is possible to disperse the force that pushes up the lower resin body.

また、突出部材2による空間3の中に樹脂体10を充填
した構造になっているので、ベット1の下面と樹脂体10
との剥離防止が可能となり、クラックが発生しにくい。
以上のことから、装置の信頼性が向上する。
Moreover, since the resin body 10 is filled in the space 3 formed by the protruding member 2, the lower surface of the bed 1 and the resin body 10 are
It is possible to prevent peeling from the surface and cracks are less likely to occur.
From the above, the reliability of the device is improved.

第2図は、本発明の第2の実施例を示す図で同図
(a)は、ベットの斜視図,同図(b)は、同図(a)
のベットを用いた樹脂封止型半導体装置の断面の概略図
である。ここで、第1の実施例と同一部分には、同一番
号を付して詳細な説明は省略する。この実施例では、第
1の実施例と同様にベット1の複数箇所を打ち抜き加工
し、下面に、複数個の突出部材2を形成するが、その両
脇に貫通した穴12を形成する。この実施例によれば、上
記第1の実施例と同様に、クラックの発生の抑制、ベッ
トの下面と樹脂体との剥離防止ができることは勿論であ
るが、突出部材2の両脇に貫通した穴12を設けているの
で、空間に樹脂体を充填しやすく、ボイドの発生を防止
することができる。
FIG. 2 is a diagram showing a second embodiment of the present invention. FIG. 2 (a) is a perspective view of a bed, and FIG. 2 (b) is the same figure (a).
3 is a schematic cross-sectional view of a resin-sealed semiconductor device using the bed of FIG. Here, the same parts as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, as in the first embodiment, a plurality of portions of the bed 1 are punched and a plurality of protruding members 2 are formed on the lower surface, but holes 12 penetrating both sides are formed. According to this embodiment, similarly to the first embodiment, it is of course possible to suppress the generation of cracks and prevent the lower surface of the bed from being separated from the resin body, but the protrusion member 2 is penetrated on both sides. Since the holes 12 are provided, it is possible to easily fill the space with the resin body and prevent generation of voids.

第3図は、本発明の第3の実施例を示すもので、ベッ
トの斜視図である。ここで、第1の実施例と同一部材に
は、同一番号を付して詳細な説明は、省略する。この実
施例では、突出部材13をベット1とは別に形成し、ベッ
ト1の下面に取付けるもので、上記第1の実施例と同様
に、クラックの発生の抑制、ベットの下面と樹脂体との
剥離防止ができる。
FIG. 3 shows a third embodiment of the present invention and is a perspective view of a bed. Here, the same members as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the projecting member 13 is formed separately from the bed 1, and is attached to the lower surface of the bed 1. Therefore, similarly to the first embodiment, the generation of cracks is suppressed and the lower surface of the bed and the resin body are separated from each other. Can prevent peeling.

ここで、突出部材の材料及び取り付け方法について
は、特に限定されないが、ベットと同一材料又は、それ
に近い性質を持つものであれば望ましい。
Here, the material and mounting method of the protruding member are not particularly limited, but it is desirable that the material is the same as or similar to that of the bed.

[発明の効果] 以上、詳述したように、本発明によれば、ベットの下
面と樹脂体との密着性を向上させ、ヒートショックによ
るクラックの発生を抑制することができるので、装置の
信頼性が向上し、歩留りも向上する。
[Effects of the Invention] As described in detail above, according to the present invention, the adhesion between the lower surface of the bed and the resin body can be improved, and the occurrence of cracks due to heat shock can be suppressed. And the yield is improved.

【図面の簡単な説明】[Brief description of drawings]

第1図は、本発明に係る樹脂封止型半導体装置の一実施
例を示すもので、同図(a)は、ベットの斜視図、同図
(b)は、同図(a)のベットのA−A′に沿う断面
図、同図(c)は、同図(a)のベットをB−B′に沿
って切断した樹脂封止型半導体装置の断面図、 第2図は、本発明に係る第2の実施例の樹脂封止型半導
体装置を示すもので、同図(a)は、ベットの斜視図,
同図(b)は、同図(a)のベットをC−C′線に沿っ
て切断した樹脂封止型半導体装置の概略断面図、 第3図は、本発明の第3の実施例の樹脂封止型半導体装
置に於けるベットの斜視図, 第4図は、従来の樹脂封止型半導体装置を示すもので、
同図(a)は、リードフレームの平面図、同図(b)
は、同図(a)のベットをD−D′線に沿って切断した
樹脂封止型半導体装置の断面図, 第5図は、ヒートショック後の従来の樹脂封止型半導体
装置の断面図である。 1……ベット 2……突出部材 3……空間 4……接着剤 5……半導体チップ 6……電極部材 7……ボンディングワイヤー 8……インナーリード部 9……アウターリード部 10……樹脂体 11……水分 12……貫通した穴 13……突出部材 14……従来のベット 15……クラック
FIG. 1 shows an embodiment of a resin-sealed semiconductor device according to the present invention. FIG. 1 (a) is a perspective view of a bed, and FIG. 1 (b) is a bed of FIG. 2A is a cross-sectional view taken along the line A-A ', FIG. 2C is a cross-sectional view of the resin-sealed semiconductor device obtained by cutting the bed shown in FIG. 3A along the line BB', and FIG. The resin-encapsulated semiconductor device according to the second embodiment of the present invention is shown in FIG.
3B is a schematic sectional view of a resin-sealed semiconductor device obtained by cutting the bed shown in FIG. 3A along the line C-C ', and FIG. 3 shows a third embodiment of the present invention. FIG. 4 is a perspective view of a bed in a resin-sealed semiconductor device, and FIG. 4 shows a conventional resin-sealed semiconductor device.
FIG. 3A is a plan view of the lead frame, and FIG.
Is a cross-sectional view of the resin-encapsulated semiconductor device obtained by cutting the bed of FIG. 5A along the line D-D '. FIG. 5 is a cross-sectional view of the conventional resin-encapsulated semiconductor device after heat shock. Is. 1 ... Bed 2 ... Projection member 3 ... Space 4 ... Adhesive 5 ... Semiconductor chip 6 ... Electrode member 7 ... Bonding wire 8 ... Inner lead part 9 ... Outer lead part 10 ... Resin body 11 …… Moisture 12 …… Through hole 13 …… Projecting member 14 …… Conventional bed 15 …… Crack

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】上面に半導体チップが載置されたベット
と、 このベットの下面に接続され、かつ、このベット面内の
任意の方向に沿った長辺を備えた形状を有する、空間を
介して下方に突出された第一の突出部材と、 この任意の方向と異なる前記ベット面内の方向に沿った
長辺を備えた形状を有する、空間を介して下方に突出さ
れた第二の突出部材と、 インナーリード部とアウターリード部を有するリード
と、 前記ベット、第一の突出部材、第二の突出部材、半導体
チップ及び、インナーリード部とが封止される樹脂体と
を備えていることを特徴とする樹脂封止型半導体装置。
1. A bed having a semiconductor chip mounted on the upper surface thereof and a shape having a long side connected to the lower surface of the bed and extending in an arbitrary direction within the bed surface. And a second protrusion protruding downward through a space, which has a shape including a first protruding member protruding downward and a long side along a direction in the bed surface different from the arbitrary direction. A member, a lead having an inner lead portion and an outer lead portion, a resin body in which the bed, the first protruding member, the second protruding member, the semiconductor chip, and the inner lead portion are sealed. A resin-encapsulated semiconductor device characterized by the above.
【請求項2】前記第一及び第二の突出部材がベットを抜
き打ち加工して形成されてなることを特徴とする前記特
許請求の範囲第1項記載の樹脂封止型半導体装置。
2. The resin-encapsulated semiconductor device according to claim 1, wherein the first and second projecting members are formed by punching a bed.
【請求項3】前記第一及び第二の突出部材が、ベットと
別個に形成され、前記ベットの下面に取り付けられてな
ることを特徴とする前記特許請求の範囲第1項記載の樹
脂封止型半導体装置。
3. The resin encapsulation according to claim 1, wherein the first and second projecting members are formed separately from the bed and are attached to the lower surface of the bed. Type semiconductor device.
JP2117741A 1990-05-09 1990-05-09 Resin-sealed semiconductor device Expired - Fee Related JP2515036B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2117741A JP2515036B2 (en) 1990-05-09 1990-05-09 Resin-sealed semiconductor device
KR1019910007417A KR950003234B1 (en) 1990-05-09 1991-05-08 Resin seal type semiconductor device
US07/873,689 US5175610A (en) 1990-05-09 1992-04-24 Resin molded type semiconductor device having a metallic plate support

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2117741A JP2515036B2 (en) 1990-05-09 1990-05-09 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPH0415945A JPH0415945A (en) 1992-01-21
JP2515036B2 true JP2515036B2 (en) 1996-07-10

Family

ID=14719156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2117741A Expired - Fee Related JP2515036B2 (en) 1990-05-09 1990-05-09 Resin-sealed semiconductor device

Country Status (2)

Country Link
JP (1) JP2515036B2 (en)
KR (1) KR950003234B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129811A (en) * 1995-10-30 1997-05-16 Mitsubishi Electric Corp Resin sealed semiconductor device
JPH09153586A (en) * 1995-12-01 1997-06-10 Texas Instr Japan Ltd Semiconductor device, its manufacture and lead frame

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482554A (en) * 1987-09-24 1989-03-28 Mitsubishi Electric Corp Resin-sealed semiconductor device

Also Published As

Publication number Publication date
JPH0415945A (en) 1992-01-21
KR950003234B1 (en) 1995-04-06

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