JP2000306924A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a field-effect transistor capable of achieving highly controlled adjustment of the depths of gate recesses by making adjustments per superlattice layer or cycle, while ensuring uniformity in their depths, based on selective etching. SOLUTION: A buffer layer 12 and a channel layer 13 are sequentially laminated on a semi-insulating GaAs substrate 11, and an AlAs/GaAs superlattice 14 is laminated as a gate recess layer in the desired number of cycles, and an n+-GaAs layer 15 is then formed (a). The layer 15 is selectively etched toward the first layer of the superlattice 14 to be removed, thereby forming a first-stage recess 16 (b). After forming a gate pattern on an SiO2 film 17 with a desired opening width, a GaAs layer 14b of the superlattice 14 is selectively etched toward the AlAs layer 14a to remove the superlattice 14 for a single cycle. This selective etching step is repeated to achieve the desired depth of recess, thereby forming a gate recess 18 (c), after which a gate electrode 19 and an ohmic electrode 20 are formed (d).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly, to a gate recess depth per superlattice layer or one period while ensuring uniformity of the gate recess depth by selective etching. TECHNICAL FIELD The present invention relates to a two-stage recessed structure field effect transistor capable of adjusting the resistance and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a method of manufacturing a two-stage recess structure field effect transistor, for example, "High Gain
and high Efficiency K-Ba
ndPower HEMT with WSi / Au
T-Shaped Gate "(T. Kunii et.
al, 1997 MTT-S Digest pp.
1187-1190).

In this manufacturing method, as shown in FIG. 9A, an n ⁺ -GaAs layer is first formed using an epitaxial substrate.
The first-stage recess is formed by selectively removing the layer 911 from the AlGaAs layer 910 serving as an etching stopper layer with citric acid [see FIG. 9B].

[0004] Next, the gate recess layer, n ^-- Ga
The As layer 99 is made of i-AlGaAs by dry etching.
A gate recess is formed by selectively etching away the s layer 98 [see FIG. 9C]. Finally, by forming a gate electrode 914 and an ohmic electrode 913, a two-stage recess structure field effect transistor is manufactured (see FIG. 9D).

In FIG. 9, reference numeral 91 denotes semi-insulating GaAs.
s substrate, 92, 94 and 96 are i-AlGaAs layers, 9
3, 97 is an n ⁺ -AlGaAs layer, 95 is i-inG
The aAs layer 912 is a SiO ₂ film.

[0006]

In the above-mentioned conventional method for manufacturing a two-stage recess structure field effect transistor, the gate recess depth is controlled by selective etching while ensuring a high gate recess depth uniformity. It is impossible to do.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a highly controlled gate for each superlattice layer or period while ensuring uniformity of the gate recess depth by selective etching.
An object of the present invention is to provide a field effect transistor capable of adjusting a recess depth and a method of manufacturing the same.

[0008]

A first field-effect transistor according to the present invention comprises a buffer layer, a channel layer, a gate recess layer, and n ⁺ -GaAs on a semi-insulating GaAs substrate.
A field-effect transistor in which the layers are sequentially stacked,
The gate recess layer is made of an AlAs / GaAs superlattice.

A second field effect transistor according to the present invention is a field effect transistor in which a buffer layer, a channel layer, a gate recess layer, and an n ⁺ -GaAs layer are sequentially laminated on a semi-insulating GaAs substrate. The gate recess layer is made of an InGaP / GaAs superlattice.

A third field effect transistor according to the present invention is a field effect transistor in which a buffer layer, a channel layer, a gate recess layer, and an n ⁺ -GaAs layer are sequentially stacked on a semi-insulating GaAs substrate, The gate recess layer comprises an InGaP / AlGaAs superlattice.

A fourth field effect transistor according to the present invention is a field effect transistor in which a buffer layer, a channel layer, a gate recess layer, and an n ⁺ -InGaAs layer are sequentially stacked on a high-resistance InP substrate. The gate recess layer is made of an InP / InGaAs superlattice.

In a fifth field effect transistor according to the present invention, a buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, a gate recess layer, and an n ⁺ -GaAs layer are sequentially formed on a semi-insulating GaAs substrate. A stacked field effect transistor, wherein the gate recess layer is AlAs /
It consists of a GaAs superlattice.

In a sixth field effect transistor according to the present invention, a buffer layer, a channel layer, an electron supply layer doped with n-type impurities, a gate recess layer, and an n ⁺ -GaAs layer are sequentially formed on a semi-insulating GaAs substrate. A stacked field effect transistor, wherein said gate recess layer is InGaP.
/ GaAs superlattice.

In a seventh field effect transistor according to the present invention, a buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, a gate recess layer, and an n ⁺ -GaAs layer are sequentially formed on a semi-insulating GaAs substrate. A stacked field effect transistor, wherein said gate recess layer is InGaP.
/ AlGaAs superlattice.

An eighth field-effect transistor according to the present invention
Means that a buffer layer, a channel layer, and n are formed on a high-resistance InP substrate.
Supply layer and gate recess layer doped with p-type impurities
And n ⁺ Field effect in which -InGaAs layer is sequentially laminated
A transistor, wherein the gate recess layer is InP / I
It consists of an nGaAs superlattice.

A first method of manufacturing a field effect transistor according to the present invention comprises the steps of laminating a buffer layer and a channel layer on a semi-insulating GaAs substrate, and forming an Al layer on the channel layer.
Growing an As / GaAs superlattice for a desired period; and forming n ⁺ -GaAs on the AlAs / GaAs superlattice.
Stacking layers and selectively etching the n ⁺
Forming a first recess by selectively etching away the GaAs layer with respect to the first AlAs layer of the AlAs / GaAs superlattice, and alternately using the AlAs layer and the GaAs layer of the AlAs / GaAs superlattice; Selectively etching to form a gate recess.

According to a second method of manufacturing a field effect transistor according to the present invention, a buffer layer and a channel layer are laminated on a semi-insulating GaAs substrate, and In is formed on the channel layer.
Growing a GaP / GaAs superlattice for a desired period; and forming n ⁺ -GaAs on the InGaP / GaAs superlattice.
stacking an s layer and selectively etching the n ⁺
Forming a first-stage recess by selectively etching away the GaAs layer with respect to the first InGaP layer of the InGaP / GaAs superlattice, and alternately using the InGaP layer and the GaAs layer of the InGaP / GaAs superlattice; Selectively etching to form a gate recess.

According to a third method of manufacturing a field effect transistor of the present invention, a buffer layer and a channel layer are stacked on a semi-insulating GaAs substrate, and an In layer is formed on the channel layer.
A step of growing a GaP / AlGaAs superlattice for a desired period, and forming n ⁺ on the InGaP / AlGaAs superlattice.
Stacking a n-GaAs layer and selectively etching the n ⁺ -GaAs layer into the InGaP / AlGaAs layer.
Forming a first-stage recess by selectively etching and removing the first InGaP layer of the superlattice;
The InGaP layer of the P / AlGaAs superlattice and AlGa
Forming a gate recess by alternately selectively etching the As layer.

According to a fourth method of manufacturing a field effect transistor according to the present invention, a buffer layer and a channel layer are laminated on a high-resistance InP substrate;
Growing an InGaAs superlattice for a desired period;
N ⁺ -InGaAs on the InP / InGaAs superlattice
stacking an s layer and selectively etching the n ⁺
Forming a first recess by selectively etching and removing the InGaAs layer with respect to the first InP layer of the InP / InGaAs superlattice, and alternately using the InP layer and the InGaAs layer of the InP / InGaAs superlattice; Selectively etching to form a gate recess.

A fifth method of manufacturing a field-effect transistor according to the present invention comprises the steps of laminating a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate; AlAs / GaAs on top
growing the s superlattice for a desired period;
Stacking an n ⁺ -GaAs layer on the / GaAs superlattice, and selectively removing the n ⁺ -GaAs layer by selective etching with respect to the first AlAs layer of the AlAs / GaAs superlattice. Forming a first recess; and forming a gate recess by alternately selectively etching the AlAs layer and the GaAs layer of the AlAs / GaAs superlattice.

According to a sixth method of manufacturing a field effect transistor of the present invention, a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity are stacked on a semi-insulating GaAs substrate. InGaP / Ga on top
Growing a As superlattice for a desired period;
laminating the n ⁺ -GaAs layer aP / GaAs super lattice, the n ⁺ -GaAs by selective etching
The layer is the first layer of InGaP / GaAs superlattice, InGa
Forming a first recess by selectively etching away the P layer; and forming the first recess in the InGaP / GaAs superlattice.
forming a gate recess by alternately selectively etching the nGaP layer and the GaAs layer.

A seventh method of manufacturing a field effect transistor according to the present invention comprises the steps of: laminating a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate; InGaP / Al on top
Growing a GaAs superlattice for a desired period;
laminating the n ⁺ -GaAs layer NGAP / AlGaAs super lattice, the by selective etching n ⁺
Forming a first-stage recess by selectively etching away the GaAs layer from the first InGaP layer of the InGaP / AlGaAs superlattice;
selectively etching the InGaP layer and the AlGaAs layer of the aAs superlattice alternately to form a gate recess.

An eighth method of manufacturing a field effect transistor according to the present invention comprises the steps of: laminating a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a high resistance InP substrate; InP / InGaAs
Growing a superlattice for a desired period;
stacking an n ⁺ -InGaAs layer on the nGaAs superlattice, and selectively etching the n ⁺ -InGa
The As layer is replaced with the In layer of the first layer of the InP / InGaAs superlattice.
Forming a first-stage recess by selectively etching away the P layer; and forming the first recess in the InP / InGaAs superlattice.
forming a gate recess by alternately selectively etching the nP layer and the InGaAs layer.

That is, in the method of manufacturing a field effect transistor according to the present invention, AlAs / GaAs, InGaP / GaAs, and InAs are formed as gate recess layers on the bottom of the first recess.
Either a GaP / AlGaAs or InP / InGaAs superlattice is inserted, and a selective etching method is applied to the formation of the gate recess, and the superlattice is etched one layer or one period at a time.

By selectively etching the superlattice one layer or one cycle at a time to form a gate recess, it is possible to secure a high uniformity of the gate recess depth by the selective etching while maintaining the uniformity of the gate recess by one layer or one cycle. Of the gate recess depth can be controlled with high control. For example, an AlAs layer has four molecular layers (hereinafter, referred to as one molecular layer = 1ML), GaAs
When the layer is a 4 ML superlattice, one cycle of the superlattice is etched in one cycle of the selective etching step, so that about 2 nm
It is possible to adjust the depth of the gate recess every time.

[0026]

Next, an embodiment of the present invention will be described with reference to the drawings. FIGS. 1A to 1D are cross-sectional views showing a manufacturing process of a field-effect transistor according to a first embodiment of the present invention. In the figure, in the manufacturing process of the field effect transistor according to the first embodiment of the present invention, MB
E (Molecular Beam Epitaxy:
Molecular beam epitaxy) or MOCVD (Metalor
ganic Chemical Vapor Depos
Ition: semi-insulating G by metalorganic chemical vapor deposition)
After laminating a buffer layer 12 and a channel layer 13 in this order on an aAs substrate 11, AlAs / Ga is formed as a gate recess layer.
As superlattice 14 is laminated for a desired period, and finally n ⁺ −
A GaAs layer 15 is grown [see FIG. 1 (a)].

Next, for example, using a photoresist as a mask and a citric acid-based etchant, the first layer of AlA
An initial recess 16 is formed by selectively removing the n ⁺ -GaAs layer 15 by etching from the s layer 14a. At this time, the AlAs layer 14a on the surface to be etched is dissolved and removed at the time of washing with water after the etching, and the GaAs layer 1 is removed.
4b is exposed [see FIG. 1 (b)].

Subsequently, a gate pattern is formed with a desired opening width on the SiO2 film 17, for example, and a gate recess forming step is performed. Using the SiO ₂ film 17 as a mask, the GaAs 14b exposed on the surface by the citric acid-based selective etchant is removed from the AlAs 14 as in the formation of the first recess 16.
a is selectively removed by etching.

As described above, the AlAs layer 14a is made of Ga
In the case of the AlAs / GaAs superlattice 14, one cycle of the superlattice is etched and removed in one cycle of the selective etching step, because the As layer 14b is dissolved and removed at the time of washing with water after the etching. That is, in the case of the AlAs / GaAs superlattice 14, for example, the AlAs layer 14a is formed with an accuracy of one period of the superlattice.
Is 4ML and the GaAs layer 14b is a 4ML superlattice,
The depth of the gate recess can be adjusted with an accuracy of about every 2 nm.

The above-described cycle is repeated until a desired recess depth is reached, and after the gate recess 18 is formed (see FIG. 1C), a gate electrode 19 and an ohmic electrode 20 are formed to form a two-step recess structure electric field. The effect transistor is completed [see FIG. 1 (d)].

FIG. 2 is a sectional view showing the structure of a field effect transistor according to a second embodiment of the present invention. In the figure, the field effect transistor according to the second embodiment of the present invention is the same as the field effect transistor according to the first embodiment of the present invention, except that the gate recess layer is an InGaP / GaAs superlattice 24, and the GaAs layer 24b of the InGaP layer 24a. Hydrochloric acid (HCl: H ₂ O) as a selective etchant for
= 1: 1), a sulfuric acid-based etchant is used as a selective etchant for the GaAs layer 24b with respect to the InGaP layer 24a. In addition, the first recess is an n ⁺ -GaAs layer 2
5 is formed using the sulfuric acid-based etchant which is a selective etchant for the InGaP layer 24a.

In the case of the field effect transistor according to the second embodiment of the present invention, the depth of the gate recess can be adjusted with the accuracy of one superlattice layer. In FIG. 2, 21 is a semi-insulating GaAs substrate, 22 is a buffer layer, 23 is a channel layer, 25 is an n ⁺ -GaAs layer, 26 is a gate electrode,
7 is an ohmic electrode.

FIG. 3 is a sectional view showing the structure of a field effect transistor according to a third embodiment of the present invention. In the figure, the field effect transistor according to the third embodiment of the present invention is the same as the field effect transistor according to the first embodiment of the present invention, except that the gate recess layer is an InGaP / AlGaAs superlattice 34, and the AlGaAs layer 3 of the InGaP layer 34a.
Dilute hydrochloric acid (HCl:
H ₂ O = 1: 1), InGa of the AlGaAs layer 34b
A sulfuric acid-based etchant is used as a selective etchant for the P layer 34a. The first recess is n ⁺ −
The GaAs layer 35 is formed using the sulfuric acid-based etchant which is a selective etchant for the InGaP layer 34a.

In the case of the field effect transistor according to the third embodiment of the present invention, the depth of the gate recess can be adjusted with the accuracy of one superlattice layer. 3, 31 is a semi-insulating GaAs substrate, 32 is a buffer layer, 33 is a channel layer, 35 is an n ⁺ -GaAs layer, 36 is a gate electrode,
7 is an ohmic electrode.

FIG. 4 is a sectional view showing the structure of a field effect transistor according to a fourth embodiment of the present invention. In the figure, the field effect transistor according to the fourth embodiment of the present invention is the same as the field effect transistor according to the first embodiment of the present invention except that the semi-insulating GaAs substrate is replaced with the high-resistance InP substrate 4.
1, the n ⁺ -GaAs layer is replaced with an n ⁺ -InGaAs layer 45;
The gate recess layer is made of an InP / InGaAs superlattice 44, and dilute hydrochloric acid is used as a selective etchant for the InGaAs layer 44b of the InP layer 44a, and a phosphoric acid-based etchant is used as a selective etchant for the InP layer 44a of the InGaAs layer 44b. A gate recess is formed.

In the case of the field effect transistor according to the fourth embodiment of the present invention, the precision gate recess depth of one superlattice layer can be adjusted. In FIG. 4, reference numeral 42 denotes a buffer layer, 43 denotes a channel layer, 46 denotes a gate electrode, and 47 denotes an ohmic electrode.

FIGS. 5A to 5D are cross-sectional views showing the steps of manufacturing a field effect transistor according to the fifth embodiment of the present invention. In the figure, in the manufacturing process of the field effect transistor according to the fifth embodiment of the present invention, MBE or M
After a buffer layer 52, a channel layer 53, and an electron supply layer 54 doped with an n-type impurity are sequentially stacked on a semi-insulating GaAs substrate 51 by an OCVD method, an AlAs / GaAs superlattice 55 is stacked as a gate recess layer. And finally n ⁺
A GaAs layer 56 is grown [see FIG. 5 (a)].

Next, for example, using a photoresist as a mask, a citric acid-based etchant is used to form the AlA of the first layer of the superlattice.
An initial recess 57 is formed by selectively etching away the n ⁺ -GaAs layer 56 from the s layer 55a. At this time, the AlAs layer 55a on the surface to be etched is dissolved and removed at the time of washing with water after the etching, and the GaAs layer 55a is removed.
The layer 55b is exposed [see FIG. 5B].

Subsequently, a gate pattern is formed with a desired opening width on the SiO ₂ film 58, for example, and a gate recess forming step is performed. Using the SiO ₂ film 58 as a mask, the GaAs layer 55b exposed on the surface by the citric acid-based selective etchant
The layer 55a is selectively removed by etching.

As described above, the AlAs layer 55a is made of Ga
In the case of the AlAs / GaAs superlattice 55, one cycle of the superlattice is etched and removed in one cycle of the selective etching step, because the As layer 55b is melted and removed at the time of water washing after the etching. That is, in the case of the AlAs / GaAs superlattice 55, for example, the AlAs layer 55a can be formed with an accuracy of one period of the superlattice.
Is 4 ML and the GaAs layer 55 b is a 4 ML super lattice,
The depth of the gate recess can be adjusted with an accuracy of about every 2 nm.

The above cycle is repeated until a desired recess depth is obtained, and after the gate recess 59 is formed (see FIG. 5C), a gate electrode 510 and an ohmic electrode 511 are formed to form a two-step recessed structure electric field. The effect transistor is completed [see FIG. 5D].

FIG. 6 is a sectional view showing the structure of a field effect transistor according to a sixth embodiment of the present invention. In the figure, the field effect transistor according to the sixth embodiment of the present invention is the same as the field effect transistor according to the fifth embodiment of the present invention, except that the gate recess layer is an InGaP / GaAs superlattice 65, and the GaAs layer 65b of the InGaP layer 65a. Hydrochloric acid (HCl: H ₂ O) as a selective etchant for
= 1: 1), and a sulfuric acid-based etchant is used as a selective etchant for the GaAs layer 65b with respect to the InGaP layer 65a. In addition, the first-stage recess is an n ⁺ -GaAs layer 6.
6 is formed using the sulfuric acid-based etchant which is a selective etchant for the InGaP layer 65a.

In the case of the field effect transistor according to the sixth embodiment of the present invention, the depth of the gate recess can be adjusted with the accuracy of one superlattice layer. 6, reference numeral 61 denotes a semi-insulating GaAs substrate, 62 denotes a buffer layer, 63 denotes a channel layer, 64 denotes an electron supply layer doped with an n-type impurity, 66 denotes an n ⁺ -GaAs layer, and 67 denotes a gate electrode. And 68 are ohmic electrodes.

FIG. 7 is a sectional view showing the structure of a field effect transistor according to a seventh embodiment of the present invention. In the figure, the field effect transistor according to the seventh embodiment of the present invention is the same as the field effect transistor according to the fifth embodiment of the present invention, except that the gate recess layer is an InGaP / AlGaAs superlattice 75, and the AlGaAs layer 7 of the InGaP layer 75a.
Dilute hydrochloric acid (HCl:
H ₂ O = 1: 1), InGa of the AlGaAs layer 75b
A sulfuric acid-based etchant is used as a selective etchant for the P layer 75a. The first recess is n ⁺ -G
The aAs layer 76 is formed using the sulfuric acid-based etchant which is a selective etchant for the InGaP layer 75a.

In the case of the field effect transistor according to the seventh embodiment of the present invention, the depth of the gate recess can be adjusted with the accuracy of one superlattice layer. 7, reference numeral 71 denotes a semi-insulating GaAs substrate, 72 denotes a buffer layer, 73 denotes a channel layer, 74 denotes an electron supply layer doped with an n-type impurity, 76 denotes an n ⁺ -GaAs layer, and 77 denotes a gate electrode. , 78 are ohmic electrodes.

FIG. 8 is a sectional view showing a structure of a field effect transistor according to an eighth embodiment of the present invention. In the figure, the field-effect transistor according to the eighth embodiment of the present invention is the same as the field-effect transistor according to the fifth embodiment of the present invention except that the substrate is a high-resistance InP substrate 81, n ⁺ -GaAs.
The s layer is replaced with an n ⁺ -InGaAs layer 86, the gate recess layer is made of an InP / InGaAs superlattice 85, and the
Dilute hydrochloric acid (HCl: H ₂ O = 1: 1), In as a selective etchant for the InGaAs layer 85b of the layer 85a.
First-stage recesses and gate recesses are formed by using a phosphoric acid-based etchant as a selective etchant for the GaAs layer 85b with respect to the InP layer 85a.

In the case of the field effect transistor according to the eighth embodiment of the present invention, the depth of the gate recess can be adjusted with the accuracy of one superlattice layer. 8, reference numeral 82 denotes a buffer layer, 83 denotes a channel layer, 84 denotes an electron supply layer doped with an n-type impurity, 87 denotes a gate electrode, and 88 denotes an ohmic electrode.

As described above, by selectively etching the superlattice one layer or one cycle at a time to form the gate recesses, the uniformity of the gate recess depth by the selective etching is ensured and the superlattice one layer or one layer is formed. Highly controlled gain for each cycle
The recess depth can be adjusted. For example, when the AlAs layer is 4 ML and the GaAs layer is 4 ML superlattice, one cycle of the superlattice is etched in one cycle of the selective etching process, so that the gate recess depth can be adjusted about every 2 nm.

The present invention can take the following aspects in connection with the description of the claims.

(1) A buffer layer, a channel layer, a gate recess layer, and n ⁺ -GaAs are formed on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition.
A field-effect transistor in which the layers are sequentially stacked,
A field effect transistor, wherein the gate recess layer is made of an AlAs / GaAs superlattice.

(2) A buffer layer, a channel layer, a gate recess layer, and n ⁺ -GaAs are formed on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition.
A field-effect transistor in which the layers are sequentially stacked,
A field effect transistor, wherein the gate recess layer is made of an InGaP / GaAs superlattice.

(3) A buffer layer, a channel layer, a gate recess layer, and n ⁺ -GaAs are formed on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition.
A field-effect transistor in which the layers are sequentially stacked,
A field effect transistor, wherein the gate recess layer is made of an InGaP / AlGaAs superlattice.

(4) A buffer layer, a channel layer, a gate recess layer, and n ⁺ -InGaAs are formed on a high-resistance InP substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition.
A field-effect transistor in which the layers are sequentially stacked,
A field-effect transistor, wherein the gate recess layer is made of an InP / InGaAs superlattice.

(5) A buffer layer, a channel layer, an electron supply layer doped with n-type impurities, a gate recess layer, and n ⁺ − on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition. A field effect transistor in which a GaAs layer is sequentially laminated, wherein the gate recess layer is made of an AlAs / GaAs superlattice.

(6) A buffer layer, a channel layer, an electron supply layer doped with n-type impurities, a gate recess layer, and n ⁺ − on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition. A field effect transistor in which a GaAs layer is sequentially stacked, wherein the gate recess layer is made of an InGaP / GaAs superlattice.

(7) A buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, a gate recess layer, and n ⁺ − on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition. A field effect transistor in which a GaAs layer is sequentially stacked, wherein the gate recess layer is made of an InGaP / AlGaAs superlattice.

(8) A buffer layer, a channel layer, an electron supply layer doped with n-type impurities, a gate recess layer, and n ⁺ -InGaAs on a high-resistance InP substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition. A field effect transistor in which layers are sequentially stacked, wherein the gate recess layer is made of an InP / InGaAs superlattice.

(9) A step of laminating a buffer layer and a channel layer on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and forming an AlAs / GaAs superlattice on the channel layer And growing n ⁺ -Ga on the AlAs / GaAs superlattice.
Stacking an As layer and selectively etching the n layer.
⁺ -GaAs layer is the first of the AlAs / GaAs superlattice.
Forming a first recess by selectively etching and removing the AlAs layer of the layer, and forming a gate recess by selectively etching the AlAs layer and the GaAs layer of the AlAs / GaAs superlattice alternately. A method for manufacturing a field-effect transistor, comprising:

(10) A step of laminating a buffer layer and a channel layer on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and an InGaP / GaAs superlattice is desired on the channel layer. And growing n ⁺ on the InGaP / GaAs superlattice.
Forming a first-stage recess by selectively etching and removing the n ⁺ -GaAs layer by selective etching with respect to the first InGaP layer of the InGaP / GaAs superlattice by selective etching; The InGaP /
Forming a gate recess by alternately selectively etching the InGaP layer and the GaAs layer of the GaAs superlattice.

(11) A step of stacking a buffer layer and a channel layer on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and an InGaP / AlGaAs superlattice is desired on the channel layer. Growing the n ⁺ -GaAs layer on the InGaP / AlGaAs superlattice, and selectively etching the n ⁺ -GaAs layer into the InGaP / Al
Forming a first-stage recess by selectively etching and removing the first InGaP layer of the GaAs superlattice; and selectively etching the InGaP layer and the AlGaAs layer of the InGaP / AlGaAs superlattice alternately. Forming a recess.

(12) A step of laminating a buffer layer and a channel layer on a high-resistance InP substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and forming an InP / InGaAs superlattice on the channel layer. A step of growing for a period, and n ⁺ -I on the InP / InGaAs superlattice.
stacking an nGaAs layer and selectively etching the n ⁺ -InGaAs layer by the InP / InGaAs.
Forming a first-stage recess by selectively etching and removing the first InP layer of the superlattice;
Forming a gate recess by alternately selectively etching the InP layer and the InGaAs layer of the GaAs superlattice.

(13) A step of stacking a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and AlAs on the supply layer
Growing a / GaAs superlattice for a desired period, stacking an n ⁺ -GaAs layer on the AlAs / GaAs superlattice, and selectively etching the n ⁺ -Ga layer.
The As layer is made of AlA of the first layer of the AlAs / GaAs superlattice.
forming an initial recess by selectively etching away the s layer; and forming the first recess in the AlAs / GaAs superlattice.
The As layer and the GaAs layer are selectively etched alternately to form a gate.
Forming a recess.

(14) A step of stacking a buffer layer, a channel layer and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and InGa on the supply layer
Growing a P / GaAs superlattice for a desired period;
Stacking an n ⁺ -GaAs layer on the InGaP / GaAs superlattice, and selectively etching the n ⁺ -
Forming a first recess by selectively etching and removing the GaAs layer from the first InGaP layer of the InGaP / GaAs superlattice; and alternately changing the InGaP layer and the GaAs layer of the InGaP / GaAs superlattice. Forming a gate recess by selective etching.

(15) A step of stacking a buffer layer, a channel layer and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, InGa on the supply layer
Growing a P / AlGaAs superlattice for a desired period; and n ⁺ -G on the InGaP / AlGaAs superlattice.
laminating an aAs layer; and selectively etching and removing the n ⁺ -GaAs layer from the first InGaP layer of the InGaP / AlGaAs superlattice by selective etching to form a first-stage recess. InGaP /
The InGaP layer of the AlGaAs superlattice and the AlGaAs
Forming a gate recess by alternately selectively etching the layers.

(16) A step of laminating a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on one of a high-resistance InP substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and InP / In on the layer
Growing a GaAs superlattice for a desired period;
laminating the n ⁺ -InGaAs layer nP / InGaAs super lattice, the n ⁺ by selective etching -
An InGaAs layer is formed on the first of the InP / InGaAs superlattice.
Forming a first recess by selectively etching and removing the InP layer of the layer, and forming a gate recess by selectively etching the InP layer and the InGaAs layer of the InP / InGaAs superlattice alternately. A method for manufacturing a field-effect transistor, comprising:

[0066]

As described above, according to the present invention, the superlattice grown as the gate recess layer is selectively etched one layer or one cycle at a time to form the gate recess, thereby forming the gate by selective etching. The effect is that the gate recess depth can be controlled in a highly controlled manner for each layer of the superlattice or for each period while ensuring the uniformity of the recess depth.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing a manufacturing process of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a field-effect transistor according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a configuration of a field-effect transistor according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a configuration of a field-effect transistor according to a fourth embodiment of the present invention.

FIGS. 5A to 5D are cross-sectional views illustrating the steps of manufacturing a field-effect transistor according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a configuration of a field-effect transistor according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a configuration of a field-effect transistor according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view showing a configuration of a field-effect transistor according to an eighth embodiment of the present invention.

FIGS. 9A to 9D are cross-sectional views showing the steps of manufacturing a conventional field-effect transistor.

[Explanation of symbols]

11, 21, 31, 51, 61, 71 Semi-insulating GaAs
s substrate 12, 22, 32, 42, 52, 62, 72, 82 buffer layer 13, 23, 33, 43, 53, 63, 73, 83 channel layer 14 AlAs / GaAs superlattice 14a AlAs layer 14b GaAs layer 15, 25, 35, 56, 66, 76 n ⁺ -GaAs
s layer 16,57 first stage recess 17,58 SiO ₂ film 18,59 gate recess 19,26,36,46,510,67,77,87
Gate electrode 20, 27, 37, 47, 511, 68, 78, 88
Ohmic electrode 24,65 InGaP / GaAs superlattice 24a, 34a, 65a, 75a InGaP layer 24b, 65b GaAs layer 34,75 InGaP / AlGaAs superlattice 34b, 75b AlGaAs layer 41,81 High-resistance InP substrate 44,85 InP / InGaAs superlattice 44a, 85a InP layer 44b, 85b InGaAs layer 45n ⁺ -InGaAs layer 54, 64, 74, 84 Electron supply layer doped with n-type impurity

Claims (16)

[Claims] 1. A field effect transistor in which a buffer layer, a channel layer, a gate recess layer, and an n ⁺ -GaAs layer are sequentially stacked on a semi-insulating GaAs substrate.
A field-effect transistor, wherein the recess layer is made of an AlAs / GaAs superlattice. 2. A field effect transistor in which a buffer layer, a channel layer, a gate recess layer and an n ⁺ -GaAs layer are sequentially stacked on a semi-insulating GaAs substrate.
A field-effect transistor, wherein the recess layer is made of an InGaP / GaAs superlattice. 3. A field effect transistor in which a buffer layer, a channel layer, a gate recess layer, and an n ⁺ -GaAs layer are sequentially laminated on a semi-insulating GaAs substrate.
A field effect transistor, wherein the recess layer is made of an InGaP / AlGaAs superlattice. 4. A field effect transistor in which a buffer layer, a channel layer, a gate recess layer, and an n ⁺ -InGaAs layer are sequentially stacked on a high-resistance InP substrate.
A field-effect transistor, wherein the recess layer is made of an InP / InGaAs superlattice. 5. A field effect transistor in which a buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, a gate recess layer, and an n ⁺ -GaAs layer are sequentially stacked on a semi-insulating GaAs substrate. A field effect transistor, wherein the gate recess layer comprises an AlAs / GaAs superlattice. 6. A field effect transistor in which a buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, a gate recess layer, and an n ⁺ -GaAs layer are sequentially stacked on a semi-insulating GaAs substrate. A field-effect transistor, wherein the gate recess layer comprises an InGaP / GaAs superlattice. 7. A field effect transistor in which a buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, a gate recess layer, and an n ⁺ -GaAs layer are sequentially stacked on a semi-insulating GaAs substrate. A field effect transistor, wherein the gate recess layer is made of an InGaP / AlGaAs superlattice. 8. A buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, and a gate on a high resistance InP substrate.
A field effect transistor in which a recess layer and an n ⁺ -InGaAs layer are sequentially stacked, wherein the gate recess layer comprises an InP / InGaAs superlattice. 9. A step of stacking a buffer layer and a channel layer on a semi-insulating GaAs substrate, and forming an Al layer on the channel layer.
Growing an As / GaAs superlattice for a desired period; and forming n ⁺ -GaAs on the AlAs / GaAs superlattice.
Stacking layers, and selectively etching the n ⁺
Forming a first recess by selectively etching away the GaAs layer with respect to the first AlAs layer of the AlAs / GaAs superlattice, and alternately using the AlAs layer and the GaAs layer of the AlAs / GaAs superlattice; Forming a gate recess by selective etching. 10. A step of laminating a buffer layer and a channel layer on a semi-insulating GaAs substrate;
a step of growing an nGaP / GaAs superlattice for a desired period, and forming n ⁺ -Ga on the InGaP / GaAs superlattice.
Stacking an As layer and selectively etching the n layer.
Forming a first-stage recess by selectively etching away the ⁺ -GaAs layer with respect to the first InGaP layer of the InGaP / GaAs superlattice;
forming a gate recess by alternately selectively etching the InGaP layer and the GaAs layer of the s superlattice. 11. A step of laminating a buffer layer and a channel layer on a semi-insulating GaAs substrate;
a step of growing an nGaP / AlGaAs superlattice for a desired period, and forming n ⁺ on the InGaP / AlGaAs superlattice.
Stacking a -GaAs layer and selectively etching the n ⁺ -GaAs layer into the InGaP / AlGaAs layer.
forming a first recess by selectively etching away the first InGaP layer of the s superlattice;
The InGaP layer of GaP / AlGaAs superlattice and Al
Forming a gate recess by alternately selectively etching a GaAs layer. 12. A step of laminating a buffer layer and a channel layer on a high-resistance InP substrate, and forming an InP layer on the channel layer.
Growing the InP / InGaAs superlattice for a desired period, and forming n ⁺ -InG on the InP / InGaAs superlattice.
forming an initial recess by selectively etching and removing the n ⁺ -InGaAs layer by selective etching with respect to the first InP layer of the InP / InGaAs superlattice by selective etching; InP / InGa
Forming a gate recess by alternately selectively etching the InP layer and the InGaAs layer of the As superlattice. 13. A step of laminating a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate, and forming AlAs / Ga on the electron supply layer.
Growing an As superlattice for a desired period;
stacking an n ⁺ -GaAs layer on the s / GaAs superlattice, and selectively removing the n ⁺ -GaAs layer by selective etching with respect to the first AlAs layer of the AlAs / GaAs superlattice. Forming a gate recess by selectively etching the AlAs layer and the GaAs layer of the AlAs / GaAs superlattice alternately to form a gate recess. . 14. A step of stacking a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate, and forming InGaP / G on the electron supply layer.
growing an aAs superlattice for a desired period;
Laminating the n ⁺ -GaAs layer GaP / GaAs super lattice, the n ⁺ -GaA by selective etching
the InGaP / GaAs superlattice as the first layer of InG
forming a first recess by selectively etching and removing the aP layer; and forming a gate recess by selectively etching the InGaP layer and the GaAs layer of the InGaP / GaAs superlattice alternately. A method for manufacturing a field effect transistor, comprising: 15. A step of laminating a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate, and forming InGaP / A on the electron supply layer.
growing a 1GaAs superlattice for a desired period; and forming n ⁺ -GaAs on the InGaP / AlGaAs superlattice.
Stacking layers and selectively etching the n ⁺
Forming a first-stage recess by selectively etching away the GaAs layer from the first InGaP layer of the InGaP / AlGaAs superlattice;
selectively etching the InGaP layer and the AlGaAs layer of the aAs superlattice alternately to form a gate recess. 16. A step of laminating a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a high-resistance InP substrate, and forming InP / InGaAs on the electron supply layer.
growing the s superlattice for a desired period;
Stacking an n ⁺ -InGaAs layer on the InGaAs superlattice, and selectively etching the n ⁺ -InG
The aAs layer is formed as the first layer I of the InP / InGaAs superlattice.
forming a first recess by selectively etching and removing the nP layer; and forming a gate recess by selectively etching the InP layer and the InGaAs layer of the InP / InGaAs superlattice alternately. A method for manufacturing a field effect transistor, comprising: