JPH01144681A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To shorten a manufacturing process while improving high-speed and high-frequency characteristics by simultaneously forming an emitter electrode and a collector electrode and arranging the emitter electrode and the collector electrode to a base electrode in a self-alignment manner. CONSTITUTION:A semiconductor layer N-GaAs layer 2, a P-GaAs layer 3 and an N-AlGaAs layer 4 are shaped successively onto the surface of a semi-insulating GaAs substrate 1 through an MBE method, and hydrogen ions (H<+>) are implanted to form an insulating region 5. An SiO2 film 6 and a resist film are shaped onto the layer 4, the film 6 is etched, and the layer 4 is etched to expose the surface of the P-GaAs layer 3. The resist film is removed, a resist film 8 is formed into the region 5, and an AuZnNi layer 9 is evaporated. The film 8 is gotten rid of, and a resist film 10 for a collector electrode is shaped. The layer 9 on the film 6 is exposed through etching, and taken off through etching by an ion milling method by Ar<+>, the layer 3 is etched, and the layer 2 in a collector electrode region is exposed. The film 6 is etched, and an AuGeNi layer 11 is evaporated. An emitter electrode 11a and a collector electrode 11b are formed simultaneously onto the surfaces of the layer 2 and the layer 4 in a self-alignment manner with a base electrode 9a at that time. Lastly, the film 10 is removed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a bipolar transistor.

[Conventional technology]

Bipolar transistors have an excellent feature of higher current driving capability than field effect transistors. Therefore, in recent years, research and development of bipolar transistors using not only Si but also compound semiconductors such as GaAs have been actively conducted.

In particular, in bipolar transistors using compound semiconductors, the emitter-paste junction can be configured into a Peter junction by using molecular beam epitaxy (hereinafter referred to as MBE) technology, and even with a high concentration of paste, the emitter injection efficiency can be improved. It has the advantage of being able to keep dogs quiet.

FIGS. 2(a) to 2(C) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a bipolar transistor.

GaAs 3 and n-A I Ga As layers 4 are sequentially formed by the MBE method, and then Au in a predetermined pattern is formed.
Emitter electrode 11a made of GeNi layer and S on it
After forming the iO□ film 6, using this as a mask, p-Ga
An AuZnNi layer-9 is formed on the As layer 3 in a self-aligned manner.

Here, an emitter electrode 11a made of an AuGeNi layer is used.
On top of this, a 5i02 film 6 and a layer 9 of Au Z n N remain.

Subsequently, a photoresist film 10a having a predetermined pattern is formed to cover the emic electrode 11a'i so that the width WB of the pace electrode becomes a predetermined value.

Next, as shown in FIG. 2(b), the photoresist film 10a is
Using ! as a mask, the AuZnNi layer 9 is etched to form the base electrode 9a, and by etching! 1ll
The surfaces of the p-GaAs layer 3 and the n-GaAs layer 20 are removed, and a photoresist film 10a is further coated with n-G as a mask.
Ohmic metal AuGeNi layer 1 on the surface of the aAs layer 20
1 is deposited from above.

Next, as shown in FIG. 2C, the photoresist film 10a is dissolved and lifted off in an organic solvent to form a collector electrode 11b.

[Problem that the invention seeks to solve]

In the conventional bipolar transistor manufacturing method described above, first, the emitter electrode 11a is formed, then the base electrode 9a is formed, and then the collector electrode 11b is formed. Therefore, in this method, it was necessary to perform the vapor deposition process of the conductor layer three times.

An object of the present invention is to shorten the manufacturing process by performing two evaporation steps in a method of manufacturing a bipolar transistor having extremely excellent high-speed and high-frequency characteristics by forming an emitter electrode and a collector electrode in a self-aligned manner with a base electrode. It is an object of the present invention to provide a method for manufacturing bipolar transistors with improved manufacturing yield and mass productivity.

[Means for solving problems]

The method for manufacturing a bipolar transistor of the present invention includes forming a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of a first conductivity type, and an insulating layer on a semi-insulating substrate. a step of sequentially depositing semiconductor layers, a step of forming a first mask with a predetermined pattern on the insulator layer, and a step of sequentially depositing the insulator layer and the third semiconductor layer using the first mask. forming an emitter layer (or collector layer) made of the third semiconductor layer;
After removing the first mask, the first mask is removed from the surface of the insulator layer.
selectively exposing the first conductor layer on the insulating layer by forming a second mask with a predetermined pattern on the conductor layer; By sequentially etching and removing the conductor layer and the second semiconductor layer, the base electrode made of the first conductor layer and the base layer made of the second semiconductor layer are made into the emitter layer (or collector layer). After etching and removing the insulating layer, a second layer is formed on the first semiconductor layer and on the emitter layer (or collector layer) using the second mask. The method includes the step of sequentially forming a collector electrode (or emitter electrode) and an emitter electrode (or collector electrode) simultaneously and in self-alignment with the base electrode by forming a conductor layer.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the non-explosion gate.

First, as shown in FIG. 1(a), semi-insulating G a A
An n-GaAs layer 2 as a first semiconductor layer, a p-GaAs layer 3 as a second semiconductor layer, and an n-AIGaAs layer 4 as a third semiconductor layer are formed on the surface of the s-substrate 1.
After sequential formation using the BE method, hydrogen ions (H+
) is implanted to form an insulating region 5.

Next, as shown in FIG. 1(b), the n-AlGaAs layer 4
After sequentially forming a 5i02 film 6 and a photoresist film 7 having a predetermined pattern thereon, this photoresist film 7 is
The Si02 film 6 was removed by reactive ion beam etching using a mask of l)n-AA! The GaAs layer 4 is etched to expose the surface of the p-GaAs layer 3.

Next, as shown in FIG. 1C, after removing the photoresist film 7, a photoresist film 8 is formed on the insulating region 5, and an AuZnNi layer ohmically connected to the p-n-GaAs layer 2 is formed from above. 9 is deposited.

Next, as shown in FIG. 1(d), after the photoresist film 8 is removed by cleaning with an organic solvent, a photoresist film 10 having a predetermined pattern for forming a collector electrode is formed. Subsequently, the surface of the photoresist film 100 is etched by reactive ion beam etching to form a 5i
After exposing the AuZnNi layer 9 on the 02 film 6, the AuZnNi layer 9 is removed by etching by ion milling using Ar+, and the pp-GaAs layer is etched using a mixture of phosphoric acid, hydrogen peroxide, and water. 3 to expose the n-()aAs layer 2 in the region where the collector electrode is to be formed.

Next, as shown in FIG. 1(e), after etching the 5i02 film 6 with buffered hydrofluoric acid, the n-G
aAs layer 2 and n-AAiGaA which becomes the emitter layer
The AuGeNi layer 11 which is ohmically connected to the s-layer 4 has a vapor layer thickness of 1°. At this time, the n-GaAs layer 2 and the n-AlGaA
An emitter electrode 11a and a collector electrode 11b are simultaneously formed on the surface of the s-layer 40 in a self-aligned manner with the base electrode 9a.

Finally, as shown in FIG. 1(f), the photoresist film 1
By removing 0! lJ AuGeN i-layer 11
A compound semiconductor bipolar transistor can be created by lift-off.

In the above embodiment, the emitter top type was described, but the embodiment is not limited to this, but the collector top type can also be implemented in the same manner, and the effect will be the same.

In addition, as semiconductors, GaAs and A/GaAs
Although we have described the ones using InP, it is limited to these.
Other compound semiconductors such as InGaAs or InGaAs may also be used. Also,
The insulating film is not limited to the 5i02 film described above, but a nitride film such as SiNx may also be used.

〔Effect of the invention〕

As explained above, the present invention shortens the manufacturing process by forming the emitter electrode and the collector electrode at the same time, and also improves high-speed and high-frequency characteristics by arranging the emitter electrode and the collector electrode in a self-aligned manner with the base electrode. This has the effect of realizing an extremely superior compound semiconductor bipolar transistor.

As a result of this, the manufacturing process is reduced in the production of bipolar transistors with a cut-off frequency of 30 GHz or higher.
This not only improves yield and device characteristics, but also enables mass production and reduces costs.

[Brief explanation of the drawing]

1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (C) are cross-sectional views of a semiconductor chip shown in the order of steps to explain a conventional method for manufacturing a bipolar transistor. 1- GaAs substrate, 2 ・= n-GaAs layer, 3
・-p-GaAs layer, 4 ・-n-AA! GaAs layer, 5... Insulating region, 6... Si02 film, 7, 8...
... Photoresist film, 9 ... AuZnNi layer, 9
a... Base electrode, 10... Photoresist film, 11
- AuGeN i layer, 11 a - emitter electrode,
11b...Collector electrode. Agent Patent Attorney Susumu Uchihara P-4-

Claims (1)

[Claims] A first semiconductor layer of a first conductivity type and a second semiconductor layer are formed on a semi-insulating substrate.
a step of sequentially depositing a second conductive type semiconductor layer, a first conductive type third semiconductor layer, and an insulating layer; forming a first mask with a predetermined pattern on the insulating layer; a step of sequentially etching and removing the insulator layer and the third semiconductor layer using the first mask to form an emitter layer (or collector layer) made of the third semiconductor layer; forming a first conductor layer on the entire surface including the surface of the insulator layer after removing the first mask; and forming a second mask with a predetermined pattern on the first conductor layer to selectively remove the exposing the first conductor layer on the insulator layer, and sequentially etching and removing the first conductor layer and the second semiconductor layer using the second mask. The base electrode consisting of the conductor layer and the base layer consisting of the second semiconductor layer are connected to the emitter layer (
or collector layer), and after etching and removing the insulator layer, use the second mask to form a layer on the first semiconductor layer and the emitter layer (or collector layer). ), forming a collector electrode (or emitter electrode) and an emitter electrode (or collector electrode) simultaneously and in self-alignment with the base electrode by forming a second conductor layer on the base electrode. A method for manufacturing a bipolar transistor.