JP3225948B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to field effect transistors and a manufacturing method thereof, and more particularly selective etching
Ensuring the depth uniformity of the second recess for arranging the gate electrode
And while the depth of the second recess in one layer or one every period superlattice
The present invention relates to a two-stage recessed structure field effect transistor capable of adjusting the height and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a method of manufacturing a two-stage recess structure field effect transistor, for example, "High Gain
and high Efficiency K-Ba
ndPower HEMT with WSi / Au
T-Shaped Gate "(T. Kunii et.
al, 1997 MTT-S Digest pp.
1187-1190).

In this manufacturing method, as shown in FIG. 9A, an n + -GaAs layer 911 is first selectively etched away from an AlGaAs layer 910 serving as an etching stopper layer using citric acid using an epitaxial substrate. Thus, a first recess is formed [see FIG. 9B].

Next, the n ^-- GaAs layer 99 is dry-etched.
A second recess in which a gate electrode is disposed by selectively etching and removing the i-AlGaAs layer 98 by etching.
Then, a film is formed [see FIG. 9C]. Finally, by forming a gate electrode 914 and an ohmic electrode 913, a two-stage recess structure field effect transistor is manufactured (see FIG. 9D).

In FIG. 9, reference numeral 91 denotes semi-insulating GaAs.
s substrate, 92, 94 and 96 are i-AlGaAs layers, 9
3, 97 is an n ⁺ -AlGaAs layer, 95 is i-inGa
An As layer 912 is a SiO2 film.

[0006]

In the above-described method for manufacturing a field-effect transistor having a two-step recess structure, the high uniformity of the second recess depth by selective etching is ensured while the second recess depth is reduced. No adjustment is possible.

Therefore, an object of the present invention is to solve the above-mentioned problems and to achieve uniformity of the depth of the second recess by selective etching while achieving high control of the superlattice layer or cycle .
It is an object of the present invention to provide a field effect transistor capable of adjusting the recess depth of No. 2 and a method of manufacturing the same.

[0008]

According to the first field effect transistor of the present invention, a buffer layer, a channel layer, an AlAs / GaAs superlattice layer, and an n ⁺ layer are formed on a semi-insulating GaAs substrate.
-Epitaxial substrate in which GaAs layers are sequentially laminated
Formed by etching and removing the n ⁺ -GaAs layer thereon
A first recess, and AlAs / Ga in the first recess.
The As superlattice layer is formed by etching away a desired amount.
Two-stage recess having a second recess formed therein
It is a structured field effect transistor.

A second field-effect transistor according to the present invention comprises a buffer layer, a channel layer, an InGaP / GaAs superlattice layer, and an n ⁺ -GaAs layer on a semi-insulating GaAs substrate.
N ⁺ -Ga on an epitaxial substrate in which
First recess formed by etching away As layer
And an InGaP / GaAs superlattice in the first recess.
A second layer formed by etching away the layer by a desired amount
Field effect having a two-stage recess structure having a recess
The result is a transistor.

A third field-effect transistor according to the present invention comprises a buffer layer, a channel layer, an InGaP / AlGaAs superlattice layer, and n ⁺ -GaAs on a semi-insulating GaAs substrate.
N ⁺ on an epitaxial substrate in which layers are sequentially formed.
-A first layer formed by etching away the GaAs layer.
Recess and InGaP / AlGaAs in the first recess.
s superlattice formed by etching a desired amount
A two-stage recess structure having a second recess
It is a field effect transistor.

According to a fourth field effect transistor of the present invention, a buffer layer, a channel layer and an I
nP / InGaAs superlattice layer and n ⁺ -InGaAs layer
N ⁺ -In on an epitaxial substrate on which
First recess formed by etching away the GaAs layer
And an InP / InGaAs super-grade in the first recess.
The second element is formed by etching the element by a desired amount.
Field effect having a two-stage recess structure having a recess
The result is a transistor.

According to a fifth field effect transistor of the present invention, a buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, an AlAs /
GaAs superlattice layer and n ⁺ -GaAs layer are sequentially formed
N ⁺ -GaAs layer on the epitaxial substrate
A first recess formed by removing the chin,
A desired amount of AlAs / GaAs superlattice is etched into the recess.
Having a second recess formed by removing the notch
A two-stage recess structure field effect transistor characterized by the following:
You.

According to a sixth field effect transistor of the present invention, a buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, and an InGaP are formed on a semi-insulating GaAs substrate.
/ GaAs superlattice layer and n ⁺ -GaAs layer sequentially laminated
An n ⁺ -GaAs layer is etched on the formed epitaxial substrate.
A first recess formed by removing the chin,
InGaP / GaAs superlattice in desired amount in recess
It has a second recess formed by etching away.
In two-step recess structure field effect Trang register, wherein bets
is there.

According to a seventh field effect transistor of the present invention, a buffer layer, a channel layer, an electron supply layer doped with an n-type impurity and an InGaP are formed on a semi-insulating GaAs substrate.
/ AlGaAs superlattice layer and n ⁺ -GaAs layer are sequentially stacked
An n ⁺ -GaAs layer is formed on the formed epitaxial substrate.
A first recess formed by etching away;
InGaP / AlGaAs superlattice in recess 1
The second recess formed by etching away the amount of
Field-effect transformer having a two-stage recess structure characterized by having
It is a Gista.

According to an eighth field effect transistor of the present invention, a buffer layer, a channel layer and an n-type
Supply layer doped with p- type impurities and InP / InG
aAs superlattice layer and n ⁺ -InGaAs layer sequentially laminated
N ⁺ -InGaAs layer on the epitaxial substrate
A first recess formed by etching away;
InP / InGaAs superlattice in desired amount in one recess
Has a second recess formed by etching only
Field-effect transistor with two-stage recess structure
It is.

According to a first method of manufacturing a field effect transistor according to the present invention, a buffer layer and a channel layer are sequentially formed on a semi-insulating GaAs substrate.
AlAs / GaAs superlattice on top of layer, AlAs layer on top
Growing a desired period, and the AlAs /
Step of laminating n ⁺ -GaAs layer on GaAs superlattice
And n ⁺ -GaAs using a photoresist as a mask.
The layer is A, which is the uppermost layer of the AlAs / GaAs superlattice layer.
By selectively etching away the As layer
Forming a first recess; and forming a first recess in the first recess.
Forming a mask having an opening in a part of the first recess and
Forming on the n ⁺ -GaAs layer, the mask
AlAs layer selectively from GaAs layer through opening
Etching and removing the GaAs layer from the AlAs layer
And selectively etching and removing the desired number of times.
Forming a second recess by repeating the process.
You.

According to a second method of manufacturing a field effect transistor according to the present invention, a buffer layer and a channel layer are sequentially formed on a semi-insulating GaAs substrate.
An InGaP / GaAs superlattice on top of the InGaP layer.
Growing a desired period of time as an upper layer;
Stack n ⁺ -GaAs layer on aP / GaAs superlattice
And n ⁺ -Ga using a photoresist as a mask.
The As layer is the uppermost layer of the InGaP / GaAs superlattice layer.
Selectively etch away certain InGaP layers
Forming a first recess, thereby forming the first recess.
A mask having an opening in a part of the recess is provided in the first recess.
Forming on the n ⁺ -GaAs layer and the
The InGaP layer from the opening of the mask to the GaAs layer
And selectively removing the GaAs layer by etching.
Selectively removing the GaP layer by etching.
Step of forming a second recess by repeating a desired number of times
And

According to a third method of manufacturing a field effect transistor according to the present invention, a buffer layer and a channel layer are sequentially formed on a semi-insulating GaAs substrate.
InGaP / AlGaAs superlattice on the InGaP layer
Growing as a top layer for a desired period;
n ⁺ -GaAs layer on nGaP / AlGaAs superlattice
Stacking, and using the photoresist as a mask, the n
^{The +} -GaAs layer as the InGaP / AlGaAs superlattice;
Selectively etches InGaP layer which is the uppermost layer
Forming a first recess by removing the recess
And a mask having an opening in a part of the first recess
Formed on the first recess and the n ⁺ -GaAs layer
The InGaP layer from the opening of the mask
Step of selectively etching away the lGaAs layer
And AlGaAs layer are selectively etched with respect to InGaP layer.
And repeating the step of removing
Forming a recess.

A fourth method of manufacturing a field effect transistor according to the present invention comprises the steps of sequentially forming a buffer layer and a channel layer on a high-resistance InP substrate ;
The I nP / InGaAs superlattice an InP layer as a top layer
Growing for a desired period by using the InP / InG
Step of laminating n ⁺ -InGaAs layer on aAs superlattice
And n ⁺ -InGa using a photoresist as a mask.
The As layer is the uppermost layer of the InP / InGaAs superlattice layer.
Selective etching removal for certain InP layer
Forming a first recess by using the first recess,
Forming a mask having an opening in a part of the first recess in the first recess;
And forming on the n ⁺ -InGaAs layer.
The InP layer from the opening of the mask to the InGaAs layer
And selectively etching and removing the InGaAs layer
Selectively etching away the InP layer.
Step of forming a second recess by repeating a desired number of times
And

According to a fifth method of manufacturing a field effect transistor according to the present invention, a buffer layer, a channel layer and an electron supply layer doped with an n-type impurity are formed on a semi-insulating GaAs substrate.
And forming AlA on the electron supply layer.
The s / GaAs superlattice is desired to have the AlAs layer as the uppermost layer.
A step of growing for the period, and the AlAs / GaAs superstrate.
Laminating an n ⁺ -GaAs layer on the substrate;
The n ⁺ -GaAs layer is formed using the AlA
For the AlAs layer, which is the uppermost layer of the s / GaAs superlattice layer,
The first recess by selectively etching away
Forming an opening, and an opening in a part of the first recess.
The first recess and the n ⁺ -Ga
Forming on an As layer, and forming A from the opening of the mask.
1As layer is selectively etched away from GaAs layer
And the step of selectively etching the GaAs layer with respect to the AlAs layer.
And the step of removing the
Forming a second recess.

According to a sixth method of manufacturing a field effect transistor according to the present invention, a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity are formed on a semi-insulating GaAs substrate.
Are sequentially formed, and InG is formed on the electron supply layer.
aP / GaAs superlattice with InGaP layer as top layer
A step of growing for a desired period, and the InGaP / GaAs
stacking an n ⁺ -GaAs layer on the s superlattice;
Wherein said n ⁺ -GaAs layer Torejisuto as a mask
InGa which is the uppermost layer of the InGaP / GaAs superlattice layer
By selectively etching away the P layer,
Forming a first recess; and forming one recess in the first recess.
A mask having an opening in the first recess and the mask
forming on the n ⁺ -GaAs layer and opening the mask;
The InGaP layer is selectively etched from the opening with respect to the GaAs layer.
Step of removing etching and bonding GaAs layer to InGaP layer
And selectively etching and removing the desired number of times.
Forming a second recess by repeating the process.
You.

According to a seventh method of manufacturing a field effect transistor of the present invention, a buffer layer, a channel layer and an electron supply layer doped with an n-type impurity are formed on a semi-insulating GaAs substrate.
Are sequentially formed, and InG is formed on the electron supply layer.
aP / AlGaAs superlattice with InGaP layer as top layer
Growing the desired period, and the InGaP / A
Step of stacking n ⁺ -GaAs layer on lGaAs superlattice
And n ⁺ -GaAs using a photoresist as a mask.
The layer is the uppermost layer of the InGaP / AlGaAs superlattice layer.
Selectively etch away certain InGaP layers
Forming a first recess, thereby forming the first recess.
A mask having an opening in a part of the recess is provided in the first recess.
Forming on the n ⁺ -GaAs layer and the
From the opening of the mask to the InGaP layer to the AlGaAs layer
Process for selective etching and AlGaAs
Layer is selectively etched away with respect to the InGaP layer
Step 2 is repeated a desired number of times to form a second recess
And a step of performing

According to an eighth method of manufacturing a field effect transistor of the present invention, a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity are sequentially formed on a high-resistance InP substrate.
Forming a next layer, and forming InP / I on the electron supply layer.
Desired period of nGaAs superlattice with InP layer as top layer
Growing step, and the InP / InGaAs superlattice
Laminating an n ⁺ -InGaAs layer thereon,
The n ⁺ -InGaAs layer is
InP layer which is the uppermost layer of the InP / InGaAs superlattice layer
Is selectively removed by etching with respect to
Forming a recess; and forming a recess in the first recess.
It said mask having an opening first Lise scan and the n ⁺
-Forming on the InGaAs layer and opening the mask.
The InP layer is selectively etched from the opening with respect to the InGaAs layer.
Step of removing etching and bonding InGaAs layer to InP layer
And selectively etching and removing the desired number of times.
Forming a second recess by repeating the process.
You.

That is, in the method of manufacturing a field-effect transistor according to the present invention , the AlAs / Ga
As, InGaP / GaAs, InGaP / AlGaAs
s, insert any of InP / InGaAs superlattices
And a selective etchant for forming a second recess for arranging the gate.
Applying the super-lattice method one layer or one period at a time
To

By selectively etching the superlattice one layer or one cycle at a time to form the second recess, high uniformity of the recess depth due to the selective etching is ensured.
Highly controlled recess depth adjustment for each superlattice layer or cycle
Becomes possible. For example, an AlAs layer is composed of four molecular layers (hereinafter, referred to as “layer”)
In the case where the GaAs layer is a 4 ML superlattice, one cycle of the superlattice is etched in one cycle of the selective etching process, so that the recess depth can be adjusted about every 2 nm.

[0026]

Next, an embodiment of the present invention will be described with reference to the drawings. FIGS. 1A to 1D are cross-sectional views showing a manufacturing process of a field-effect transistor according to a first embodiment of the present invention. In the figure, in the manufacturing process of the field effect transistor according to the first embodiment of the present invention, MB
E (Molecular Beam Epitaxy:
Molecular beam epitaxy) or MOCVD (Metalor
ganic Chemical Vapor Depos
Ition: semi-insulating G by metalorganic chemical vapor deposition)
After a buffer layer 12 and a channel layer 13 are sequentially formed on an aAs substrate 11 , AlAs is formed on the channel layer 13.
/ GaAs superlattice 14 with AlAs layer as top layer
, And finally the AlAs / GaAs superlattice
An n ⁺ -GaAs layer 15 is grown thereon [FIG.
(A)].

Next, for example, using a photoresist as a mask, a citric acid-based etchant is used to form the AlA of the first layer of the superlattice.
A first recess 16 is formed by selectively etching away the n ⁺ -GaAs layer 15 from the s layer 14a. At this time, the AlAs layer 14a on the surface to be etched is dissolved and removed at the time of washing with water after the etching, and the GaAs layer 14b is exposed (see FIG. 1B).

Subsequently, a gate pattern is formed with a desired opening width on the SiO2 film 17, for example, and a second recess forming step is performed. Using the SiO2 film 17 as a mask, the first
Similarly to the formation of the recess 16, the GaAs layer 14b exposed on the surface by the citric acid-based selective etchant is
The layer 14a is selectively removed by etching.

As described above, the AlAs layer 14a is made of Ga
In the case of the AlAs / GaAs superlattice 14, one cycle of the superlattice is etched and removed in one cycle of the selective etching step, since it is dissolved and removed at the time of washing with water after the etching of the As layer 14b. That is, in the case of the AlAs / GaAs superlattice 14, for example, the AlAs layer 14a is formed with an accuracy of one period of the superlattice.
Is 4ML and the GaAs layer 14b is a 4ML superlattice,
The depth of the second recess for arranging the gate with an accuracy of about 2 nm can be adjusted.

The above cycle is repeated until the desired recess depth is reached, and after the second recess 18 is formed (see FIG. 1C), the gate electrode 19 and the ohmic electrode 20 are formed to form a two-step recess structure. The field effect transistor is completed [see FIG. 1 (d)].

FIG. 2 is a sectional view showing the structure of a field effect transistor according to a second embodiment of the present invention. In the figure, the field effect transistor according to the second embodiment of the present invention is the same as the field effect transistor according to the first embodiment of the present invention, except that the AlAs / GaAs superlattice layer 14 is formed of InGaP.
/ GaAs superlattice 24 and the Ga of the InGaP layer 24a.
Dilute hydrochloric acid (HCl: H2 O = 1: 1) as a selective etchant for the As layer 24b, In of the GaAs layer 24b.
A sulfuric acid-based etchant is used as a selective etchant for the GaP layer 24a. The first recess is n
^{The +} -GaAs layer 25 is formed using the above-mentioned sulfuric acid-based etchant which is a selective etchant for the InGaP layer 24a.

In the case of the field effect transistor according to the second embodiment of the present invention, the depth of the second recess can be adjusted with the accuracy of one superlattice layer. 2, 21 is a semi-insulating GaAs substrate, 22 is a buffer layer, 23 is a channel layer, 25 is an n + -GaAs layer, 26 is a gate electrode, 27
Is an ohmic electrode.

FIG. 3 is a sectional view showing the structure of a field effect transistor according to a third embodiment of the present invention. In the figure, the field effect transistor according to the third embodiment of the present invention is the same as the field effect transistor according to the first embodiment of the present invention except that the AlAs / GaAs superlattice layer 14 is formed of InGaP.
/ AlGaAs superlattice 34, dilute hydrochloric acid (HCl: H2 O = 1: 1), AlGaAs layer 3 as selective etchant for InGaAsP layer 34a with respect to AlGaAs layer 34b.
A sulfuric acid-based etchant is used as a selective etchant for the 4b InGaP layer 34a. The first recess is formed using the above-mentioned sulfuric acid-based etchant which is a selective etchant for the InGaP layer 34a of the n ⁺ -GaAs layer 35.

In the case of the field effect transistor according to the third embodiment of the present invention, the depth of the second recess can be adjusted with the precision of one superlattice layer. In FIG. 3, 31 is a semi-insulating GaAs substrate, 32 is a buffer layer, 33 is a channel layer, 35 is an n ⁺ -GaAs layer, 36 is a gate electrode, 37
Is an ohmic electrode.

FIG. 4 is a sectional view showing the structure of a field effect transistor according to a fourth embodiment of the present invention. In the figure, the field effect transistor according to the fourth embodiment of the present invention is the same as the field effect transistor according to the first embodiment of the present invention except that the semi-insulating GaAs substrate is replaced with the high-resistance InP substrate 4.
1, the n ⁺ -GaAs layer 15 is replaced with the n ⁺ -InGaAs layer 4
5. The AlAs / GaAs superlattice layer 14 is made of InP / InG
aGaAs superlattice 44, and InGaAs of InP layer 44a.
Dilute hydrochloric acid, In as selective etchant for layer 44b
A first recess and a second recess are formed by using a phosphoric acid-based etchant as a selective etchant of the GaAs layer 44b with respect to the InP layer 44a.

In the case of the field effect transistor according to the fourth embodiment of the present invention, the depth of the second recess can be adjusted with the precision of one superlattice layer. In FIG. 4, reference numeral 42 denotes a buffer layer, 43 denotes a channel layer, 46 denotes a gate electrode, and 47 denotes an ohmic electrode.

FIGS. 5A to 5D are cross-sectional views showing the steps of manufacturing a field effect transistor according to the fifth embodiment of the present invention. In the figure, in the manufacturing process of the field effect transistor according to the fifth embodiment of the present invention, MBE or M
Buffer layer 52 on a semi-insulating GaAs substrate 51, a channel layer 53, n-type impurity de by OCVD method - after laminated in this order up to the electron supply layer 54, the electron supply layer
An AlAs / GaAs superlattice 55 is formed on the
A desired period is laminated as the uppermost layer, and finally n ⁺ -GaAs
An s layer 56 is grown [see FIG. 5 (a)].

Next, for example, using a photoresist as a mask, a citric acid-based etchant is used to form the AlA of the first layer of the superlattice.
By selectively etching away the n ⁺ -GaAs layer 56 with respect to s layer 55a to form a first recess 57. At this time, the AlAs layer 55a on the surface to be etched is dissolved and removed at the time of washing with water after the etching, and the GaAs is removed.
The s layer 55b is exposed [see FIG. 5B].

Subsequently, a gate pattern is formed with a desired opening width on the SiO2 film 58, for example, and a second recess forming step is performed. The said SiO2 film 58 as a mask, similar to the formation of the first <br/> recess 57, the GaAs layer 55b exposed on the surface by citric acid selected etchant AlAs
The layer 55a is selectively removed by etching.

As described above, the AlAs layer 55a is made of Ga
In the case of the AlAs / GaAs superlattice 55, one cycle of the superlattice is etched and removed in one cycle of the selective etching step, because the As layer 55b is dissolved and removed at the time of water washing after the etching of the As layer 55b. That is, in the case of the AlAs / GaAs superlattice 55, for example, the AlAs layer 55a can be formed with an accuracy of one period of the superlattice.
Is 4 ML and the GaAs layer 55 b is a 4 ML super lattice,
The depth of the second recess can be adjusted with an accuracy of about every 2 nm.

The above-described cycle is repeated until a desired recess depth is obtained, and after forming the second recess 59 (see FIG. 5C), a gate electrode 510 and an ohmic electrode 511 are formed to form a two-step recess structure. The field effect transistor is completed [see FIG. 5 (d)].

FIG. 6 is a sectional view showing the structure of a field effect transistor according to a sixth embodiment of the present invention. In the figure, the field effect transistor according to the sixth embodiment of the present invention is the same as the field effect transistor according to the fifth embodiment of the present invention, except that the AlAs / GaAs superlattice 55 is formed of InGaP /
GaAs superlattice 65 is used, and GaAs of InGaP layer 65a is formed.
As a selective etchant for the s layer 65b, dilute hydrochloric acid (H
Cl: H2 O = 1: 1), InGa of the GaAs layer 65b.
A sulfuric acid-based etchant is used as a selective etchant for the P layer 65a. The first recess is n ⁺ −
Formed by using the sulfuric acid etchant is a selective etchant for InGaP layer 65a of GaAs layer 66.

In the case of the field effect transistor according to the sixth embodiment of the present invention, the depth of the second recess can be adjusted with the accuracy of one superlattice layer. 6, reference numeral 61 denotes a semi-insulating GaAs substrate, 62 denotes a buffer layer, 63 denotes a channel layer, 64 denotes an electron supply layer doped with an n-type impurity, 66 denotes an n + -GaAs layer, and 67 denotes a gate electrode. And 68 are ohmic electrodes.

FIG. 7 is a sectional view showing the structure of a field effect transistor according to a seventh embodiment of the present invention. In the figure, the field effect transistor according to the seventh embodiment of the present invention is the same as the field effect transistor according to the fifth embodiment of the present invention except that the AlAs / GaAs superlattice 55 is formed of InGaP /
The AlGaAs superlattice 75 is used, and the A of the InGaP layer 75a is
Dilute hydrochloric acid (HCl: H2 O = 1: 1) as the selective etchant for the lGaAs layer 75b, the AlGaAs layer 75
A sulfuric acid-based etchant is used as a selective etchant for the InGaP layer 75a. The first Lise <br/> scan is formed using the sulfuric acid etchant is a selective etchant for InGaP layer 75a of n ⁺ -GaAs layer 76.

In the case of the field effect transistor according to the seventh embodiment of the present invention, the depth of the second recess can be adjusted with the accuracy of one superlattice layer. 7, reference numeral 71 denotes a semi-insulating GaAs substrate, 72 denotes a buffer layer, 73 denotes a channel layer, 74 denotes an electron supply layer doped with an n-type impurity, 76 denotes an n ⁺ -GaAs layer, and 77 denotes a gate electrode. , 78 are ohmic electrodes.

FIG. 8 is a sectional view showing a structure of a field effect transistor according to an eighth embodiment of the present invention. In the figure, the field effect transistor according to the eighth embodiment of the present invention is the same as the field effect transistor according to the fifth embodiment of the present invention except that the substrate is a high-resistance InP substrate 81, n ⁺ -GaAs.
The layer is replaced with an n ⁺ -InGaAs layer 86, and AlAs / G
The aAs superlattice 55 is an InP / InGaAs superlattice 85, and dilute hydrochloric acid (HCl: H2O = 1: 1) is used as a selective etchant for the InP layer 85a with respect to the InGaAs layer 85b.
1) A first recess and a second recess are formed by using a phosphoric acid-based etchant as a selective etchant for the InP layer 85a of the InGaAs layer 85b .
You.

In the case of the field effect transistor according to the eighth embodiment of the present invention, the depth of the second recess can be adjusted with the accuracy of one superlattice layer. 8, reference numeral 82 denotes a buffer layer, 83 denotes a channel layer, 84 denotes an electron supply layer doped with an n-type impurity, 87 denotes a gate electrode, and 88 denotes an ohmic electrode.

[0048] Thus, by forming the second recess is selectively etched superlattice one layer or one period superlattice 1 while ensuring the depth uniformity of the second recess
Highly controlled recess depth adjustment for each layer or one cycle is possible. For example, the AlAs layer is 4ML, and the GaAs layer is 4M.
In the case of the L superlattice, one cycle of the superlattice is etched in one cycle of the selective etching process, so that the second
The depth of the recess can be adjusted.

The present invention can take the following aspects in connection with the description of the claims.

(1) A buffer layer, a channel layer, an AlAs / GaAs superlattice layer, and n ⁺ are formed on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition.
-Epitaxial substrate in which GaAs layers are sequentially laminated
Formed by etching and removing the n ⁺ -GaAs layer thereon
A first recess, and AlAs / Ga in the first recess.
The As superlattice layer is formed by etching away a desired amount.
Two-stage recess having a second recess formed therein
Structural field effect transistor.

(2) A buffer layer, a channel layer, an InGaP / GaAs superlattice layer, and n are formed on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition.
⁺ -GaAs layer is sequentially formed on the epitaxial substrate
The n ⁺ -GaAs layer is formed on the plate by etching away.
A first recess, and InGaP /
The GaAs superlattice layer is etched away by a desired amount and shaped.
Two-stage recess having a second recess formed
Seth structure field effect transistor.

(3) A buffer layer, a channel layer, and an InGaP / AlGaAs superlattice layer formed on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition.
And an n ⁺ -GaAs layer sequentially laminated
The n ⁺ -GaAs layer is removed by etching on the
A first recess formed, and InG in the first recess.
Etch aP / AlGaAs super lattice by desired amount
Having a second recess formed by leaving
Two-stage recess structure field effect transistor.

(4) A buffer layer, a channel layer, an InP / InGaAs superlattice layer, and n ⁺ − are formed on a high-resistance InP substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition.
Epitaxial base formed by sequentially laminating InGaAs layers
Formed by etching away n ⁺ -InGaAs layer on plate
A first recess formed therein, and an InP /
Etch the InGaAs superlattice in desired amount
Two-stage having a second recess formed
Recessed structure field effect transistor.

(5) A buffer layer, a channel layer, an electron supply layer doped with an n-type impurity, an AlAs / GaAs superlattice layer, and n on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition. ⁺ -GaAs layer
And n ⁺ − on an epitaxial substrate sequentially laminated.
First recess formed by etching away the GaAs layer
And an AlAs / GaAs superlattice in the first recess.
Is etched and removed by a desired amount.
Field effect having two-step recess structure characterized by having recess
Transistor.

(6) A buffer layer, a channel layer, an electron supply layer doped with n-type impurities, an InGaP / GaAs superlattice layer, and n on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition. ⁺ -GaAs
N ⁺ − on an epitaxial substrate in which
First recess formed by etching away the GaAs layer
And an InGaP / GaAs superstrate in the first recess.
The second element is formed by etching the element by a desired amount.
Field effect having a two-stage recess structure having a recess
Fruit transistor.

(7) A buffer layer, a channel layer, an electron supply layer doped with n-type impurities, an InGaP / AlGaAs superlattice layer, and n on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition. ⁺ -Ga
N on an epitaxial substrate on which an As layer is sequentially laminated.
⁺ -GaAs layer formed by etching away
A recess and InGaP / AlGa in the first recess.
The As superlattice is formed by etching away a desired amount.
A two-stage recess structure having a second recess
Field effect transistor.

(8) A buffer layer, a channel layer, an electron supply layer doped with n-type impurities, an InP / InGaAs superlattice layer, and n ⁺ on a high-resistance InP substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition. -InGaAs
N ⁺ − on an epitaxial substrate in which
The first formed by etching and removing the InGaAs layer
A recess and InP / InGaAs in the first recess.
A superlattice formed by etching away a desired amount
A two-stage recess structure having two recesses
Field effect transistor.

(9) A step of sequentially forming a buffer layer and a channel layer on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and forming an AlAs / GaAs superlattice on the channel layer. To the AlAs layer
Growing a desired period as an uppermost layer;
Laminating an n ⁺ -GaAs layer on an As / GaAs superlattice
And n ⁺ -Ga using a photoresist as a mask.
The As layer is the uppermost layer of the AlAs / GaAs superlattice layer.
To selectively remove AlAs layer by etching
Forming a first recess by the first recess,
A mask having an opening in a part of the first recess and the first recess.
And forming on the n ⁺ -GaAs layer;
Select the AlAs layer from the GaAs layer
Process of etching and GaAs layer to AlAs layer
And the step of selectively removing by etching the desired number of times
Only to form a second recess by repeating
And a method for manufacturing a field effect transistor.

(10) A step of sequentially forming a buffer layer and a channel layer on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and an InGaP / GaAs superlattice on the channel layer. To InGa
Growing the P layer as the uppermost layer for a desired period;
An n ⁺ -GaAs layer is formed on the InGaP / GaAs superlattice.
Stacking, and using the photoresist as a mask, the n
⁺ -GaAs layer is the same as that of the InGaP / GaAs superlattice layer.
Selectively etches the top InGaP layer
Forming a first recess by removing;
Forming a mask having an opening in a part of the first recess by the
Forming the first recess and the n ⁺ -GaAs layer
And a GaAs layer from the opening of the mask to the InGaP layer.
And GaAs layer selectively etching away
For selectively etching away InGaP layer
Step 2 is repeated a desired number of times to form a second recess.
Field effect transistor having a process of
Manufacturing method.

(11) a step of sequentially forming a buffer layer and a channel layer on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition ;
An InGaP / AlGaAs superlattice is formed on the channel layer by In.
A step of growing a GaP layer as an uppermost layer for a desired period.
And n ⁺ -G on the InGaP / AlGaAs superlattice.
laminating an aAs layer and using a photoresist as a mask
Then, the n ⁺ -GaAs layer is changed to the InGaP / AlGa.
Select for InGaP layer which is the top layer of As superlattice layer
First recess is formed by selective etching
Having an opening in a part of the first recess
Forming a mask on the first recess and the n ⁺ -GaAs layer;
And forming InGaP through the opening of the mask.
Layer is selectively etched away with respect to the AlGaAs layer
Process and AlGaAs layer selective to InGaP layer
The desired number of etching steps
Forming a second recess by using
Method of manufacturing a field effect transistor.

(12) A step of sequentially forming a buffer layer and a channel layer on a high-resistance InP substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, and forming an InP / InGaAs superlattice on the channel layer. InP layer
Growing a desired period as an upper layer;
/ InGaAs superlattice stacked n ⁺ -InGaAs layer
And n ⁺ − using a photoresist as a mask.
The InGaAs layer is replaced with the InP / InGaAs superlattice layer.
Selectively etch away the top InP layer
Forming a first recess by performing
A mask having an opening in a part of the recess in the first recess.
Recess and forming on the n ⁺ -InGaAs layer
And an InGaAs layer from the opening of the mask to an InGaAs layer.
For selectively removing by etching and InGaAs
A process for selectively removing the s layer by etching with respect to the InP layer
Step 2 is repeated a desired number of times to form a second recess.
Field effect transistor having a process of
Manufacturing method.

(13) sequentially forming a buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on the semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition; An AlAs / GaAs superlattice is formed on the electron supply layer with the AlAs layer as the uppermost layer.
Growing for a desired period by using the AlAs / Ga
Laminating an n ⁺ -GaAs layer on the As superlattice;
Using the photoresist as a mask and the n ⁺ -GaAs layer
AlAs which is the uppermost layer of the AlAs / GaAs superlattice layer
By selectively etching away the layer,
Forming a recess in a part of the first recess
A mask having an opening is formed on the first recess and the n ⁺
Forming on a GaAs layer, and opening the mask
Etches AlAs layer selectively with respect to GaAs layer
Removal process and GaAs layer selected for AlAs layer
Repeating the desired number of times
And forming a second recess.
Of manufacturing a field effect transistor.

(14) laminating a buffer layer, a channel layer and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition; InG on the supply layer
growing the aP / GaAs superlattice for a desired period; and forming n ⁺ -GaAs on the InGaP / GaAs superlattice.
stacking an s layer, and selectively etching the n
⁺ -GaAs layer is selectively etched away from the first InGaP layer of the InGaP / GaAs superlattice to form a first-stage recess;
Forming a gate recess by alternately selectively etching the InGaP layer and the GaAs layer of the As superlattice.

(15) A buffer layer, a channel layer and an electron supply layer doped with an n-type impurity are sequentially formed on the semi-insulating GaAs substrate by one of molecular beam epitaxy and metal organic chemical vapor deposition, An InGaP / GaAs superlattice on the electron supply layer, an InGaP layer on the top layer
Growing a desired period of time,
/ Stacking n ⁺ -GaAs layer on GaAs superlattice
And n ⁺ -GaAs using a photoresist as a mask.
Layer is the top layer of the InGaP / GaAs superlattice layer
Selective etching removal for InGaP layer
Forming a first recess by the first recess,
A mask having an opening in a part of the first recess and the first recess.
And forming on the n ⁺ -GaAs layer;
InGaP layer is selected over GaAs layer from opening
Process to remove by etching and GaAs layer to InGaP
Selectively etching away the layer.
Having a step of forming a second recess by repeating the number of times
A method for manufacturing a field effect transistor, comprising:

(16) a step of sequentially forming a buffer layer, a channel layer and an electron supply layer doped with an n-type impurity on one of the high-resistance InP substrates by one of molecular beam epitaxy and metal organic chemical vapor deposition; I on the electron supply layer
The nP / InGaAs superlattice is formed with the InP layer as the uppermost layer.
A step of growing for a desired period, and the InP / InGaAs
stacking an n ⁺ -InGaAs layer on the s superlattice;
N ⁺ -InGaAs using a photoresist as a mask
Layer is the top layer of the InP / InGaAs superlattice layer
By selectively etching away the InP layer
Forming a first recess in the first recess;
A mask having an opening in a part thereof is formed in the first recess and the front.
Forming on the n ⁺ -InGaAs layer;
InP layer is selected from InGaAs layer through Ink opening
Process of etching and removing InGaAs layer by InP
Selectively etching away the layer.
Having a step of forming a second recess by repeating the number of times
A method for manufacturing a field effect transistor, comprising:

[0066]

According to the present invention as described above, according to the present invention, the
The superlattice immediately under n ⁺ -GaAs is
Is formed by selective etching one cycle at a time.
And, while ensuring uniformity of the recess depth,
Highly controlled recess depth can be adjusted for each cycle
There is an effect that.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing the steps of manufacturing a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a configuration of a field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a configuration of a field effect transistor according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a configuration of a field effect transistor according to a fourth embodiment of the present invention.

FIGS. 5A to 5D are cross-sectional views illustrating steps for manufacturing a field effect transistor according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a configuration of a field effect transistor according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a configuration of a field-effect transistor according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view showing a configuration of a field effect transistor according to an eighth embodiment of the present invention.

FIGS. 9A to 9D are cross-sectional views showing the steps of manufacturing a conventional field effect transistor.

[Explanation of symbols]

11, 21, 31, 51, 61, 71 Semi-insulating GaAs substrate 12, 22, 32, 42, 52, 62, 72, 82 Buffer layer 13, 23, 33, 43, 53, 63, 73, 83 Channel layer 14 AlAs / GaAs superlattice 14a AlAs layer 14b GaAs layer 15,25,35,56, 66,76 n ⁺ -GaAs layer 16,57 first recess 17,58 SiO ₂ film 18,59 second recess 19, 26, 36, 46, 510, 67, 77, 87 Gate electrode 20, 27, 37, 47, 511, 68, 78, 88 Ohmic electrode 24, 65 InGaP / GaAs superlattice 24a, 34a, 65a, 75a InGaP layer 24b, 65b GaAs layer 34, 75 InGaP / AlGaAs superlattice 34b, 75b AlGaAs layer 41, 81 Resistance InP substrate 44,85 InP / InGaAs superlattice 44a, 85a InP layer 44b, 85b InGaAs layer 45 n ⁺ -InGaAs layer 54,64,74,84 n-type impurity to de - electron supply layer which is flop

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-77177 (JP, A) JP-A-10-154806 (JP, A) JP-A-61-263282 (JP, A) JP-A 60-77 9174 (JP, A) JP-A-62-213279 (JP, A) JP-A-10-13547 (JP, A) JP-A-10-275813 (JP, A) JP-A-10-173167 (JP, A) JP-A-11-3896 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/812

Claims (16)

(57) [Claims] 1. A buffer layer, a channel layer, an AlAs / GaAs superlattice layer, and n ⁺ -Ga on a semi-insulating GaAs substrate.
N on an epitaxial substrate on which an As layer is sequentially laminated.
⁺ -GaAs layer formed by etching away
A recess and more than AlAs / GaAs in the first recess.
A third layer formed by etching away the lattice layer by a desired amount.
A two-stage recess structure field effect transistor having two recesses . 2. A buffer layer, a channel layer, an InGaP / GaAs superlattice layer, and n ⁺ -G on a semi-insulating GaAs substrate.
on an epitaxial substrate on which an aAs layer is sequentially laminated
A first layer formed by etching away the n ⁺ -GaAs layer
Of InGaP / GaAs in the first recess.
The s superlattice layer is formed by etching away a desired amount.
A two-stage recessed field effect transistor having a second recess . 3. A buffer layer, a channel layer, an InGaP / AlGaAs superlattice layer and an n ⁺ layer on a semi-insulating GaAs substrate.
-Epitaxial substrate in which GaAs layers are sequentially laminated
The n + -GaAs layer is formed by etching away
A first recess, and InGaP /
Etch and remove AlGaAs superlattice by desired amount
Two-stage having a second recess formed
Recessed structure field effect transistor. 4. A buffer layer, a channel layer, an InP / InGaAs superlattice layer, and n ⁺ -InG on a high-resistance InP substrate.
on an epitaxial substrate on which an aAs layer is sequentially laminated
formed by etching away the n ⁺ -InGaAs layer
A first recess and InP / InG in the first recess;
aAs superlattice formed by etching a desired amount
Two-stage recess having a second recess formed therein
Structural field effect transistor. 5. A buffer layer, a channel layer and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate.
N ⁺ -GaA the AlAs / GaAs superlattice layer and n ⁺ -GaAs layer and sequentially laminated epitaxial substrate
a first recess formed by etching away the s layer;
Desiring AlAs / GaAs superlattice in the first recess
The second recess formed by etching away the amount of
A two-stage recessed structure field effect transistor comprising: 6. A buffer layer, a channel layer and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate.
The InGaP / GaAs superlattice layer and the n ⁺ -GaAs layer
N ⁺ -GaAs is formed on an epitaxial substrate
a first recess formed by etching away the s layer;
An InGaP / GaAs superlattice is located in the first recess.
A second recess formed by etching and removing a desired amount
1. A two-stage recessed structure field effect transistor comprising: 7. A buffer layer, a channel layer and an electron supply layer doped with an n-type impurity on a semi-insulating GaAs substrate.
InGaP / AlGaAs superlattice layer and n ⁺ -GaAs layer
And n ⁺ -G on an epitaxial substrate in which
First recess formed by etching away aAs layer
And more than InGaP / AlGaAs in the first recess.
A second formed by etching away the grating by a desired amount
2. A two-stage recessed structure field effect transistor having a recess . 8. A buffer layer, a channel layer, an electron supply layer doped with an n-type impurity and an In
An n ⁺ -InG layer is formed on an epitaxial substrate on which a P / InGaAs superlattice layer and an n ⁺ -InGaAs layer are sequentially formed.
First recess formed by etching away aAs layer
And an InP / InGaAs superlattice in the first recess.
Is etched and removed by a desired amount.
A field-effect transistor having a two-stage recess structure, comprising a recess . 9. semi-insulating the steps of sequentially stacked a buffer layer and the channel layer on a GaAs substrate, the uppermost layer of the AlAs layer AlAs / GaAs superlattice on the channel layer
And growing desired period as the AlAs /
Laminating an n ⁺ -GaAs layer on a GaAs superlattice, and using the photoresist as a mask for the n ⁺ -GaAs layer;
The layer is A, which is the uppermost layer of the AlAs / GaAs superlattice layer.
By selectively etching away the As layer
Forming a first recess; and forming a first recess in the first recess.
Forming a mask having an opening in a part of the first recess and
Forming on the n ⁺ -GaAs layer, the mask
AlAs layer selectively from GaAs layer through opening
Etching and removing the GaAs layer from the AlAs layer
And selectively etching and removing the desired number of times.
Forming a second recess repeatedly . 10. A process for semi-insulating sequentially stacked a buffer layer and the channel layer on a GaAs substrate, an InGaP layer of InGaP / GaAs superlattice with the channel <br/> Le layer
And growing desired period as the uppermost layer, the In
Laminating an n ⁺ -GaAs layer on a GaP / GaAs superlattice; and n + -G
The aAs layer is the uppermost layer of the InGaP / GaAs superlattice layer.
Is selectively removed by etching with respect to the InGaP layer
Forming a first recess by forming
A mask having an opening in a part of the recess in the first recess.
Forming a recess on the n ⁺ -GaAs layer;
The InGaP layer is connected to the GaAs layer from the opening of the mask.
And selectively removing the GaAs layer by etching.
a step of selectively removing the nGaP layer by etching;
Is repeated a desired number of times to form a second recess.
A method for manufacturing a field effect transistor, comprising: 11. A buffer layer on a semi-insulating GaAs substrate and the channel layer and the step of sequentially laminating forming the InGaP / AlGaAs superlattice to the channel <br/> Le layer InGaP
Wherein the step of desired cycles grow a layer as the uppermost layer, laminating the n ⁺ -GaAs layer to the InGaP / AlGaAs super lattice, the photoresist as a mask
The n ⁺ -GaAs layer is made of InGaP / AlGaAs
Selectively etch the InGaP layer, which is the uppermost layer of the
Step of Forming First Recess by Removing Ching
And a mask having an opening in a part of the first recess
Formed on the first recess and the n ⁺ -GaAs layer
The InGaP layer from the opening of the mask
Step of selectively etching away the lGaAs layer
And AlGaAs layer are selectively etched with respect to InGaP layer.
And repeating the step of removing
Forming a recess as described above. 12. A step of sequentially forming a buffer layer and a channel layer on a high-resistance InP substrate, and forming an InP / InGaAs superlattice on the channel layer with an InP layer as an uppermost layer.
And growing desired cycles and the InP / an In
Laminating the n ⁺ -InGaAs layer on a GaAs superlattice, the n ⁺ -ing the photoresist as a mask
The aAs layer is the uppermost layer of the InP / InGaAs superlattice layer.
By etching selectively to the InP layer
Forming a first recess by means of
A mask having an opening in a part of the recess
Forming on the n ⁺ -InGaAs layer and
The InP layer is connected to the InGaAs layer from the opening of the mask.
For selectively removing by etching and InGaAs layer
Etching selectively to the InP layer; and
Is repeated a desired number of times to form a second recess.
A method for manufacturing a field effect transistor, comprising: 13. A process for sequentially laminating forming the electron supply layer doped buffer layer and the channel layer and the n-type impurity on a semi-insulating GaAs substrate, Al on the electron supply layer
A step of desired cycles grow the as / GaAs superlattice with AlAs layer as the uppermost layer, laminating the n ⁺ -GaAs layer to the AlAs / GaAs super lattice, Fotore
The n ⁺ -GaAs layer is converted to the Al
For the AlAs layer, which is the uppermost layer of the As / GaAs superlattice layer,
And selectively etching away the first recess.
Forming a recess, and opening an opening in a part of the first recess.
A mask having a portion with the first recess and the n ⁺ -G
forming on the aAs layer, and from the opening of the mask
Selectively remove AlAs layer from GaAs layer by etching
Removing the GaAs layer selectively with respect to the AlAs layer
Repeat the process of removing by etching the desired number of times
Forming a second recess . 14. A process for sequentially laminating forming the electron supply layer doped buffer layer and the channel layer and the n-type impurity on a semi-insulating GaAs substrate, In the electron supply layer
The GaP / GaAs superlattice a step of <br/> grow the desired period of InGaP layer as the uppermost layer, the InGaP / Ga
Laminating the n ⁺ -GaAs layer on As superlattice off
Using the photoresist as a mask and the n ⁺ -GaAs layer
InG which is the uppermost layer of the InGaP / GaAs superlattice layer
By selectively etching away the aP layer
Forming a first recess; and forming a first recess in the first recess.
A mask having an opening in a part thereof is formed in the first recess and the front.
Forming on the n ⁺ -GaAs layer;
Selective InGaP layer from GaAs layer through opening
Etching removal process and GaAs layer to InGaP layer
And the step of selectively removing by etching the desired number of times
Forming a second recess only by repeating the method. 15. A process for sequentially laminating forming the electron supply layer doped buffer layer and the channel layer and the n-type impurity on a semi-insulating GaAs substrate, In the electron supply layer
GaP / AlGaAs superlattice with InGaP layer as top layer
And growing desired cycles and the InGaP /
Laminating the n ⁺ -GaAs layer on AlGaAs superlattice, said n ⁺ -GaA the photoresist as a mask
The s layer is the uppermost layer of the InGaP / AlGaAs superlattice layer.
Is selectively removed by etching with respect to the InGaP layer
Forming a first recess by forming
A mask having an opening in a part of the recess in the first recess.
Forming a recess on the n ⁺ -GaAs layer;
Converting the InGaP layer to an AlGaAs layer from the opening of the mask
For selectively removing by etching and AlGaAs
The s layer is selectively etched away from the InGaP layer.
And forming the second recess by repeating the process a desired number of times.
A method of manufacturing a field-effect transistor. 16. A buffer layer, a channel layer, and an electron supply layer doped with an n-type impurity on a high-resistance InP substrate.
A step of sequentially stacked, InP on the electron supply layer /
A step of InGaAs grown superlattice desired period an InP layer as a top layer and a step of laminating the n ⁺ -InGaAs layer to the InP / InGaAs super lattice, Photo
Using the resist as a mask, the n ⁺ -InGaAs layer is
InP which is the uppermost layer of the InP / InGaAs superlattice layer
By selectively etching away the layer,
Forming a recess, and a part of the first recess
A mask having an opening in the first recess and the n
Forming on the ⁺ -InGaAs layer, the mask
An InP layer is selectively formed from an opening with respect to an InGaAs layer.
Etching removal process and InGaAs layer to InP layer
And the step of selectively removing by etching the desired number of times
Forming a second recess only by repeating the method.