JP2000304783A - Frequency sweeping signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cumulative value of the error of a sweep chopping frequency Δf. SOLUTION: When a center frequency FC, a span ΔF, and a time coefficient TS are set, the sweep starting frequency FS for the N-bit integer section and M-bit decimal section of (FC-ΔF/2).2N/FCK are stored in a register 32 with respect to a reference clock frequency FCK and frequency setting data bit number N of a DDS(direct digital synthesizer) and the N-bit integer section and the sweep increment frequency Δf of the M-bit decimal section of (ΔF/(p.FCK).2N are set in a register 33, and an (N+M) bit fixed-point cumulative adder 34 cumulatively adds the frequency Δf by using the sweep starting frequency FS as an initial value and sets the N-bit integer section of the cumulatively added value of the (N+M) bits in the frequency setting section of the DDS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to, for example, a frequency sweeping local signal generator and a signal generator of a spectrum analyzer, and is applied to a direct digital synthesizer (DD).
The present invention relates to a frequency sweep signal generator that generates a frequency sweep signal using S).

[0002]

2. Description of the Related Art FIG. 2 shows a conventional frequency sweep signal generator of this kind. Direct digital synthesizer (D
In DS 11, the value set in the frequency control register 14 is added by the phase accumulator 15, and the value is converted into digital sine wave data by the sine look-up table 16. The digital sine wave data is converted into an analog signal by a DA converter 17 and further passed through a low-pass filter 18 to output an analog sine wave signal.

For example, in a frequency sweep in a spectrum analyzer, parameters such as a center frequency F _C , a frequency sweep span ΔF, and a sweep time T _S are set in a sweep setting section 21.
And the sweep setting unit 21 sets [(F _C −ΔF / 2) 2
^N / F _CK ] to obtain sweep start frequency data F _S. Operation reference clock generator 12 of the F _CK is DDS11
And N is the number of bits of frequency data set in the frequency control register 14. [X] represents an integer part of x. Further, a sweep resolution p for the set sweep time T _S is determined with reference to a correspondence table (not shown) between the sweep time and the sweep resolution (the number of measurement points) [(ΔF / (p · F _CK )) · 2 ^N ] to obtain the sweep frequency data Δf.

The N bits (integer part) of the sweep start frequency data F _S are stored in an F _S register 22, and the N bits (integer part) of the sweep frequency data Δf are stored in a Δf register 23.
Is stored in Using the sweep start frequency data F _S as an initial value, the sweep frequency data Δf is an N-bit accumulator 2
The cumulative addition is performed at 4. That is, F _S is set in the addition register 25 in the initial state, and then the content of the addition register 25 and Δf are added by the adder 26 and stored in the addition register 25 for each T _S / p. The cumulative addition result f _A of the addition register 25 is set in the frequency control register 14 as frequency data of the generated signal. In this way, as an output of the DDS 11, from the frequency F _S ,
A frequency sweep signal whose frequency increases by Δf every T _S / p is obtained.

[0005]

As described above, in the related art, when a set frequency is converted into DDS set frequency data, a decimal part is truncated. For this reason, when the number of points p is increased particularly in a narrow frequency sweep span ΔF, the accumulated value of the errors in the decimal part greatly affects the span accuracy. This accumulated error is ｛(ΔF / (p ·
F _CK )) · 2 ^N -[(ΔF / (p · F _CK )) · 2 ^N ]｝
-It becomes p.

[0006]

According to the present invention, not only the N-bit integer part but also the M-bit decimal part are set for the sweep start frequency data F _S and the sweep step frequency data Δf, respectively. An N + M-bit cumulative adder is used, and only the N-bit integer part in the N + M-bit cumulative addition value f _A is set in the DDS as generated frequency data.

[0007]

FIG. 1 shows an embodiment of the present invention.
Parts corresponding to those in FIG. 2 are given the same numbers. Sweep settings
A sweep parameter such as a center frequency F_C,frequency
Several sweep spans ΔF, sweep time T_SIs set. Sweep
In the fixed part 31, [(F_C-ΔF / 2) 2 ^N/ F_CK] Operation
And the sweep start frequency data F_SThe N-bit integer part of
As well as (F_C-ΔF / 2) 2^N/ F_CKFraction of
Find M bits (below the decimal point). Similarly, the sweep time T
_STo determine the sweep resolution p, and [(ΔF / (p · F_CK))
・ 2^N] To calculate the N bit of the sweep frequency data Δf.
And the integer part of (ΔF / (p · F_CK)) ・
2^NM bits of the decimal part (below the decimal point) are obtained. this
From the N-bit integer part and the M-bit decimal part
Data F_SAnd the sweep frequency data Δf are N +
M-bit F_SStored in register 32 and Δf register 33
Is done.

[0008] These F_SAnd Δf are N-bit integer part, decimal
In the M-bit fixed-point accumulator 34, F_SThe initial
The value is T_SΔf is cumulatively added for each / p. Toes
R F _SIs stored in the N + M-bit addition register 35 in the initial state.
After the setting, the contents of the addition register 35 and Δf are N +
The sum is added by the M-bit adder 36 to the addition register 35.
T to be stored_SIt is repeated every / p. This addition
Cumulative addition value f of the arithmetic register 35_AWhere the N-bit integer part is
The generated frequency data is stored in the frequency setting unit 14 of the DDS 11.
Is set.

According to this configuration, if the number of bits M of the decimal part is sufficiently large, the sweeping frequency Δf of N + M bits is obtained.
Can be ignored, the cumulative error resulting from the cumulative addition of Δf can be ignored, and the error of the N-bit frequency setting data f _A set in the DDS can be ignored due to the sweep. The larger the number M of bits of the decimal part is, the smaller the effect of the accumulated error can be. The number of M's may be determined so as to satisfy the required accuracy. However, in general, the bit width is limited and the value of M is also determined by the control on the constituting hardware.

In the above description, the cumulative addition of Δf is configured as hardware of a cumulative adder.
U may do it. The sweep setting parameters include a center frequency F _C , a sweep frequency span ΔF, and a sweep time T _S.
Not limited to this, for example, a sweep start frequency F _S , a sweep stop frequency F _E , and a sweep time T _S may be set. When the frequency sweep is repeated, the sweep start frequency F _S may be set in the addition register 35 when the cumulative addition value f _A reaches the sweep stop frequency. In the above description, the frequency is swept by increasing the frequency. However, if the sign of Δf is made negative, the frequency can be swept by decreasing.

[0011]

As described above, according to the present invention, the sweep addition frequency .DELTA.f is also cumulatively added to the fractional part thereof, and only the N bits of the integer part are used as the DDS frequency setting data. It can be significantly smaller than the technology, and the effect of frequency errors can be reduced when narrow spans are swept at many points.

[Brief description of the drawings]

FIG. 1 is a diagram showing a functional configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional frequency sweep signal generator.

Claims (1)

[Claims] 1. A set swept increments frequency data according to the parameter Δf = ΔF / (p × F C) × 2 N (Δ
F: Sweep frequency span, p: Sweep resolution, F _C : Direct digital synthesizer reference clock signal frequency,
N: calculates the number of bits) of the frequency control register direct digital synthesizer, a sweep increments frequency data Δf the sweep start frequency data F _S as an initial value by cumulatively adding the cumulative adder, the direct and the accumulated value f _A In a frequency sweep signal generator for setting an N-bit generated signal frequency data in a digital synthesizer, a sweep start frequency data F _S and a sweep step frequency data Δf are respectively set as an N-bit integer part and an M-bit decimal part, _A frequency sweep signal generator, wherein the number of bits of the accumulator is N + M bits, and an integer part of upper N bits in the accumulated value f _A is set as generated signal frequency data in the direct digital synthesizer.