JP2001136064A - Frequency signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency signal generator employing a PLL circuit that can optionally set a frequency of an output frequency signal. SOLUTION: An arithmetic circuit 12 that gives a frequency division ratio G to a frequency divider 6 of a PLL circuit, consists of an upper limit memory 17 that stores the denominator produced in the case that a fraction J of a multiplier value [N+J] is indicated by a rational number (K/L) as an upper limit value, a 1st adder 14 that sums the numerator and a feedback value, a 1st delay circuit 15 that delays the outputted sum H to give the delayed sum to the 1st adder, a 2nd delay circuit 16 that delays the sum H of the 1st adder, a comparator circuit 18 that compares the sum delayed by the 2nd delay circuit with the upper limit L of the upper limit value memory to provide an output of an output value E that is 0 when the sum is less than the upper limit value 1st or that is 1 when the sum reaches the upper limit so as to clear the 1st delay circuit, and a 2nd adder 19 that sums an integral value N of the multiplier value [N+J] and the output E of the comparator circuit to apply the sum [N+E] to the frequency divider 6 as the frequency division ratio G.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a frequency signal generator for generating frequency signals having various frequencies, and more particularly to a frequency signal generator using a fractional method for a frequency divider.

[0002]

2. Description of the Related Art A frequency signal generator for outputting a frequency signal having high frequency accuracy is included in a measuring device for measuring the operating characteristics of a repeater and various transceivers incorporated in a mobile communication system or a data communication system. It is built in. It is required not only that the frequency value of the frequency signal output from the frequency signal generator can be set with high accuracy, but also that the frequency can be changed with high accuracy.

In general, a PLL circuit is used to ensure high frequency stability in an output frequency signal. A frequency signal generator using this PLL circuit is configured as shown in FIG.

For example, a reference signal generator 1 composed of a crystal oscillator or the like generates a reference frequency signal a having a reference frequency f _R.
Is output. The reference frequency signal a output from the reference signal generator 1 is input to the phase detector 2. The phase detector 2 detects a phase difference between the input reference frequency signal a and the frequency-divided signal b output from the frequency divider 6, and outputs a phase difference signal c having a voltage proportional to the phase difference. .

[0005] The phase difference signal c output from the phase detector 2
Is a loop filter 3, after high frequency components are removed,
New phase difference signal c ₁ as a VCO (voltage-controlled oscillator)
4 is input.

The VCO 4 outputs a frequency signal d having an output frequency f _O proportional to the signal value of the phase difference signal c ₁ to an output terminal 5.
Output to The output frequency signal d output from the VCO 4 is input to the frequency divider 6. The frequency divider 6 divides the frequency of the output frequency signal d by a frequency division ratio N (N: an integer) input from the outside, and applies the frequency divided signal b to the phase detector 2.

Therefore, the phase detector 2, the loop filter 3, the VCO 4, and the frequency divider 6 constitute a PLL circuit.

In the frequency signal generator incorporating such a PLL circuit, the output frequency f _O of the output frequency signal d output from the output terminal 5 is N times the reference frequency f _R.

Since f _O = N · f _R N is an integer, the output frequency f _O can take only an integer multiple of the reference frequency f _R. If the reference frequency f _R is set low, problems such as a decrease in loop response characteristics of the PLL circuit occur.

Therefore, a frequency signal generator employing a fractional method for obtaining an output frequency f _O that is a rational number multiple of the reference frequency f _R has been proposed (US Pat. No. 3,928,928).
813).

That is, as shown in FIGS. 3 and 4, the frequency division ratio N set in the frequency divider 6 is set to [N + 1] every fixed period T _S.
Switch to. For example, once every 10 times, inserting a [N + 1], the output frequency f _O is the reference frequency f _R [N + 0.
1] times.

Therefore, by appropriately setting N (positive integer value) and J (decimal value) constituting the multiple value [N + J], an output frequency f _{O which} is an arbitrary multiple of the reference frequency f _R can be obtained. .

F _O = [N + J] · f _R N; positive integer 0 <J <1 Note that N is an integer value, J is a decimal value (fractional value) called a fractional value, and a rational number It is.

FIG. 5 shows a frequency signal generator capable of obtaining an output frequency signal d having an output frequency f _O which is [N + J] times the reference frequency f _R of the reference frequency signal a.
It is configured as shown in FIG.

That is, the frequency division ratio G applied to the frequency divider 6 in the frequency signal generator shown in FIG.
And an arithmetic circuit 7 for performing a switching operation between.
Then, a clock signal CLK having a clock of a constant cycle T _S (constant frequency f _S ) is input from the clock terminal 8 to the arithmetic circuit 7.

In order to obtain an output frequency f _O which is [N + J] times the reference frequency f _R, a decimal value J constituting the multiple value [N + J] is represented by a fraction having the following (2 ⁿ ) as a denominator.

J = M / (2 ⁿ ) M, n; integer The denominator (2 ⁿ ) indicates that the arithmetic circuit 7 is constituted by a binary arithmetic circuit. 1
In the case of a zero-ary arithmetic circuit, the denominator is (10
ⁿ ). The numerator value M of this fraction and the multiple value [N +
J] is calculated in advance and set in the arithmetic circuit 7.

The arithmetic circuit 7 is configured as shown in FIG. As shown, the arithmetic circuit 7 includes a first adder 9, a delay circuit 10, and a second adder 11. The delay circuit 10 performs an operation specified in synchronization with a clock of a constant period T _S of the clock signal CLK.

The numerator M (integer) when the decimal value J of the multiple value [N + J] is expressed as a fraction is applied to one input terminal 9 a of the first adder 9. The feedback value output from the delay circuit 10 is input to the other input terminal 9b of the first adder 9. The first adder 9 adds the numerator value M of the decimal value J and the feedback value and sends the added value to the delay circuit 10. The delay circuit 10 outputs the added value to the clock signal CL.
K is only one period T _S delayed of applying as a feedback value to the first other input terminal 9b of the adder 9.

Therefore, the first adder 9 calculates the numerator M when the decimal value J of the multiple value [N + J] is expressed as a fraction.
(Integer) is cumulatively added.

When the added value of the first adder 9 exceeds the upper limit value (upper digit value) of the first adder 9, a one-value carry signal e from the OVF (overflow) terminal is output to the second adder 9. The signal is output to one input terminal 11b of the adder 11.

The upper limit value (upper limit digit value) of the first adder 9 indicates the maximum value of the value that can be calculated by the first adder 9 and is formed by a binary arithmetic circuit. When n = 3, the maximum value is [111] (= 7). Therefore, when M = 1, one out of eight clocks of the clock signal CLK
At this time, a one-value carry signal e is output. When M = 2, the one-value carry signal e is output once every four clocks of the clock signal CLK.

An integer N of a multiple value [N + J] is input to the other input terminal 11a of the second adder 11. The second adder 11 adds the values applied to the respective input terminals 11a and 11b and applies the result to the frequency divider 6 as a frequency dividing ratio G.

The integer value N of the multiple value [N + J] is
The one-value carry signal e is applied to the input terminal 11b at the timing when the sum of the first adder 9 overflows. Therefore, the clock signal CL
Arithmetic circuit 7 in synchronization with a clock having a constant period T _S in K
Is sequentially applied to the frequency divider 6 from N or [N +
1].

In the frequency signal generator configured as described above, [N + 1] appears in the frequency division ratio G sequentially applied from the arithmetic circuit 7 to the frequency divider 6 in synchronization with the clock of the clock signal CLK. Rate is a multiple value [N
+ J] (= [N + M / (2 ⁿ )])
(= M / (2 ⁿ )).

Therefore, the average frequency division ratio G applied to the frequency divider 6 is a multiple value [N + J] set in the arithmetic circuit 7, so that the output frequency of the output frequency signal d output from the output terminal 5 It is possible to make f _O [N + J] times the reference frequency f _R.

[0027]

However, FIG.
The conventional frequency signal generator shown in FIG. 6 also has the following problems to be solved.

That is, the output timing of the one-value carry signal e sent from the first adder 9 incorporated in the arithmetic circuit to the second adder 11 is determined by the addition value of the first adder 9. , Only when the value exceeds the upper limit determined by the hardware configuration of the first adder 9. For example, in the case of a binary (2 ⁿ ) 3-bit (n = 3) adder, the upper limit is [11
1] (= 7).

Therefore, according to the hardware configuration of the first adder 9 incorporated, the multiple value [N + J] (= [N
+ M / (2 ⁿ )]), the decimal value J (= M / (2 ⁿ ))
There is a large restriction on the value that can be obtained.

Further, only at the timing when the sum of the first adder 9 overflows, the carry signal e of one value is obtained.
Is not output, the decimal value J in the multiple value [N + J] is obtained when the arithmetic circuit 7 is configured by a binary arithmetic circuit.
Can only take the value of (M / (2 ⁿ )). For example, J =
M / (2 ⁿ + p) (p is an integer) cannot be taken. When the arithmetic circuit 7 is a decimal arithmetic circuit, the decimal value J in the multiple value [N + J] is (M / (10 ⁿ )).
Can only take the value of

As described above, even if the number of types of the first adders 9 incorporated in the arithmetic circuit 7 is increased, the decimal value J in the multiple value [N + J] cannot be set to an arbitrary value. . As a result, not be set the output frequency f _O of the output frequency signal d to any multiple of the reference frequency fS of the reference frequency signal a.

The present invention has been made in view of such circumstances, and by comparing an addition value output from an adder with an upper limit value determined by a multiple value, only one simple hardware circuit member is used. It is an object of the present invention to provide a frequency signal generator capable of arbitrarily setting an output frequency of an output frequency signal.

[0033]

According to the present invention, there is provided a reference signal generator for generating a reference frequency signal having a reference frequency, and the position of the reference frequency signal output from the reference signal generator and the input divided signal. A phase detector that detects a phase difference and outputs a phase difference signal corresponding to the phase difference, a voltage controlled oscillator that outputs a frequency signal having a frequency corresponding to the phase difference signal output from the phase detector, and a voltage controlled oscillator A frequency divider that divides the frequency of the output frequency signal output from the phase divider by the applied integer frequency division ratio and sends it as a divided signal to the phase detector, and a multiplication of the input integer value and decimal value From the numbers,
The present invention is applied to a frequency signal generator including an arithmetic circuit for sequentially calculating each frequency division ratio so that the average value of the frequency division ratio sequentially applied to the frequency divider becomes a multiple value.

In order to solve the above problem, in the frequency signal generator of the present invention, the upper limit for storing the denominator value when the input decimal value is represented by a fraction as the upper limit value in the arithmetic circuit. A value memory, a first adder that adds and outputs a numerator value when the input decimal value is represented by a fraction and the input feedback value,
And a second delay circuit for delaying the sum output from the first adder and delaying the sum output from the first adder. And the added value output from the second delay circuit is compared with the upper limit value stored in the upper limit value memory, and when the added value is smaller than the upper limit value, an output value of 0 is output. When the value reaches the upper limit value, the comparator outputs an output value of one value to clear the first delay circuit, and adds the input integer value and the output value of the comparison circuit to divide the added value. A second adder for applying the ratio to the frequency divider.

In the frequency signal generator configured as described above, when the output frequency of the output frequency signal is set to [N + J] times the reference frequency of the reference frequency signal, the multiple [N + J] is converted to an arbitrary rational number. Explain why you can set it.

N constituting the multiple value [N + J] is a positive integer value, and J is a positive decimal value. The fractional value J, which is all rational numbers that are not irrational numbers, is expressed by K
It can be represented by the following fraction with (integer) being the molecular value.

J = K / L The first adder accumulatively adds the input numerator value K, similarly to the first adder of the conventional arithmetic circuit shown in FIG. When the denominator value L is reached, the output value from the comparison circuit becomes one value. Therefore, at this timing, the frequency division ratio G applied from the second adder to the frequency divider changes from N to [N + 1].

Therefore, the average frequency division ratio G applied to the frequency divider becomes a multiple value [N + J] set in the arithmetic circuit, so that the output frequency of the output frequency signal output from this frequency signal generator is It can be [N + J] times the reference frequency.

In this case, when the first adder reaches the denominator value L of the decimal value J before the addition value overflows,
The output value from the comparison circuit becomes one, and the added value is cleared. Therefore, various denominator values L can be handled by a single first adder by using the first adder as an adder having a bit configuration with a margin.

As a result, the denominator value L of the decimal value J of the multiple value [N + J] can be set to an arbitrary integer value, so that the output frequency of the output frequency signal can be obtained by one hardware component (first adder). Can be set to any rational number times the reference frequency of the reference frequency signal.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration of a frequency signal generator according to the embodiment. The same parts as those of the conventional frequency signal generator shown in FIG. 5 are denoted by the same reference numerals, and detailed description of the overlapping parts will be omitted.

[0042] In the frequency signal generator of the embodiment, to the divider 6, N or at a fixed period T _S [N +
An arithmetic circuit 12 for applying the frequency division ratio G of [1] is provided. The arithmetic circuit 12 has a different circuit configuration from the arithmetic circuit 7 of the conventional frequency signal generator shown in FIG. For this arithmetic circuit 12, a constant period T
A clock signal CLK having an _S clock is input.

The frequency dividing condition setting unit 13 sets a multiple value [N +] when the output frequency f _O of the output frequency signal d is set to a rational number times the reference frequency f _R of the reference frequency signal a.
J] is input, the input multiple value [N + J]
Is developed into the following fraction.

J = K / L where M and L are integer values.

The frequency dividing condition setting unit 13 converts the integral value N of the multiple value [N + J] and the decimal value J of the multiple value [N + J] into a fraction (K /
The denominator value L and the numerator value K in the case indicated by L) are sent to the arithmetic circuit 12.

The arithmetic circuit 12 is configured as shown in FIG. As shown, the arithmetic circuit 12 includes a first adder 14, a first delay circuit 15, a second delay circuit 1616, an upper limit memory 17, a comparison circuit 18, and a second adder 19. Have been. Then, the first and second delay circuits 15 and 16 perform a delay operation for one cycle T _{S of the} clock with respect to the input value, respectively, in synchronization with the clock of the fixed cycle T _S in the clock signal CLK.

The denominator value L (integer) when the decimal value J of the multiple value [N + J] is represented by a fraction is written into the upper limit memory 17. The numerator value K (integer) when the decimal value J of the multiple value [N + J] is expressed as a fraction is applied to one input terminal 14 a of the first adder 14. This first adder 14
The feedback value output from the first delay circuit 15 is input to the other input terminal 14b.

The first adder 14 calculates the numerator value K of the decimal value J.
And by adding the feedback value, it sends out the added value H to one input of a second 1 in the clock signal CLK by the delay circuit of the period T _S content only compared with a delay circuit 18, the addition value H The signal is sent to the first delay circuit 15. The first delay circuit 15 is applied to the other input terminal 14b of the first adder 14 and the added value H that is input as the feedback value with a delay by one period T _S content in the clock signal CLK.

Therefore, the first adder 14 synchronizes the numerator value K (integer) when the decimal value J of the multiple value [N + J] is expressed as a fraction with the clock of the fixed period T _S in the clock signal CLK. , And output as an added value H.

The upper limit L stored in the upper limit memory 17 is constantly applied to the other input terminal of the comparison circuit 18. The comparison circuit 18 is connected to the second delay circuit 16
Then, the addition value H of the first adder 14 delayed by one cycle T _S in the clock signal CLK is compared with the upper limit value L of the upper limit value memory 17, and the addition value H has not reached the upper limit value L. In this case, an output value E (= 0) of 0 value is output. When the added value H reaches the upper limit L, the comparison circuit 18 outputs a one-valued output value.
E (= 1) is output.

The output value E output from the comparison circuit 18 is input to the clear terminal (CLR) of the first delay circuit 15 and is also applied to one input terminal 19b of the second adder 19.

When the sum H of the first adder 14 has not reached the upper limit L, the output value E of the comparator 18 remains at 0, so that the feedback value of the first delay circuit 15 is It will not be cleared.

On the other hand, when the sum H of the first adder 14 reaches the upper limit L, the output value E of the comparison circuit 18 changes to 1 and the feedback value of the first delay circuit 15 is cleared. . That is, at this time, since the upper limit L is equal to the added value H as the feedback value, the feedback value input from the first delay circuit 15 to the first adder 14 is cleared to zero. You.

The feedback value input to the first adder 14 is 0
Is cleared, the addition value H output from the first adder 14 also returns to the initial value K, and the cumulative addition to the numerator value K (integer) is started again.

The other input terminal 19a of the second adder 19 receives an integer value N of a multiple value [N + J]. The second adder 11 adds the values applied to the input terminals 19a and 19b and applies the result to the frequency divider 6 as a frequency division ratio G.
Therefore, the dividing ratio G is such that the output value E of the comparing circuit 18 is 0
If the value is N, the value is N. If the output value E of the comparison circuit 18 is 1, the value is [N + 1].

In the arithmetic circuit 12 configured as described above, the first adder 14 cumulatively adds the numerator value K of the fraction (K / L) indicating the decimal value J in the multiple value [N + J]. When the addition value H reaches a denominator value (upper limit value) L of a fraction (K / L) indicating the decimal value J, the output value E of the comparison circuit 18 becomes one value. As a result, the frequency division ratio G output from the second adder 19 is [N + 1].

Then, in the frequency division ratio G sequentially applied from the arithmetic circuit 12 to the frequency divider 6, the rate at which [N + 1] appears is the upper limit value of how many (how many) numerator values K are accumulated. Since it is represented by the denominator value L, as a result, the decimal value J (=) in the multiple value [N + J] (= [N + K / L])
K / L).

Therefore, the average frequency division ratio G applied to the frequency divider 6 becomes the multiple value [N + J] set in the arithmetic circuit 12, so that the output frequency of the output frequency signal d output from the output terminal 5 f _O can be set to [N + J] times the reference frequency f _R.

In this case, the first adder 14 calculates the sum H
Denominator value (upper limit) L of decimal value J before overflow
, The output value E from the comparison circuit 18 becomes 1, and the feedback value to the first adder 14 is cleared.
The output added value H returns to the initial value K which is the numerator value.

Therefore, by using the first adder 14 as a bit-structured adder having a margin, one first adder 14 can be used.
Can correspond to various denominator values L.
As a result, the denominator value L of the decimal value J of the multiple value [N + J] can be set to an arbitrary integer value, and conversely, the numerator value K can be set to an arbitrary integer value. Therefore, with the first adder 14 of one, it is possible set the output frequency f _O of the output frequency signal d to any rational multiple of the reference frequency f _S of the reference frequency signal a. For example, as a decimal value J of a multiple value [N + J], J
Fractions such as = 1/100001, 1/1002 can be set.

The output frequency f _O of the output frequency signal d
Is changed, it is only necessary to input the corresponding multiple value [N + J] to the frequency division condition setting unit 13, so that the operability of the frequency signal generator can be greatly improved.

[0062]

As described above, in the frequency signal generator according to the present invention, the addition value H output from the first adder in the arithmetic circuit for calculating the frequency division ratio applied to the frequency divider is doubled. The decimal value J constituting the numerical value [N + J] is expressed as a fraction (K
/ L) is compared with the denominator value (upper limit) L of the fraction, and when the added value H reaches this upper limit, the division ratio G of [N + 1] is output. Therefore, the output frequency of the output frequency signal can be set to an arbitrary rational number with only one simple hardware circuit member, and operability can be improved and manufacturing costs can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a frequency signal generator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an arithmetic circuit incorporated in the frequency signal generator according to the embodiment;

FIG. 3 is a block diagram showing a schematic configuration of a general frequency signal generator using a PLL circuit;

FIG. 4 is a waveform chart showing a change in a frequency division ratio applied to a frequency divider incorporated in the frequency signal generator.

FIG. 5 is a block diagram showing a schematic configuration of a conventional frequency signal generator employing a fractional PLL.

FIG. 6 is a block diagram showing a detailed configuration of an arithmetic circuit incorporated in the frequency signal generator using the fractional PLL.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Reference signal generator 2 ... Phase detector 3 ... Loop filter 4 ... VCO 5 ... Output terminal 6 ... Divider 12 ... Operation circuit 13 ... Division condition setting part 14 ... First adder 15 ... First Delay circuit 16: Second delay circuit 17: Upper limit value memory 18: Comparison circuit 19: Second adder

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 BB10 CC01 CC21 CC41 CC53 CC58 DD13 DD44 GG09 HH10 JJ05 KK36 PP03 QQ02 RR12 RR18 SS05

Claims (1)

[Claims] 1. A reference signal generator for generating a reference frequency signal having a reference frequency, and detecting a phase difference between the reference frequency signal output from the reference signal generator and the input divided signal. A phase detector that outputs a phase difference signal corresponding to the phase difference, a voltage controlled oscillator that outputs a frequency signal having a frequency corresponding to the phase difference signal output from the phase detector, A frequency divider (6) that divides the frequency of the output frequency signal output from the voltage controlled oscillator by an applied integer division ratio and sends the frequency-divided signal to the phase detector; From the multiple value (N + J) consisting of the numerical value (N) and the decimal value (J), each division ratio is set so that the average value of the division ratio (G) sequentially applied to the frequency divider becomes the multiple value. Arithmetic circuit (12) for sequentially calculating
The arithmetic circuit (12) includes: an upper limit value memory for storing a denominator value (L) when the input decimal value is represented by a fraction (K / L) as an upper limit value. (17) a first value for adding and outputting the numerator value (K) and the input feedback value when the input decimal value is expressed as a fraction
An adder (14), a first delay circuit (15) for delaying the added value (H) output from the first adder and sending it as a feedback value to the first adder; A second delay circuit for delaying the added value (H) output from the first adder; an added value output from the second delay circuit; and an upper limit value stored in the upper limit value memory. And outputs a zero value output value (E) when the added value is less than the upper limit value, and outputs a one value output value (E) when the added value reaches the upper limit value, A comparing circuit (18) for clearing the delay circuit of (1), and adding the input integer value and the output value (E) of the comparing circuit to obtain the added value as a dividing ratio (G) to the divider. A frequency signal generator including a second adder (19) for applying the frequency signal.