JP2000294734A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device which can prevent the occurrence of electromigration without reducing the number of mounted unit cells. SOLUTION: In a semiconductor integrated circuit device, a main clock driver 24 is formed in a core area 12 and sub-clock drivers 26 are formed in unused portions of an IQ cell area 14. Then clock supplying main wiring 18 is formed in the upper layer of the core area 12 in parallel with one side of the boundary of the area 12, and clock supplying wiring 22 is formed in such away that one end of the wiring 22 is connected to the main wiring 18 and the other end is extended to the end sections of the unused portions in the IO cell area 14 perpendicularly to the main wiring 18. In addition, the output terminals of the sub-clock drivers 26 are connected to the wiring 22, and the input terminals of the drivers 26 are connected to the output terminal of the main clock driver 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a gate array (g) in which a unit cell in which a basic circuit is formed is formed in a core region of a semiconductor chip.
The present invention relates to an arrangement of a clock driver and a wiring (clock tree) thereof in a semiconductor integrated circuit device such as a semiconductor device.

[0002]

2. Description of the Related Art Recently, clock skew has become a problem in semiconductor integrated circuit devices due to the demand for high-speed system operation, and various countermeasures have been proposed for eliminating this clock skew. .

[0003] However, in any of the methods, a large number of flip-flops must be driven, so that a large number of clock drivers are required for the semiconductor integrated circuit device.

[0004]

As described above, the conventional semiconductor integrated circuit device requires a large amount of clock drivers to eliminate clock skew. Therefore, the conventional semiconductor integrated circuit device is mounted on a semiconductor integrated circuit device, for example, a gate array. There is a problem that the number of unit cells to be used is reduced.

When a clock driver is arranged in a core region of a gate array, only a thin power supply line for a unit cell can be used as a clock driver line in the core region. Therefore, a large amount of current flows during charging and discharging between the clock driver having a large load capacity and the load capacity, and a large voltage drop occurs in the power supply wiring on the unit cell. There has been a problem that electromigration occurs in the cell power supply wiring.

The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit device which prevents the occurrence of electromigration without reducing the number of mounted unit cells. Aim.

[0007]

In order to achieve the above object, according to the present invention, a unit cell in which a basic circuit is formed is arranged in a core region of a semiconductor chip, and a unit cell is provided around the core region. In a semiconductor integrated circuit device in which an IO cell region in which an IO cell is arranged is formed and a plurality of clock drivers for driving clock supply wiring are formed in a semiconductor chip, a clock signal is externally received, and A main clock driver for distributing a clock signal to a sub-clock driver among the clock drivers is formed in the core area, the sub-clock driver is formed in an unused portion in the IO cell area, and a clock supply layer is provided in an upper layer of the core area. The main wiring is formed so as to be parallel to one side of the boundary of the core region, and to be orthogonal to the main wiring for clock supply. A clock supply line is formed such that one end is connected to the clock supply main line and the other end is extended to an end of an unused portion in the IO cell area, and the output terminal of the sub clock driver is connected to the clock supply line. And an input terminal connected to an output terminal of the main clock driver.

According to a second aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, a wiring length from an output end of the main clock driver to each of the sub clock drivers is formed to be equidistant. It is characterized by the following.

According to a third aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first or second aspects, the core region is connected to an adjacent IO cell in each of the IO cells. A power supply wiring is formed along one side of the boundary, and a clock input wiring for supplying a clock signal to each IO cell is formed on the core region side in each of the IO cells in parallel with the power supply wiring, A clock input terminal is provided on the core area side in an unused portion of the IO area, and the clock input wiring and the clock supply wiring are connected via the clock input terminal.

[0010] The invention described in claim 4 is the first to third aspects of the present invention.
In the semiconductor integrated circuit device according to any one of the above, the power supply wiring formed in the IO cell has an extremely larger cross-sectional area than the power supply wiring for the unit cell.

According to the semiconductor integrated circuit device of the present invention, the subclock driver is formed in an unused IO cell in the IO cell area, and the power supply wiring of the unit clock is used as the power supply wiring of the subclock driver. Since a power supply wiring having a large cross-sectional area is formed and used for each IO cell, the occurrence of electromigration can be prevented without reducing the number of unit cells mounted on the semiconductor chip.

According to the semiconductor integrated circuit device of the second aspect, the wiring length from the output terminal of the main clock driver to each sub clock driver is formed so as to be equidistant. The propagation delay times become equal, and clock skew hardly occurs.
Note that the wiring length in this case may be formed so as to be a distance near equidistant.

According to a third aspect of the present invention, a power supply wiring is formed along one side of the core region so as to be connected to an adjacent IO cell in each IO cell, and An IO cell and a vacant IO cell (IO cell are formed in advance so that a clock input wiring for supplying a clock signal to each IO cell is formed on the core region side of each IO cell in parallel with the power supply wiring. Cell), and the wiring between the subclock drivers can be wired simply by arranging the IO cell and the empty IO cell in the IO cell area at the time of layout, so that a large load is imposed on the layout software. Without wiring, wiring required for supplying a clock signal can be performed.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. Prior to the description of the present embodiment, a configuration of a gate array as a conventional semiconductor integrated circuit device will be briefly described with reference to FIGS.
In FIG. 4, a core region 12 in which unit cells are arranged and an IO cell region 14 in which IO cells are arranged around the core region 12 are formed on the semiconductor chip 10.
A pad 1 connected to a terminal on the package side and a wire 40 is provided outside the IO cell region 14 on the semiconductor chip 10.
6 are provided. A clock input from the outside is provided in the core region 12 by a plurality of sub-clock drivers 26.
And a plurality of sub-clock drivers 26 are formed.

Further, a clock supply main wiring 1 for supplying a clock signal to a circuit element constituting a basic circuit formed in a unit cell (not shown) is provided in the core region 12.
The clock supply sub-wiring 8 and the clock supply sub-wiring 20 are formed in a T-shape (in the illustrated example, a fish bone shape: the clock supply sub-wiring 20 crosses the clock supply main wiring 18). The output terminal of the main clock driver 24 and the input terminal of each subclock driver, and the output terminal of each subclock driver and the main clock supply wiring 18 are connected via unit cell wiring. As shown in FIG. 4, there is an area where many IO cells can be arranged in the IO cell area 14 in relation to the package pins. That is, in FIG. 5, the hatched portion of the IO cell region 14 indicates an unused portion, and the number of IO cells actually arranged in the IO cell region 14 is considerably small as shown in FIG. Are unused, and the unused IO cell arrangement area is used only for connection of a power supply section of a normal IO cell used in the IO cell area 14. In FIG. 5, reference numeral 50 denotes a conductor terminal connected to the package side.

In the present invention, a clock tree is formed by using an unused portion of the IO cell area 14, that is, an unused IO cell arrangement area in the IO cell area 14.

FIG. 1 shows a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. In the present embodiment, it is assumed that the clock tree uses a T type. In the figure,
On the semiconductor chip 10, a core region 12 in which unit cells are arranged and an IO cell region 14 in which IO cells are arranged around the core region 12 are formed. Outside the IO cell region 14 on the semiconductor chip 10, pads 16 connected to terminals on the package side by wires 40 are provided. In the core region 12, a main clock driver 24 for distributing a clock input from the outside to a plurality of sub-clock drivers 26 is formed. The IO cell area 14 has an IO cell (shaded area) 28 in which IO cells to be used are arranged, and an empty IO cell area 30 which is an unused part. In the case of a T-type clock tree, the output ends of the plurality of sub-clock drivers 26 are connected to a clock supply main wiring that is thick, that is, has a large cross-sectional area.
All of the plurality of sub-clock drivers 26
It is arranged in the O cell region 30.

Further, a clock supply main wiring 18 and a clock supply wiring 20 for supplying a clock signal to circuit elements constituting a basic circuit formed in a unit cell (not shown) are provided above the core region 12. It is formed in a T shape. That is, the clock supply main wiring 18 is formed in parallel with one side of the boundary of the core region 12, and the clock supply sub wiring 20 is formed so as to be orthogonal to the clock supply main wiring 18. The output terminal of the main clock driver 24 and the input terminal of each sub-clock driver 26 are connected via unit cell wiring formed based on a wiring mask so that the wiring lengths thereof are substantially equal to each other. The same thickness (cross-sectional area) as that of the clock supply sub-wiring 20 so that the distance between the output end of each sub-clock driver 26 and the clock supply main wiring 18 is the shortest.
Are connected by the clock supply wiring 22.

According to the semiconductor integrated circuit device of the first embodiment of the present invention, the number of unit cells to be mounted can be increased because the subclock driver is formed in an empty IO cell area of the IO cell area. Can be.

Further, since the wiring lengths from the output end of the main clock driver to the respective sub-clock drivers are formed so as to be substantially equidistant, the propagation delay time of the clock signal in the wiring becomes substantially equal and clock skew occurs. It becomes difficult.

A semiconductor integrated circuit device according to a second embodiment of the present invention will be described with reference to FIGS. The semiconductor integrated circuit device according to the present embodiment is different from the semiconductor integrated circuit device according to the first embodiment in the configuration in that the wiring patterns of the power supply wiring and the clock input wiring in the IO cell area are set in advance for each IO cell. In the layout, each IO cell is arranged in the IO cell area, and the wiring between the output terminal of the main clock driver and the input terminal provided for the clock input wiring in the vacant IO cell and the vacant IO cell The wiring between the output end of the subclock driver and the clock supply main wiring formed in the core region is performed. The other configuration is completely the same, and the duplicate description is omitted. . FIG. 2 shows an empty IO cell area 30.
FIG. 3 shows the wiring pattern of an empty IO cell
Each of the wiring patterns of the O cell 28 is shown. In FIG. 2, an empty I
The wiring pattern of the O cell supplies power to a logic gate power supply line 300, a logic gate ground line 302, and an I / O driver for supplying power to a logic gate constituted by unit cells arranged in the core region. And a driver ground line 306, which are formed in parallel with each other. The power supply line 300 for the logic gate and the ground line 302 for the logic gate have a much larger cross-sectional area than the power supply wiring for the unit cells for supplying power to the unit cells arranged in the core region. Specifically, for example, the line width of the unit cell power supply wiring is 0.5 μm (CM
The line width of the logic gate power supply line 300 and the logic gate ground line 302 is 8.5 μm, whereas the line width of the OS is 1.9 μm.

Further, a clock input line 308 for supplying a clock signal to each IO cell and a clock input line 308 for supplying a clock signal to each IO cell are provided on the core area side of the empty IO cell area 30 in parallel with the driver power supply line 304 and the driver ground line 306. A clock enable input line 310 for providing a clock enable signal is formed. The clock input line 308 and the clock enable input line 310 are provided with input terminals 320 and 322.

When arranging the vacant IO cell in the vacant cell region 30 at the time of layout, the power supply line 300 for the logic gate and the ground line 302 for the logic gate are parallel to one side of the boundary of the core region 12 (FIG. 1). To be placed. After arranging the vacant IO cell in the vacant cell area 30, the clock input line 330,
The clock enable input line 340 is connected to the output terminal of the main clock driver 24, and is connected to the output terminal of the sub clock driver 26 provided in the empty IO cell and to the main clock supply wiring 18.

The wiring pattern of the IO cell 28 includes input terminals 320 and 322 and a clock input line 33 as shown in FIG.
0, except that the clock enable input line 340 is not provided, the wiring pattern is the same as that of the empty IO cell area 30, and the same elements are denoted by the same reference numerals and overlapping description will be omitted. This IO cell 28 is also arranged at a predetermined position in the IO cell area 14 at the time of layout similarly to the empty IO cell.

As described above, at the time of layout, the IO cell area 1
By arranging empty IO cells and IO cells 28 in 4, power supply wiring and clock supply wiring are provided between the subclock drivers.

According to the semiconductor integrated circuit device of the second embodiment of the present invention, the subclock driver is formed in an empty IO cell in the IO cell area, and the power supply for the unit cell is used as the power supply wiring of the subclock driver. Since the power supply wiring having a larger cross-sectional area than the wiring is formed and used for each IO cell, the occurrence of electromigration can be prevented without reducing the number of unit cells mounted on the semiconductor chip.

The wiring between the sub-clock drivers can be performed by arranging IO cells and empty IO cells in the IO cell area at the time of layout, so that a clock signal can be supplied without imposing a large load on layout software. Necessary wiring can be performed.

[0028]

As described above, according to the semiconductor integrated circuit device of the first to fourth aspects, the subclock driver is formed in an empty IO cell in the IO cell area, and is used as a power supply wiring of the subclock driver. Since power supply wiring having a larger cross-sectional area than the power supply wiring for unit cells is formed and used for each IO cell, the occurrence of electromigration can be prevented without reducing the number of unit cells mounted on the semiconductor chip. it can.

According to the semiconductor integrated circuit device of the present invention, since the wiring lengths from the output terminal of the main clock driver to each of the sub clock drivers are formed so as to be approximately equidistant, clock signal wiring is performed. , The propagation delay times become substantially equal, and clock skew hardly occurs.

According to a third aspect of the present invention, a power supply wiring is formed along one side of the core region so as to be connected to an adjacent IO cell in each IO cell, and IO cells and empty IO cells are created in advance so that a clock input wiring for supplying a clock signal to each IO cell is formed on the core region side of each IO cell in parallel with the power supply wiring. Wiring between clock drivers is performed by arranging IO cells and empty IO cells at the time of layout.
Since wiring can be performed only by arranging in the O cell region, wiring required for supplying a clock signal can be performed without applying a large load to layout software.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a wiring pattern of an empty IO cell of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a wiring pattern of an IO cell of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a configuration of a conventional semiconductor integrated circuit device.

FIG. 5 is an explanatory diagram showing a use state of an IO cell area in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 12 Core area 14 IO cell area 16 Pad 18 Clock supply main wiring 20 Clock supply sub wiring 22 Clock supply wiring 24 Main clock driver 26 Sub clock driver 28 IO cell 30 Free IO cell area

Claims (4)

[Claims] 1. A unit cell in which a basic circuit is formed is arranged in a core region of a semiconductor chip, an IO cell region in which an IO cell is arranged is formed around the core region, and a clock supply wiring is formed. In a semiconductor integrated circuit device in which a plurality of clock drivers to be driven are formed in a semiconductor chip, a main clock driver for receiving a clock signal from the outside and distributing a clock signal to a sub clock driver among the plurality of clock drivers is provided in the core area. Formed into
The sub-clock driver is formed in an unused portion in the IO cell region, a main clock supply line is formed in an upper layer of the core region in parallel with one side of a boundary of the core region, and the main line for clock supply is formed. A clock supply line is formed so that one end is connected to the clock supply main line so as to be orthogonal, and the other end extends to an end of an unused portion in the IO cell area, and an output terminal of the subclock driver. Is connected to the clock supply wiring, and an input terminal is connected to an output terminal of the main clock driver. 2. The semiconductor integrated circuit device according to claim 1, wherein a wiring length from an output terminal of the main clock driver to each sub clock driver is formed to be equidistant. 3. A power supply line is formed along one side of a boundary of the core region so as to be connected to an IO cell adjacent to each of the IO cells, and each of the IO cells is formed in parallel with the power supply line. A clock input wiring for supplying a clock signal to each IO cell is formed on the core region side of the
2. A clock input terminal is provided on the core area side in an unused portion of an IO area, and the clock input wiring and the clock supply wiring are connected via the clock input terminal. Or the semiconductor integrated circuit device according to any one of 2. 4. The semiconductor integrated circuit device according to claim 1, wherein the power supply wiring formed in the IO cell has a cross-sectional area much larger than that of the unit cell power supply wiring. .