JPH1140674A - Method of designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design a semiconductor integrated circuit, using an I/O cell pattern, irrespective of the number of different voltage sources by designing, using an I/O pattern having a pattern of nodes connectable to patterns of outer and inner power lines. SOLUTION: A first node pattern N1 has a terminal A1 connectable to an outer power line pattern at a first area at the top end shown by a triangle and terminal A2 connectable to an inner power line pattern L1 at a second area below it shown by a triangle. A second node pattern N2 has a terminal B1 connectable to an outer ground line pattern at a first area at the top end shown by a triangle and terminal B2 connectable to an inner ground line pattern L2 at a second area below it shown by a triangle. This allows an semiconductor integrated circuit to be designed, using one kind of I/O cell pattern, irrespective of the number of different voltage sources.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for designing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, LSI (Large Scale Integrated)
When a plurality of power supplies of different voltages are used in a circuit chip, the power supply voltage is selectively used by using a plurality of I / Os. Such an LSI chip is called CAD
(Computer Aided Design) When designing with a computer equipped with software, different voltages are used, for example, in the case of using two power supplies, the pattern of I / O cells includes:
The I / O cell pattern arrangement example shown in FIG. 4 and the I / O cell pattern arrangement example in FIG. 5 are shown. In FIGS. 4 and 5, the word “pattern” is omitted in the description of the reference numerals of each unit to avoid complication.

In the case of FIG. 4, a pattern of a ground line (hatched) and a pattern of a power supply line (hatched) of the same width and parallel to each other in a rectangular frame are provided as I / O cell patterns. ) Is formed so as to connect two parallel sides of the rectangular frame, and a pattern of pads in the rectangular frame is formed.

[0004] The I / O corresponding to the power supply of the first voltage.
The patterns C1, C2, and C3 of the O cell are sequentially arranged such that the respective ends of the ground line pattern and the power supply line pattern are in contact with each other. I / O cell pattern C1,
C2 and C3 are pad patterns P1, P2 and P, respectively.
3 is provided. A power supply terminal pattern TB1 having a power supply line pattern is arranged on the left end of the power supply line pattern of the left I / O cell pattern C1 such that the right end of the power supply line pattern is in contact with the power supply terminal pattern TB1. A ground terminal pattern TG1 having a ground line pattern is arranged on the right end of the ground line pattern of the right I / O cell pattern C3 such that the left end of the ground line pattern is in contact with the ground terminal pattern TG1.

The first power line pattern L1 is constituted by the power terminal pattern TB1 and the I / O cell patterns C1, C2, C3. A ground terminal pattern TG1 and an I / O cell pattern C1,
The first ground line pattern L2 is formed by the ground line patterns C2 and C3.

Also, the patterns C4 and C5 of the I / O cells corresponding to the power supply of the second voltage are sequentially arranged so that the respective ends of the ground line pattern and the power supply line pattern are in contact with each other. The I / O cell patterns C4 and C5 have pad patterns P4 and P5, respectively. A power terminal pattern TB having a power line pattern is provided at the left end of the power line pattern of the left I / O cell pattern C3.
2 are arranged such that the right ends of the power supply line patterns are in contact with each other. A ground terminal pattern TG2 provided with a ground line pattern is arranged on the right end of the ground line pattern of the right I / O cell pattern C5 such that the left end of the ground line pattern is in contact with the ground terminal pattern TG2.

The power supply terminal pattern TB2 and the I / O cell patterns C4 and C5 have respective power supply line patterns.
A second power line pattern L3 is formed. The second ground line pattern L4 is formed by the ground terminal pattern TG2 and the I / O cell patterns C4 and C5.

Then, patterns C1 to C of each I / O cell
In 5, a pattern of each input-side buffer circuit (input-side inverter circuit) and / or a pattern of an output-side buffer circuit (output-side inverter circuit) are connected between a power supply line pattern and a ground line pattern. , And these are not shown.

In the case of FIG. 5, as the I / O cell pattern, a ground line pattern (hatched) and a power line pattern (hatched) having the same width and being parallel to each other in a rectangular frame. 2) are alternately formed so as to connect two parallel sides of the rectangular frame and a rectangular pad pattern is used.

Three I / O cell patterns C1, C2,
C3 is sequentially arranged such that each end of each of the alternating ground line pattern and the power supply line pattern is in contact with each other. The I / O cell patterns C1, C2, and C3 have pad patterns P1, P2, and P3, respectively.

The patterns C1, C2, and C3 of the I / O cells corresponding to the power supplies of the first and second voltages are arranged such that the respective ends of the ground line pattern and the power supply line pattern are in contact with each other. In order. The I / O cell patterns C1, C2, and C3 are respectively pad patterns P1,
P2 and P3 are provided. Power supply terminal patterns TB1 and TB2 each having a power supply line pattern are arranged on the left end of each power supply line pattern of the left I / O cell pattern C1 such that the right end of each power supply line pattern is in contact with the power supply line pattern. The ground terminal patterns TG1 and TG2 each having a ground line pattern are arranged on the right end of each ground line pattern of the right I / O cell pattern C3 such that the left ends of the ground line patterns are in contact with each other.

The power supply terminal pattern TB1 and the I / O cell patterns C1, C2, C3 constitute the first and second power supply line patterns L1, L3, respectively. The first and second ground line patterns L2 and L4 are configured by the ground terminal pattern TG1 and the I / O cell patterns C1, C2 and C3.

[0013]

In the case of the example of the arrangement of the I / O cell patterns shown in FIG. 4, the groups of patterns C1, C2, C3; C4, C5 of the I / O cells having different power supply voltages include: Be sure to use one set of power terminal and ground terminal TB1, TG
1: TB2 and TG2 are required, and patterns of I / O cells having different power supply voltages cannot be arranged in combination.

In the case of the I / O cell pattern shown in FIG. 5, the number of power supplies of different voltages is N at maximum (N = 2, 3, 4,...).
In the case of ()), one set of power and ground wires, two sets,.
.., N sets of I / O cell patterns, that is, N types of I / O cells
Since a / O cell pattern must be provided,
It takes time to develop the O cell pattern.

Therefore, when the number of power supplies of different voltages is N at maximum (N = 2, 3, 4,...), Only a pattern of I / O cells having N sets of power supply lines and ground lines is provided. It is conceivable that the number of power supplies of different voltages is 1, 2, 3,..., N, but the smaller the number of power supplies of different voltages is, the more I / O The number of unused power supply line patterns and ground line patterns in the cell pattern increases, thereby increasing the useless area in the I / O cell pattern and increasing the chip size of the LSI chip to be designed. turn into.

In view of the above, the present invention relates to a semiconductor integrated circuit design method for designing a semiconductor integrated circuit using a pattern of an I / O cell, wherein one type of I / O cell is used regardless of the number of power supplies of different voltages. It can be performed using the pattern of the O cell, the pattern of the I / O cell can be freely arranged,
Let us propose a device that can reduce the number of power supply terminal patterns attached to the I / O cell pattern and that does not waste the area of the I / O cell pattern regardless of the number of power supplies of different voltages. It is assumed that.

[0017]

According to the method of designing a semiconductor integrated circuit of the present invention, a pattern of a first node connectable to a pattern of an external power supply line and a pattern of an internal power supply line or / and an external ground line is provided. And a second node pattern connectable to an internal ground line pattern.
The semiconductor integrated circuit is designed using the O cell pattern.

According to the present invention, the pattern of the first node can be connected to the pattern of the external power supply line and the pattern of the internal power supply line, and / or the pattern of the second node can be connected to the external ground. It can be connected to line patterns and internal ground line patterns.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for designing a semiconductor integrated circuit according to the present invention is for designing a semiconductor integrated circuit using a pattern of an I / O cell. A first node pattern connectable to a power line pattern and an internal power line pattern or / and a second node pattern connectable to an external ground line pattern and an internal ground line pattern. There is a feature.

Embodiment A method of designing a semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to FIG. In this design method, when a plurality of power supplies of different voltages are used in an LSI (semiconductor integrated circuit) chip, the power supply voltage is selectively used by using a plurality of I / Os.
This is an example in which an I chip is designed by a computer equipped with CAD software. An example of an I / O cell pattern employed in this design method will be described with reference to FIG. In FIG. 1, the word “pattern” is omitted in the description of the reference numerals of each unit to avoid complication.

This I / O cell pattern has a rectangular frame F
In the frame F, a pattern of a power line having a predetermined width parallel to each other (a band-shaped hatching is provided inside the contour) L1 and a pattern of a ground line having a predetermined width (inside the contour) L2)
Is formed so as to connect between two long sides parallel to each other of the rectangular frame, and a rectangular pad pattern P is formed in another portion of the frame F.

In the frame F, a ground line pattern L2
, One end is close to the power line pattern L1, one end is close to the frame F, a first node pattern (hatched) N1 having a predetermined width and one end is close to the ground line L2, A second node pattern (hatched) N2 of a predetermined width reaching the frame F is provided.

The first node pattern N1 has a terminal A1 that can be connected to an external power supply line pattern at a tip portion indicated by a triangle, and an internal power supply line pattern L1 at a lower end portion indicated by a triangle. And a terminal A2 that can be connected to the terminal.

The second node pattern N2 has a terminal B1 which can be connected to an external ground line pattern at a tip indicated by a triangle and an internal ground line pattern L2 at a lower end indicated by a triangle. And a terminal B2 that can be connected to the terminal.

Patterns N1, N of first and second nodes
2 is connected to a pattern (not shown) of an input side and / or output side buffer circuit (an inverter circuit is also possible) as shown in FIG. 2, for example.

In an actual LSI chip, the power line pattern L1 and the ground line pattern L2 correspond to the upper conductive layer, and the first and second node patterns N1 and N2 correspond to the conductive layers from below. I do. The conductor layer is, for example, an aluminum layer.

In the buffer circuit of FIG. 2, the source is the internal power line pattern L through the first node pattern N1.
1 and a NMOS transistor Q2 whose drain is connected to the drain of the transistor Q1 and whose source is connectable to the internal ground line pattern L2 through the second node pattern N2. The gates of the transistors Q1 and Q2 are connected to the input electrode pattern Pin, and the drains of the transistors Q1 and Q2 are commonly connected to form a pad electrode pattern Pe (corresponding to the pad pattern P in FIG. 1). Connected.

Next, referring to FIG. 3, I / O shown in FIG.
An example of an O cell pattern arrangement will be described. In this example, when three power supplies having different voltages from each other are used, six I
The ends of the internal power line pattern (first power line pattern) L1 and the internal ground line pattern (first ground line pattern) L2 are connected to each other. Arrange them so that they face each other.

L3 is a pattern of a second power line (external power line), L4 is a pattern of a second ground line (external ground line), and L5 is a pattern of a third power line (external power line). ,
L6 is a pattern of a third grounding line (external grounding line).
The / O cell patterns C1 to C6 are arranged so as to be parallel to the first power line pattern L1 and the first ground line pattern L2.

In the patterns C1 and C2 of the I / O cell, the terminal A1 of the pattern N1 of each first node is connected to the pattern L3 of the second power supply line, and the terminal A of the pattern N2 of each second node. B1 is the second ground line pattern L4
Connected.

In the patterns C3 and C4 of the I / O cell, the terminal A2 of the pattern N1 of each first node is connected to the pattern L1 of the first power supply line, and the terminal A of the pattern N2 of each second node. B2 is the first ground line pattern L2
Connected.

In the patterns C5 and C6 of the I / O cell, the terminal A1 of the pattern N1 of each first node is connected to the pattern L5 of the third power supply line, and the terminal B1 of the pattern N2 of each second node. Are connected to the third ground line pattern L6.

Then, the patterns C1 to C of each I / O cell
6, a pattern of the input buffer circuit (input inverter circuit) and / or a pattern of the output buffer circuit (output inverter circuit) are connected between the patterns N1 and N2 of the first and second nodes. However, these are not shown.

[0034]

According to the present invention, the first node pattern connectable to the external power supply line pattern and the internal power supply line pattern or / and the external ground line pattern and the external ground line pattern Since the semiconductor integrated circuit is designed using the pattern of the I / O cell having the pattern of the second node connectable to the semiconductor device, the semiconductor integrated circuit is designed using the pattern of the I / O cell. In a method of designing an integrated circuit, the design can be performed by using one type of I / O cell pattern regardless of the number of power supplies of different voltages.
The number of power supply terminal patterns associated with the cell pattern can be reduced, and the I / O cell pattern can be obtained without wasting the area regardless of the number of power supplies of different voltages.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an I / O cell pattern used in a method of designing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a buffer circuit.

FIG. 3 is a diagram showing an example of a pattern arrangement of the I / O cell of FIG. 1;

FIG. 4 shows an I used in a conventional semiconductor integrated circuit design method.
FIG. 3 is a diagram showing an example of a pattern arrangement of / O cells.

FIG. 5 is a diagram showing an example of a pattern arrangement of another I / O cell used in a conventional semiconductor integrated circuit design method.

[Explanation of symbols]

C1 to C6: I / O cell pattern, L1, L3, L5
... power line pattern, L2, L4, L6 ... ground line pattern, N1 ... first node pattern, N2 ... second node pattern, P ... pad pattern, A1, A2,
B1, B2 ... terminals

Claims (3)

[Claims] 1. An I / O circuit comprising a pattern of a node connectable to a pattern of an external power line and a pattern of an internal power line.
A method for designing a semiconductor integrated circuit, comprising designing a semiconductor integrated circuit using a pattern of an / O cell. 2. An integrated circuit comprising a pattern of a node connectable to a pattern of an external ground line and a pattern of an internal ground line.
A method for designing a semiconductor integrated circuit, comprising designing a semiconductor integrated circuit using a pattern of an / O cell. 3. A first node pattern connectable to an external power line pattern and an internal power line pattern, and a second node pattern connectable to an external ground line pattern and an internal ground line pattern. A method for designing a semiconductor integrated circuit, comprising designing a semiconductor integrated circuit using an I / O cell pattern including a node pattern.