JP2000286385A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide techniques of restraining noises from diffusing and making an integrated circuit operate stably. SOLUTION: A shield metal layer 31 fixed at a ground level or a power supply voltage level is interposed between a semiconductor substrate 52 and a signal wiring layer 54. Noises emitted from the semiconductor substrate 52 are blocked by this shield metal layer 31 so as not to be transmitted from the semiconductor substrate 52 to the signal wiring layer 54. A capacitor is formed between shield metal layers, and a power supply voltage can be stabilized by the capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, for example, an ASIC (Application Speech).
The present invention relates to a technology which is effective when applied to a specific IC.

[0002]

2. Description of the Related Art Higher integration and higher density of semiconductor integrated circuits have been developed.
Multi-layered wiring by high speed operation and generalization, ASI
C is an indispensable technology. Multi-layering substantially reduces the wiring area, prevents the chip from increasing, shortens the average wiring length, suppresses the delay in operating speed due to wiring resistance,
Automatic placement and routing by CAD (Computer Aided Design) is possible.

An automatic generation program of a cell arrangement and wiring library for an ASIC automatically generates an arrangement and wiring library for a predetermined logic circuit such as a logical sum or a logical product or a functional cell such as a combinational circuit. The cell actual pattern information is created manually or through a cell pattern automatic generation program based on a previously designed circuit diagram. In the case of automatic, circuit diagram information is input by an interactive graphic input device. Then, the automatic cell pattern generation program automatically generates the actual pattern of the cell based on the arrangement and wiring rules in the processing process of the semiconductor integrated circuit given separately from the circuit diagram information and other designation information. The generated entity pattern information is stored as a cell database in the form of a file on a computer. Based on this, automatic placement and routing of the ASIC is performed.

As an example of a document describing automatic placement and routing, there is an "LSI Handbook (pages 280 to 280)" issued by Ohm Co., Ltd. on November 30, 1984.

[0005]

In the chip layout of a semiconductor integrated circuit, the number of wiring layers has been increased in order to increase the wiring density. However, A / D (analog / digital) conversion circuits and D / A (digital / analog)
In an ASIC that includes a circuit that handles analog signals such as a conversion circuit, the analog portion is particularly susceptible to noise and crosstalk is likely to occur. Yes, the wiring density cannot be increased. Therefore, in many cases,
The benefit of the multilayer wiring cannot be fully enjoyed.

Further, the inventors of the present application have studied that, in a multilayer wiring, a wiring layer stacked at a position closest to a semiconductor substrate is easily affected by noise from the semiconductor substrate. When coupled to an analog unit that is vulnerable to noise, the analog signal may malfunction due to the noise.

An object of the present invention is to provide a technique for suppressing noise wraparound.

Another object of the present invention is to provide a technique for stabilizing circuit operation.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, in a semiconductor integrated circuit having a semiconductor substrate (52) and a signal wiring layer (54) provided on the semiconductor substrate, a ground level or power supply is provided between the semiconductor substrate and the signal wiring layer. A shielding metal layer (31) fixed at a voltage level is laminated so as to cover almost the entire surface of the semiconductor substrate except for a predetermined region.

According to the above means, the shielding metal layer functions as a shielding member for blocking transmission of noise from the semiconductor substrate to the signal wiring layer.
This reduces noise wraparound and achieves stable circuit operation.

In a semiconductor integrated circuit having a semiconductor substrate (52) and a signal wiring layer (54) provided on the semiconductor substrate, the semiconductor integrated circuit is fixed at a ground level between the semiconductor substrate and the signal wiring layer. The shielded metal layer (31) and the shielded metal layer (32) fixed at the power supply voltage level are stacked so as to cover almost the entire surface of the semiconductor substrate except for a predetermined region.

According to the above means, the shielding metal layer functions as a shielding member for blocking transmission of noise from the semiconductor substrate to the signal wiring layer.
This reduces noise wraparound. And a shielding metal layer (31) fixed to the ground level.
And a shield metal layer (32) fixed at the power supply voltage level, a capacitor is formed between the shield metal layers, and the capacitor stabilizes the power supply voltage and stabilizes the circuit operation. To achieve.

At this time, in order to make the layout area of the block available for wiring in the block, it is preferable to lay out the shielding metal layer in an area excluding the layout area of the block. Furthermore, when there is a region where the signal wiring density is high, priority is given to the wiring in the region,
The shielding metal layer may be laid out in a region excluding a layout region of the block and a region preset as a region having a high signal wiring density.

[0015]

FIG. 1 shows an ASIC as an example of a semiconductor integrated circuit according to the present invention.

The ASIC 9 shown in FIG. 1 has a structure in which a metal layer 31 for shielding and a wiring layer 54 are laminated on one semiconductor substrate 52 such as a silicon semiconductor substrate. That is,
A shielding metal layer 31 is laminated via an insulating film so as to cover almost the entire surface of the semiconductor substrate 52 except for a predetermined region,
The signal wiring layer 54 is laminated on the shielding metal layer 31 via an insulating film. Although not particularly limited, the shielding metal layer 31 is formed of aluminum and fixed to the ground level of the circuit. Thus, even if noise is generated in the semiconductor substrate 52, a noise current caused by the noise flows through the shielding metal layer 31, but the noise is transmitted to the signal wiring layer 54 because the noise is shielded by the shielding metal layer 31. It is hard to be done.

Since the shielding metal layer 31 intervenes in this manner, noise is less likely to be transmitted to the signal wiring layer 54, so that the signal wiring layer 54 is coupled to an analog portion that is relatively susceptible to noise. However, malfunctions caused by the noise can be avoided.

FIG. 2 shows another configuration example of the ASIC which is an example of the semiconductor integrated circuit according to the present invention.

The ASIC 9 shown in FIG. 2 is formed by laminating shielding metal layers 31 and 32 and a wiring layer 54 on one semiconductor substrate 52 such as a silicon semiconductor substrate. In other words, the shielding metal layer 31 is laminated on the semiconductor substrate 52 with the insulating film interposed therebetween.
Then, a shielding metal layer 32 is laminated via an insulating film, and a signal wiring layer 54 is laminated on the shielding metal layer 32 via an insulating film. Metal layer for shielding 31,
Although not particularly limited, 32 is formed of aluminum so as to cover substantially the entire surface of the semiconductor substrate 52 except for a predetermined region. The shielding metal layer 31 is fixed to the ground level of the circuit, and the shielding metal layer 32 is fixed to the power supply voltage level of the circuit. Since the shield metal layer 31 and the shield metal layer 32 are disposed adjacently and opposed to each other, the capacitor C is formed therebetween. Since the shielding metal layer 31 is fixed to the ground level of the circuit and the shielding metal layer 32 is fixed to the power supply voltage level of the circuit, the power supply voltage of the circuit is supplied to the capacitor C with reference to the ground level. Capacitor C
Is charged. This reinforces the power supply of the circuit, so that noise is less likely to be generated in the ASIC 9.

As described above, the power supply of the circuit is reinforced by the capacitor C formed by arranging the shield metal layer 31 and the shield metal layer 32 to face each other.
Noise is less likely to be generated in the IC 9. Further, since the shielding metal layers 31 and 32 intervene, it becomes difficult for the noise from the semiconductor substrate 52 to be transmitted to the signal wiring layer 54. For example, the signal wiring layer 54 is coupled to an analog portion which is relatively weak to noise. Even in such a case, a malfunction caused by the noise can be avoided.

In the ASIC 9, when a block having a predetermined function is laid out and a plurality of blocks are connected by the signal wiring layer 54, the shielding metal layers 31, 32 are formed in a region excluding the layout region of the block. Can be laid out. For example, FIG.
As shown in (1), blocks 13, 14, and 15 each having a predetermined function are arranged. Although not particularly limited, the block 13 is an A / D (analog / digital) for converting an analog signal into a digital signal.
A conversion circuit, a block 14 is a logic circuit, and a block 15 is a D / A for converting a digital signal into an analog signal.
(Digital / analog) conversion circuit.

Although not particularly limited, the shielding metal layer 31 is formed in an area excluding the layout area of the blocks 13 to 15. Since the shield metal layer 31 is at the ground level, the ground terminals of the blocks 13 to 15 are connected to the wiring layer 31. Also,
A plurality of bonding pads 12 are arranged so as to surround the shielding metal layer 31. Of these bonding pads, 121, 122, 123, 12
Bonding pads indicated by 4, 126, 127 are connected to the shielding metal layer 31. The bonding pads 121, 122, 123, 124, 126, 12
7 is coupled to an external pin serving as a ground terminal.

The shield metal layer 32 has the same structure as the shield metal layer 31 except that the shield metal layer 32 is fixed at the power supply voltage level.

Next, the automatic placement and routing of the ASIC 9 will be described.

FIG. 8 shows a flow of the overall processing of the automatic placement and routing of the ASIC performed by using the cell placement and routing library 24. As shown in the figure, after a logic diagram is created (S11), the logic is input and a logic simulation is performed (S12). Then,
Among the plurality of wiring layers of the ASIC, a shield metal layer having a fixed potential is set (S13). Although not particularly limited, the layer closest to the semiconductor substrate is the shielding metal layer 31.
It is said. First, the layout is performed so that the entire surface is covered with metal, and then the block automatic placement floor plan is implemented based on the information of the cell placement and wiring library 24 (S
14), as shown in FIG.
14 and 15 are laid out. Then, based on the information of the cell arrangement and wiring library 24, the shielding metal layer 3
1 is corrected (S15). Specifically, as shown in FIG. 6, no metal region is formed in the regions corresponding to the blocks 13, 14, and 15. this is,
In the shield metal layer 31, the blocks 13, 14,.
This is because the wiring within 15 is possible. Next, based on the information of the cell placement and wiring library 24, the blocks 13, 1
The arrangement and wiring in the blocks 4 and 15 are performed (S17), the wiring between the blocks is performed (S17), and when the overall arrangement and wiring is finally determined, it is converted into mask data (S18) and the mask drawing data is obtained. Stored as

FIG. 8 also shows, as a reference, the flow of processing for generating a cell placement and wiring library exclusively by hand. In this case, the designer creates a cell placement and wiring library specification by picking up numerical values while looking at the actual pattern of the cell, then coding while looking at this, further checking it, and if necessary Only after the correction is completed, the cell placement and wiring library 24 is completed.

When ASIC placement and routing is performed according to the procedure shown in FIG. 8, when it becomes necessary to arrange cells of the same logic vertically or horizontally depending on the cell arrangement location, In addition, when it is necessary to use a cell pattern changed according to the arrangement location in order to correct irregularities in signal propagation delays and differences from design values, cells satisfying those requirements are determined in advance. If not prepared, the automatic cell design program is activated during the placement and routing, and a predetermined performance pattern is specified to create necessary cell actual pattern information. As described above, when a new cell in which a pattern or logic is added or changed is required in the course of placement and routing, in other words,
When it is necessary to use cells with different patterns and different performances during placement and routing, the placement and routing library uses
It can be obtained through the above procedure.

According to the above example, the following functions and effects can be obtained.

(1) Since the noise is less likely to be transmitted to the signal wiring layer 54 due to the interposition of the shielding metal layer 31, the signal wiring layer 54 is coupled to the analog portion which is relatively susceptible to noise. However, malfunctions caused by the noise can be avoided. As a result, the influence of noise is reduced, so that the circuit characteristics of the ASIC 9 can be improved.

(2) The power supply of the circuit is reinforced by the capacitor C formed by arranging the shielding metal layer 31 and the shielding metal layer 32 to face each other.
Noise is less likely to occur in the interior. Furthermore, since the shielding metal layers 31 and 32 are interposed, noise from the semiconductor substrate 52 is less likely to be transmitted to the signal wiring layer 54.
Even when 4 are coupled, malfunctions caused by the noise can be avoided.

(3) In particular, in an analog mounted ASIC including an A / D conversion circuit and a D / A conversion circuit, since the analog portion is vulnerable to noise and crosstalk easily occurs, there is no crossing or parallel running of signal wiring. Usually, the layout is made in such a manner that the wiring density cannot be increased. Due to such circumstances, there is room in the wiring area. Therefore, even if the shielding metal layers 31 and 32 are provided as described above, it is not necessary to increase the chip size because the wiring area is insufficient.

Although the invention made by the inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, the shield metal layer 31 may be fixed at the power supply voltage level, and the shield metal layer 32 may be fixed at the ground level.

A signal wiring layer may be formed between the shield metal layers 31 and 32. In this case, the capacitance of the capacitor formed between the shielding metal layers 31 and 32 is reduced, which is disadvantageous in terms of stabilizing the power supply. However, the signal wiring layer disposed between the shielding metal layers 31 and 32 is not used. Since the shield can be sandwiched between both of the shield metal layers 31 and 32, it is advantageous in suppressing the noise wraparound.

Further, in a region where the wiring density is relatively high, the signal wiring may be given priority by removing the region from the metal region in the correction of the metal region in step S15. For example, as shown in FIG. 3, assuming that the wiring density near the logic block 14 is relatively high, a shield metal layer is formed in that region in the modification of the shield metal layer in step S15, similarly to the block region. By not performing this, the area can be used for normal signal wiring. In this case, the pads 124 and 126 are used for bonding signal wiring.

Further, as shown in FIG. 3, a ground level shielding metal layer 71 fixed to the ground level and a power supply voltage level shielding metal layer 72 fixed to the power supply voltage level are formed on the same wiring layer. It may be formed.

In the above description, the invention made mainly by the present inventor is described in terms of the ASI which
Although the description has been given of the case where the present invention is applied to C, the present invention is not limited thereto, and can be widely applied to various semiconductor integrated circuits.

The present invention can be applied on condition that it includes a plurality of blocks having at least a predetermined function.

[0039]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the noise from the semiconductor substrate can be prevented from being transmitted to the signal wiring layer by the shielding metal layer fixed to the ground level or the power supply voltage level, thereby stabilizing the circuit operation. be able to.

By stacking the shielding metal layer fixed to the ground level and the shielding metal layer fixed to the power supply voltage level, a capacitor is formed between the shielding metal layers, and the power supply voltage is reduced by the capacitor. Is stabilized, so that the circuit operation can be stabilized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is an explanatory diagram showing another configuration example of the semiconductor integrated circuit according to the present invention.

FIG. 3 is an explanatory diagram showing another configuration example of the semiconductor integrated circuit according to the present invention.

FIG. 4 is an explanatory diagram of a shield metal layer layout in the semiconductor integrated circuit.

FIG. 5 is an explanatory diagram of a block layout in the semiconductor integrated circuit.

FIG. 6 is an explanatory diagram of metal area correction in the semiconductor integrated circuit.

FIG. 7 is another layout explanatory view of the semiconductor integrated circuit.

FIG. 8 is a flowchart of an overall process of the semiconductor integrated circuit.

[Explanation of symbols]

 9 ASIC 12 Bonding pad 13, 14, 15 Block 31, 32 Metal layer for shielding 52 Semiconductor substrate 54 Signal wiring layer C Capacitor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisao Shibata 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Co., Ltd. 5F038 AC05 BB06 BE07 BH10 BH19 CA17 CD05 DF12 EZ09 EZ20 5F064 AA06 BB35 EE26 EE45 EE52 HH06 HH09 HH11 HH12 HH15

Claims (5)

[Claims] 1. A semiconductor integrated circuit having a semiconductor substrate and a signal wiring layer provided on the semiconductor substrate, wherein the semiconductor integrated circuit is fixed to a ground level or a power supply voltage level between the semiconductor substrate and the signal wiring layer. A semiconductor integrated circuit, wherein a shielding metal layer is laminated so as to cover substantially the entire surface of the semiconductor substrate except for a predetermined region. 2. A semiconductor integrated circuit having a semiconductor substrate and a signal wiring layer provided on the semiconductor substrate, wherein a shielding metal layer fixed to a ground level is provided between the semiconductor substrate and the signal wiring layer. And the shielding metal layer fixed to the power supply voltage level are opposed to each other,
And a semiconductor integrated circuit which is laminated so as to cover substantially the entire surface of the semiconductor substrate except for a predetermined region. 3. A plurality of blocks having a predetermined function are laid out, and when signal wiring between the plurality of blocks is performed by the signal wiring layer, the shielding metal layer excludes a layout area of the block. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is laid out in a region. 4. When a plurality of blocks having a predetermined function are laid out and signal wiring is performed between the plurality of blocks by the signal wiring layer, the shield metal layer is provided in a layout area of the block and a signal area. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is laid out in a region excluding a region set in advance as a region having a high wiring density. 5. The semiconductor integrated circuit according to claim 3, wherein the block includes a circuit that handles an analog signal.