JP3257499B2 - Semiconductor layout apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for designing a semiconductor layout, and more particularly to a method and apparatus for designing a semiconductor layout that enables placement and routing to prevent the occurrence of soft errors in a layout design stage.

[0002]

2. Description of the Related Art In semiconductor-based integrated circuit memories, the amount of charge (memory cell capacity) stored in memory information has been reduced as semiconductor elements have become smaller and larger in capacity.

On the other hand, materials constituting an LSI, particularly solder bumps used on flip-chips as power / ground and signal terminals on the LSI, include P in the natural world.
b) contains a radioactive element (Pb210), and when an α-ray generated from this radioactive element enters the LSI chip surface, a large number of electron-hole pairs are generated.

[0004] Dynamic RAM and static RA
When α rays enter the vicinity of a memory cell such as M or an electrolytically coupled device memory, the generated electron pair flows into the well. When the charge exceeds the critical charge of the memory cell, the charge stored in the memory cell is discharged, so that the “H” level is changed to the “L” level.

[0005] This failure is a transient malfunction that does not repeat and returns to the original state when rewritten, and is called a "soft error".

[0006]

As a countermeasure against the soft error, a shielding material for α rays and a polyimide resin have been conventionally provided outside the mounting wiring (Japanese Patent Laid-Open No. 59-676).
58, JP-A-1-57650, etc.) and various methods for reducing soft errors using a data folding structure have been proposed.

However, as shown in FIG. 2, in the conventional design method, the layout position of the solder bumps could not be recognized at the LSI layout design stage. Has not been realized.

FIG. 2 is a diagram schematically showing a layout of an area bump type flip chip LSI prepared by a conventional method. On the flip-chip LSI 101, solder bumps 102 are arranged in a lattice pattern, and a hard macro 103 and dynamic circuits 104 and 105 are arranged around the solder bumps 102. In FIG. 2, a hatched area is a memory cell part (or a dynamic circuit part inside a data path) inside the hard macro, and an area surrounded by a broken line is a solder bump placement prohibited area 106.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a RAM (memory cell unit) or a dynamic circuit from an α-ray generation source such as a solder bump in a layout design stage. It is an object of the present invention to provide a semiconductor layout design method and apparatus which avoids the influence of α rays and reduces soft errors.

Another object of the present invention is to provide a design standard rule for a through hole or the like to which a stress is applied by a solder bump to control the arrangement position of the through hole, thereby preventing the occurrence of cracks in the substrate due to the stress. An object of the present invention is to provide a method and an apparatus for designing a semiconductor layout that can be avoided.

[0011]

In order to achieve the above object, a semiconductor layout design method according to the present invention is directed to a base library or a dedicated library for an arrangement position of a solder bump or the like, which is loaded on a semiconductor integrated circuit. In addition ,
Make layout design equipment recognize the solder bump placement position
A solder bump recognition layer, which is a layer dedicated to a solder bump serving as a source of α-rays, is defined, and a design standard rule is provided for a through hole or the like subjected to stress by the solder bump. The position of the through hole is controlled to prevent cracks in the substrate due to stress.

In addition, the semiconductor layout design apparatus according to the present invention may provide a layout design in which an arrangement position of the solder bump is placed in a base library or a dedicated library with respect to an arrangement position of a solder bump or the like which is loaded on the semiconductor integrated circuit.
Specializing in solder bumps that are sources of alpha
Means for defining a solder bump recognition layer, which is a layer for use, and means for controlling a layout position of the through hole by providing a design reference rule for a through hole or the like subjected to stress by the solder bump. .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the present invention, a layout design method of a semiconductor integrated circuit according to a preferred embodiment of the present invention includes the steps of: position
Is a source of α-rays.
A solder bump recognition layer, which is a dedicated layer of solder bumps , is defined, and a through-hole or the like subjected to stress by the solder bumps is provided with a design standard rule to control an arrangement position of the through-holes. Prevent cracks on the substrate.

As a technique related to the present invention, solder bumps are used.
Source such as α-rays and memory cells affected by α-rays
For devices such as and dynamic circuits,
Out layer is provided, and the position of solder bump on LSI
By letting the layout design device recognize the
Molycells and dynamic circuits can be specified from solder bumps
It is arranged at a distance more than the distance,
By performing placement control at the layout stage,
So as to prevent soft errors caused by radiation
You may .

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in more detail below with reference to examples.

FIG. 1 is a diagram for explaining the processing flow of an embodiment of the related art of the present invention. As shown in FIG. 1, in this example , in the layout design stage of a semiconductor such as an LSI, a dedicated recognition layer such as a solder bump serving as an α-ray generation source and an arrangement / wiring prohibition layer are provided in advance. ,
The size (size) of the layer and the space between the layers are registered in a technology library (design reference library) of the layout design apparatus as a design reference rule (step S1).
1).

For an α-ray source arranged on an LSI, a base library or a dedicated library
A recognition layer dedicated to the α-ray source is defined (step S1-2).

For example, in an area bump type flip chip in which solder bumps are arranged on an LSI chip, a solder bump recognition layer is defined in a base library for all solder bump arrangement positions on the LSI.

Next, among the semiconductor elements arranged on the base library of the LSI, the influence of α-ray radiation from the solder bumps, such as a memory cell part used in a RAM (hard macro) or a dynamic circuit, etc. In response to this, for elements that cause a soft error, the placement prohibited area of the solder bump is defined in the macro cell or block library (step S1-3).

A memory cell containing layout prohibition information such as solder bumps after loading a base library including recognition layers for layout positions of all α-ray sources such as solder bumps into a layout design device. Then, a macro cell such as a dynamic circuit or a block library is arranged (step S2 and subsequent steps).

At this time, when a relatively large macro cell such as a hard macro or a data path is manually placed in the internal area of the LSI (step S4), a dynamic memory cell portion inside the hard macro or a dynamic cell inside the data path is placed. Since the circuit part may overlap the solder bumps, or it may not be possible to place the solder bumps more than a specified distance from the solder bumps. The verification is performed (steps S5 and S6), and the relocation is performed on the macro cell having an error in the design standard rule (step S5).
4) Alternatively, the data of the solder bump recognition layer on the macro cell is deleted (step S7), and it is checked again whether or not the design criteria between the solder bump layer and the solder bump prohibited layer are satisfied (step S5).

When a relatively small block such as a primitive block is automatically arranged or manually arranged, a space between a solder bump recognition layer and a solder bump placement prohibition layer, which is registered as a design standard rule, is set. Perform placement, wiring, and verification according to pacing rules (step S
8).

As described above, the arrangement position of the α-ray source on the LSI and the exclusive recognition layer and the design standard rule for the element affected by the α-ray are provided to control the arrangement between the α-ray source and the block. Is provided, and as a result, it is possible to prevent occurrence of a malfunction due to a soft error.

Further, FIG. 3, the present embodiment, to improve disposed inside the block, and is a diagram showing a flip chip schematic layout view of after deleting the solder bumps on the memory cells (dynamic circuit) . FIG. 2 shows, as a comparative example, a layout diagram in which solder bumps are formed in a grid pattern on an LSI and are formed by a conventional method.

In FIG. 3, the hatched area is the memory cell portion inside the hard macro (or the dynamic circuit portion inside the data path), and the area surrounded by the broken line is the solder bump placement prohibited area.

In the present embodiment, a countermeasure against soft errors caused by α-rays generated from the solder bumps is as follows: As shown in FIGS. 4A to 4C, the arrangement position of the solder bumps 102 in FIG. This is realized by defining in various libraries as a solder bump recognition layer / a solder bump prohibition layer (area).

FIG. 4A is a schematic diagram of a base library including a solder bump recognition layer as an α-ray generation source. In this case, a dedicated solder bump recognition layer 107 is defined in the base library in accordance with the arrangement position of the solder bumps 102 arranged in a lattice on the LSI of FIG.

FIGS. 4B and 4C show a library of a hard macro (RAM) or a data path defining an α-ray forbidden area and a block (dynamic circuit) for an element affected by α-rays. Etc.) each showing a schematic diagram of the library. In this case, the solder bump placement prohibition area 108 of the α-ray generation source is defined in the memory cell part in the hard macro, and is defined in the dynamic circuit part used internally in the data path.

FIG. 5 is a schematic diagram showing a state in which an error has occurred in the design standard rules when the hard macros, data paths, and block cells are actually arranged on an LSI in this embodiment. .

As shown in FIG. 5, in the hard macro (or data path) and the dynamic circuit, the prohibition portion of the solder bump overlaps the area of the solder bump recognition layer and does not depart from the design standard. Therefore, the hard macro (data path) is on the left side so that the spacing rule between the solder bump prohibited area of the memory cell section (or the dynamic circuit section in the data path) in the hard macro and the solder bump recognition layer is followed. Next, the dynamic circuit rearranges to the right.

In FIG. 5, when the memory cell area inside the hard macro (or the dynamic circuit arrangement area inside the data path) is larger than the arrangement interval of the solder bumps and cannot be arranged more than the design standard, etc. Is
By removing the solder bump recognition layer on the memory cell region (or on the dynamic circuit region) in which the placement prohibition of the solder bump is defined, the solder bump is not placed in that region.

FIG. 6 is a diagram for explaining the improved arrangement of the hard macro and the dynamic circuit and the deletion of the data of the solder bump recognition layer from the arrangement of FIG. 5 according to the present embodiment. FIG. 3 schematically shows a layout diagram in which the improved arrangement and the solder bumps have been removed.

As described above, a hard macro (data path) or a dynamic circuit affected by α rays can be arranged at a specific distance or more from an arrangement position of a solder bump. As a result, a malfunction due to a soft error is caused. Can be prevented.

Next, an embodiment of the present invention will be described.
In a layout design apparatus for a semiconductor integrated circuit, excessive stress is applied to a position where a solder bump is arranged on an LSI, such as an area bump type flip chip. This may cause cracks in the LSI substrate.

Therefore, in the embodiment of the present invention, at the layout design stage, a solder bump recognition layer is provided in advance in the base library of the LSI at the solder bump placement position, and at the same time, the solder bump recognition layer and the through hole immediately below the solder bump are provided. By defining the spacing rule as a design standard rule in the library of the technology section, the placement of the through hole immediately below the solder bump is prohibited. As a result, the increase in stress is mitigated.

[0036]

As described above, according to the related art of the present invention, in a semiconductor layout design apparatus, a random access memory (RAM), a dynamic circuit, and the like are generated from an α-ray source such as a solder bump. It is possible to reduce soft errors by arranging elements affected by α rays at a certain distance or more, or by removing solder bumps in areas where the memory cells and dynamic circuits are arranged. Improve the operation stability and reliability of semiconductor devices.
This has the effect.

Further, according to the present invention, it is possible to provide a layout design apparatus which prohibits the placement of a through hole immediately below a solder bump, thereby alleviating an increase in stress, improving reliability, and improving product life. Is achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing flow of an embodiment of the present invention.

FIG. 2 is a schematic diagram of a layout created by a conventional method as a comparative example.

FIG. 3 is a schematic diagram of an example of a layout created according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining one embodiment of the present invention;
(A) is a base library, (B) is a macro library,
(C) is a diagram showing an example of the contents of a block library.

FIG. 5 is a diagram for explaining one embodiment of the present invention;
Hard macro (dynamic circuit) on base library
FIG. 4 is a diagram showing a layout outline after arrangement.

FIG. 6 is a diagram for explaining one embodiment of the present invention;
FIG. 4 is a diagram illustrating a schematic layout after rearranging a hard macro (dynamic circuit) and removing a solder bump layer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Flip chip 101 Solder bump 103 Hard macro 104 Memory cell part (dynamic circuit) 105 Dynamic circuit 106 Solder bump prohibited area 107 Solder bump recognition layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 21/60 H01L 21/92

Claims (2)

(57) [Claims] 1. A layout setting of the solder bump placement position in a base library or a dedicated library with respect to the placement position of the solder bump applied on the semiconductor integrated circuit.
Of solder bumps that are the source of alpha rays
A solder bump recognition layer, which is a dedicated layer, is defined, and a through-hole subjected to stress by the solder bump is provided with a design standard rule to control an arrangement position of the through-hole. A semiconductor layout design method characterized by preventing the same. Wherein relative positions of such solder bumps load on a semiconductor integrated circuit, the underlying library or private library, the layout setting the position of the solder bumps
Of solder bumps that are the source of alpha rays
Means for defining a solder bump recognition layer which is a dedicated layer; and means for providing a design standard rule for a through hole subjected to stress by the solder bump and controlling an arrangement position of the through hole. A semiconductor layout design apparatus characterized by the above-mentioned.