JP3740387B2 - Automatic flattening pattern generation method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for easily generating a flattening pattern for flattening a wiring layer when a wiring layer formed in a semiconductor integrated circuit such as an LSI is multilayered.
[0002]
[Prior art]
In recent years, wiring layers have been multilayered for high integration of VLSI.
[0003]
However, when the wiring layer is multi-layered, the uneven portion of the lower wiring pattern also affects the upper interlayer insulating film, that is, the interlayer insulating film formed on the wiring layer on which the lower wiring pattern is formed. Therefore, irregularities also appear in the interlayer insulating film. The uneven portions in the interlayer insulating film cause a step coverage failure when forming the upper wiring layer (a printing mistake caused by a step larger than the focal depth on the wafer during pattern exposure using a mask). Problems such as disconnection and defects occur in the wiring layer. For this reason, planarization of the surface of the interlayer insulating film is a necessary technique for realizing a highly reliable multilayer wiring structure.
[0004]
A resin coating method or the like has been used as a typical technique for planarizing a conventional interlayer insulating film, but this method has a problem that sufficient planarization cannot be obtained. In view of this, there has been proposed a method of flattening an interlayer insulating film by generating a flattening pattern (auxiliary pattern) using a CAD technique in a gap portion between wirings.
[0005]
As a flattening pattern generation method using CAD technology, for example, Japanese Patent Laid-Open No. 9-3069 is disclosed.
One disclosed in Japanese Patent No. 96 is known.
[0006]
Hereinafter, a conventional method for generating a flattening pattern will be described with reference to the drawings.
[0007]
FIGS. 4A to 4D and FIGS . 5A to 5C are process diagrams showing a conventional flattening pattern generation method for generating a flattening pattern in the vicinity of a wiring pattern for propagating a signal. .
[0008]
First, to generate a dummy original pattern 1101 shown in Figure 4 (a). Then enlargement processing a wiring pattern 1102 shown in FIG. 4 (b), and generates an enlarged wiring pattern 1103 shown in FIG. 4 (c). Then, by removing the overlapping portion from the dummy source pattern 1101 and enlarged wiring pattern 1103, to generate a dummy pattern 1104 shown in FIG. 4 (d).
[0009]
Then, to remove the small dummy pattern by reducing the dummy pattern 1104 by a predetermined amount, to generate a reduced dummy pattern 1205 shown in Figure 5 (a). Then, the remaining reduced dummy pattern 1205 and enlargement processing by a predetermined amount, generating a flattened pattern 1206 shown in Figure 5 (b). Finally, by combining the planarizing pattern 1206 and the wiring pattern 1102, to generate the final pattern 1207 shown in FIG. 5 (c).
[0010]
In addition, dummy patterns are generated from dummy source patterns obtained by slightly shifting the dummy source patterns 1101 in FIG. 4A vertically and horizontally, and finally the plurality of dummy patterns are combined to increase the area of the planarization pattern. Techniques have also been proposed.
[0011]
[Problems to be solved by the invention]
However, according to the above-described conventional flattening pattern automatic generation method, a flattening pattern is generated by performing a complex mask process after the completion of the wiring process, but this is performed for timing calculation after the pattern generation. Absent.
[0012]
When the timing calculation is performed, it takes time for feedback to consider the increase in wiring capacitance due to the planarization pattern. Furthermore, it is difficult to cope with a case where a timing error is detected after performing timing calculation.
[0013]
Further, since a shape interval of the dummy original pattern 1101 in which simple figures are repeated is necessary, there is a possibility that a pattern satisfying the area ratio cannot be created.
[0014]
The present invention was created in order to solve the above-described problems, and can easily generate flattening pattern information within an automatic placement and routing tool, shorten the flattening pattern information generation processing time, and calculate the timing before timing calculation. It is an object of the present invention to provide a method for automatically generating a flattened pattern that can suppress fluctuations in timing information after pattern information generation by generating flattened pattern information.
[0015]
[Means for Solving the Problems]
The flattening pattern automatic generation method of the present invention includes:
Generates flattened pattern information using an automatic placement and routing tool that has a rewrite processing unit for routed grid information, a maximum dummy pattern creation region shape extraction processing unit, a dummy pattern division processing unit, and a flattening dummy pattern generation processing unit. A method for automatically generating a flattening pattern,
A process of rewriting the wired grid information by recognizing the already wired grid and the unwired grid from the wiring pattern information and the grid information in the wiring area in the wiring layer;
A step of extracting a region including all of the unwired grid as a maximum shape information by an extraction processing unit of a maximum dummy pattern creation region shape;
A dummy pattern division processing unit including a step of performing a shape change to reduce a load capacity to the wiring in the maximum shape information,
The step of generating the flattening pattern information is characterized in that the flattening dummy pattern generation processing unit generates flattening pattern information based on the maximum shape information after the shape change in the step of changing the shape .
[0016]
In the above, the shape change for reducing the load capacity to the wiring is generally to reduce a part of the shape, and a typical example is to form a slit.
[0017]
The operation of the present invention is as follows. That is, in the process of generating the flattening pattern information, a special mask calculation process peculiar to the mask processing tool is not used, and immediately after the wiring process using the placement and routing tool is finished, Since the flattening pattern information is generated in, the flattening pattern information can be easily generated, and the calculation / verification can be performed using the wiring capacitance including the flattening pattern in the subsequent timing calculation. As a result, it is possible to reduce the malfunction rate after manufacturing the LSI. In addition, since the dummy pattern that repeats the simple figure is not divided, the number of flattening patterns and the data amount can be reduced.
[0018]
Furthermore, since the load capacity with the wiring is reduced by changing the shape, for example, by providing a slit instead of using the maximum shape as it is, the influence on the signal delay can be further reduced.
[0019]
In the present invention, in the step of generating the planarization pattern information, a step of obtaining the area ratio including the dummy pattern and collating it with the area ratio rule, or if the area ratio exceeds a predetermined value, It is preferable to include a step of generating a dummy pattern reduced by a predetermined amount and then proceeding to the collation step.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a method for automatically generating a flattening pattern according to the present invention will be described below with reference to the drawings. There are a plurality of mask layers for manufacturing an LSI. In each of the following embodiments, the processing is performed on these mask layers.
[0021]
Hereinafter, a method for automatically generating a flattening pattern according to an embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (d), FIGS. 2 and 3 .
[0022]
First, after grid information is input in step 401, the grid information 101 is initialized as shown in FIG. This initialization is performed by adding unwired grid information 103 (flag “1”). In the grid base wiring tool, the grid interval of the grid information 101 used at this time is usually set to [minimum interval + minimum line width] when using the wiring track information. There is no need to do. However, other than the grid-based wiring tool, it is necessary to consider a separation rule in the next process, and therefore the minimum line interval and the minimum grid on the mask process are set as the grid interval.
[0023]
Next, the initialized grid information and the information of the wiring pattern 102 shown in FIG. 1B are input to the step 402, and the unwired grid information 103 and the already-wired grid information 104 as shown in FIG. Generate. At this time, if the interval between the wiring pattern 102 and the grid does not satisfy the separation rule, the existing wiring grid information 104 is added to the number of grids necessary for satisfying the design rule error at the time of generating the flattening pattern. Do not wake up.
[0024]
Next, in step 403, grid information is input, the maximum shape connecting the areas of the unwired grid information 103 as shown in FIG. 1D is extracted, and the maximum shape information 105 is added to the maximum shape. To do. At this time, since the set unwired grid information 103 has already been added in consideration of the separation rule with the wiring pattern 102, a design rule error will occur if the outermost contour of the area of the unwired grid information 103 is connected. There is nothing.
[0025]
Next, in step 801, in order to reduce the capacitance between the maximum shape information (dummy pattern) 105 of the region and the wiring pattern 102, as shown in FIG. 2, the slit 701 in the vertical direction against the wiring pattern 102 The inserted pattern 702 is generated. This pattern is generated by determining whether or not the area of the maximum shape information (dummy pattern) 105 exists over a plurality of grids in the same direction as the length direction of the wiring pattern. A process of dividing the region of the maximum shape information 105 in the direction perpendicular to the wiring pattern method at intervals or at a plurality of grid intervals is performed to generate slits 701.
[0026]
Next, in step 404, the area ratio in the wiring layer including the wiring shape and the dummy pattern shape as shown in FIG. 2 is calculated.
[0027]
In step 405, whether or not the area ratio rule is satisfied is determined. If the area ratio rule is satisfied, the extracted dummy pattern is directly used as a flattening pattern. The dummy pattern is reduced so as to be reduced.
[0028]
Next, in step 407, LPE processing (resistance / capacitance extraction processing) including a planarization pattern is performed, and timing calculation is performed in step 408 based on the extracted resistance / capacitance information of the wiring.
[0029]
As described above, according to this embodiment, in the step of generating a flattened pattern information, because it does not use a mask process tool-specific special mask operation processing, planarization pattern information on a database of place and route tools Therefore, it is possible to easily generate the flattening pattern information and perform timing calculation / verification based on the capacity information including the flattening pattern, thereby reducing the malfunction rate after manufacturing the LSI. . Further, since the dummy pattern is not divided by repeating simple figures as in the case of the prior art, the number of flattening patterns and the amount of data can be further reduced as compared with the prior art.
[0030]
Further, by providing the slit in the maximum shape, the capacitance between the planarization pattern and the wiring can be reduced, and the influence on the signal delay can be further suppressed.
[0031]
【The invention's effect】
According to the flattening pattern automatic generation method of the present invention, it is possible to generate flattening pattern information with a size and an interval that satisfy the design rule with respect to data before timing verification. Verification in consideration is possible. In addition, since the flattening pattern is generated by deforming the maximum figure for the obtainable region, the number of flattening patterns and the data amount can be reduced.
[0032]
In addition, since the flattened pattern information that satisfies the design rule can be generated before the timing verification, the accuracy of the timing verification can be improved. Furthermore, by deforming the maximum figure and reducing the increase in capacity to the entire wiring, it can be applied to an LSI with relatively strict timing constraints.
[Brief description of the drawings]
FIGS. 1A to 1D are process explanatory views showing each process of a method for automatically generating a flattening pattern according to an embodiment of the present invention.
FIG. 2 is a process explanatory view showing the process of the method for automatically generating a flattening pattern according to the embodiment of the present invention (continuation of FIG. 1D).
FIG. 3 is a flowchart of a method for automatically generating a flattening pattern according to an embodiment of the present invention.
FIGS. 4A to 4D are process explanatory views showing each process of a conventional flattening pattern automatic generation method.
FIGS. 5A to 5C are process explanatory views showing respective steps of a conventional flattening pattern generation method .
[Explanation of symbols]
101 Grid information 102 Wiring pattern 103 Unwired grid information (Grid information initialization value)
104 Already-wired grid information 105 Maximum shape information (dummy pattern)
401 Grid information initialization process 402 Grid information rewrite process 403 Dummy pattern extraction process 404 Area ratio calculation process 405 Area ratio determination process 406 Dummy pattern reduction process 407 Resistance / capacity extraction process 408 Timing calculation process
701 Dummy pattern slit 702 Dummy pattern 801 Dummy pattern division processing

Claims (1)

Generates flattened pattern information using an automatic placement and routing tool that has a rewrite processing unit for routed grid information, a maximum dummy pattern creation region shape extraction processing unit, a dummy pattern division processing unit, and a flattening dummy pattern generation processing unit. A method for automatically generating a flattening pattern,
A process of rewriting the wired grid information by recognizing the already wired grid and the unwired grid from the wiring pattern information and the grid information in the wiring area in the wiring layer;
A step of extracting a region including all of the unwired grid as a maximum shape information by an extraction processing unit of a maximum dummy pattern creation region shape;
A dummy pattern division processing unit including a step of performing a shape change to reduce a load capacity to the wiring in the maximum shape information,
The step of generating the flattening pattern information is characterized in that the flattening dummy pattern generation processing unit generates flattening pattern information based on the maximum shape information after the shape change in the step of changing the shape. Pattern generation method.

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