JP2002366599A - Method for generating flattened pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily generate a flattened pattern in an automatic arrangement wiring tool, to shorten generation processing time of the flattened pattern and to suppress fluctuation of timing information after generation of the pattern. SOLUTION: Unwired grid information 103 and wired grid information 104 are generated from initialized grid information and a wiring pattern 102 after grid information 101 and the wiring pattern 102 are inputted. Next, wired horizontal grid information 201 is added to a wired horizontal grid. The maximum shape including all areas of the unwired grid information 103 including the wired horizontal grid information 201 is extracted and generation candidates for a dummy pattern are created. Next, area ratio is calculated, when the maximum area ratio rule is not satisfied, an area 203 including the wired horizontal grid information 201b is deleted by priority and influence to wiring in timing is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for easily generating a flattening pattern for flattening a wiring layer when a wiring layer formed in a semiconductor integrated circuit such as an LSI is multilayered.

[0002]

2. Description of the Related Art In recent years, multi-layered wiring layers have been used for higher integration of VLSI.

However, when the wiring layers are multi-layered, the uneven portions of the lower wiring pattern are also formed on the upper interlayer insulating film, that is, the interlayer insulating film formed on the wiring layer on which the lower wiring pattern is formed. As a result, irregularities appear in the interlayer insulating film. The uneven portion in the interlayer insulating film causes a step coverage defect (a printing error due to a step having a depth of focus or more on a wafer at the time of pattern exposure using a mask) at the time of forming an upper wiring layer. Problems such as disconnection and failure occur in the wiring layer. Therefore, planarization of the surface of the interlayer insulating film is a technique necessary for realizing a highly reliable multilayer wiring structure.

[0004] A resin coating method or the like has been used as a typical technique for flattening an interlayer insulating film in the past, but this method has a problem that sufficient flattening cannot be obtained. Therefore, a method of flattening an interlayer insulating film by generating a flattening pattern (auxiliary pattern) using a CAD technique in a gap between wirings has been proposed.

As a method of generating a flattening pattern using the CAD technique, for example, a method disclosed in Japanese Patent Application Laid-Open No. 9-306996 is known.

Hereinafter, a conventional method for generating a flattening pattern will be described with reference to the drawings.

FIGS. 11 (a) to 11 (d) and FIG. 12 (a)
(C) is a process diagram showing a conventional flattening pattern generation method for generating a flattening pattern near a wiring pattern for transmitting a signal.

First, a dummy original pattern 1101 shown in FIG. 11A is generated. Next, the wiring pattern 1102 shown in FIG. 11B is enlarged to generate an enlarged wiring pattern 1103 shown in FIG. 11C. Next, a portion overlapping the enlarged wiring pattern 1103 is deleted from the dummy original pattern 1101 to generate a dummy pattern 1104 shown in FIG.

Next, the dummy pattern 1104 is reduced by a predetermined amount to remove a small dummy pattern.
A reduced dummy pattern 1205 shown in FIG.
Then, the remaining reduced dummy pattern 1205 is enlarged by a predetermined amount to obtain a flattening pattern 1 shown in FIG.
Generate 206. Finally, the wiring pattern 1102 and the flattening pattern 1206 are combined to generate the final pattern 1207 shown in FIG.

The dummy original pattern 1 shown in FIG.
A method has also been proposed in which a dummy pattern is generated from a dummy original pattern obtained by slightly shifting 101 from top to bottom and right and left, and a plurality of these dummy patterns are finally combined to increase the area of the flattening pattern.

[0011]

However, according to the above-described flattening pattern generation method according to the prior art, a complicated mask process is performed after the completion of the wiring process to generate a flattening pattern. We did not do this for the calculations.

When performing the timing calculation, it takes a long time for feedback to consider the increase in the wiring capacitance due to the flattening pattern. Furthermore, it is also difficult to cope with a case where a timing error is detected after performing the timing calculation.

Further, since a shape interval of the dummy original pattern 1101 obtained by repeating a simple figure is required, a pattern satisfying the area ratio may not be created.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is possible to easily generate a flattening pattern in an automatic placement and routing tool, to shorten the processing time for generating a flattening pattern, An object of the present invention is to provide a flattening pattern generation method that can suppress timing information fluctuation after pattern generation by generating a flattening pattern.

[0015]

According to a first aspect of the present invention, there is provided a method for generating a flattening pattern, comprising the steps of: identifying a wired grid and an unwired grid from a wiring pattern in a wiring area in a wiring layer and grid information; A step of extracting a maximum shape connecting the unwired grids, and a step of generating a flattening pattern based on the extracted maximum shape.

The operation according to the first invention is as follows. That is, in the step of generating a flattening pattern, a special mask calculation process unique to the mask processing tool is not used, and immediately after the completion of the wiring process using the placement and routing tool, the same placement and routing tool database is used. Since the flattening pattern is generated, the flattening pattern can be easily generated. In the subsequent timing calculation, calculation and calculation are performed using the wiring capacitance including the flattening pattern.
Can be verified. As a result, it is possible to reduce the operation failure rate after the LSI is manufactured. Further, since the division of the dummy pattern in which the simple figure is repeated is not performed, the figure coefficient and data amount of the flattening pattern can be reduced.

In the first invention, in the flattening pattern generating step, the area ratio including the dummy pattern is obtained and compared with the area ratio rule, or the area ratio exceeds a predetermined value. In this case, it is preferable that the method further includes a step of generating a dummy pattern in which the dummy pattern is reduced by a predetermined amount and then proceeding to the above-described collation step.

A flattening pattern generation method according to a second aspect of the present invention includes a step of identifying a wired grid and a non-wired grid from a wiring pattern in a wiring region in a wiring layer and grid information; A step of identifying a horizontal wiring grid based on an unwired grid; a step of extracting a maximum shape connecting the unwired grid and the horizontal wiring grid; and a step of extracting a maximum shape that is more than necessary in the extracted maximum shape. It is characterized by including a step of preferentially deleting from the grid and a step of generating a flattening pattern based on the maximum shape after the deletion processing.

The operation of the second invention is as follows. That is, while exhibiting the same operation as the first invention, the unwired grid includes the wiring horizontal grid with respect to the already-wired grid, and is preferentially deleted from the wiring horizontal grid when the maximum shape does not satisfy the area ratio rule. However, since the flattening pattern is generated based on the maximum shape after the deletion processing, the flattening pattern is generated in a small area in a high wiring density and is generated in a high area in a low wiring density. As a result, the load capacity on the wiring can be reduced rationally, and the effect on the signal delay can be suppressed.

A flattening pattern generation method according to a third aspect of the present invention includes the steps of: identifying a wired grid and an unwired grid from a wiring pattern in a wiring region in a wiring layer and grid information; A step of adding flag information as to whether or not a wiring adjacent grid is used in the wiring pattern; and a step of weighting sequentially from a net with strict timing to a net with extra timing based on timing information of adjacent wiring. Extracting a maximum shape connecting the non-wired grids, a step of preferentially deleting an extracted shape more than necessary in the extracted maximum shape from a wiring adjacent grid of the strict timing net, and after the deletion process, Generating a flattening pattern based on the maximum shape. Regarding the severity of the above timing,
This is called "wiring timing requirement" or "timing tightness".
Also called.

The operation of the third invention is as follows. That is, the same effect as in the first invention is exerted, and when the unwired grid includes not only the wiring horizontal grid with respect to the already-wired grid but also the wiring timing requirement, and the maximum shape does not satisfy the area ratio rule, Is deleted preferentially from the wiring adjacent grid of the severe net, and a flattening pattern is generated based on the maximum shape after the deletion processing. Therefore, the flattening pattern is used in an area where the wiring timing requirement (timing tightness) is high. Are generated in a region where the wiring density is low. As a result, the load capacitance to the wiring can be reduced rationally, and the influence on the signal delay can be further suppressed as compared with the second invention.

A flattening pattern generation method according to a fourth aspect of the present invention includes a step of identifying a wired grid and a non-wired grid from a wiring pattern in a wiring region in a wiring layer and grid information; Extracting a maximum shape connecting the two, and performing a shape change to reduce the load capacitance to the wiring in the extracted maximum shape; and a step of generating a flattening pattern based on the changed shape. I have.

In the above description, changing the shape of the maximum shape to reduce the load capacitance to the wiring generally means reducing a part of the shape, and typically, forming a slit. Can be

The operation of the fourth invention is as follows. That is, the same effect as in the first invention is exhibited, and the load capacity between the wiring and the wiring is reduced by changing the shape, for example, by providing a slit, instead of using the maximum shape as it is. The effect on the delay can be further reduced.

The flattening pattern generation method according to the fifth aspect of the present invention includes a step of adding unwired flag information to all grids before wiring processing, and a wiring path determined when performing processing for determining a path of each wiring. The step of rewriting the grid of the wiring to the already-wired flag, the step of rewriting the grid beside the wiring to the wiring horizontal flag, Performing a capacity extraction in consideration of, and performing a timing calculation based on the extracted capacity information,
A step of restoring the flag information at the time of changing the wiring path, a step of extracting the maximum shape connecting the unwired grids remaining after determining all the wiring paths, and a step of generating a flattening pattern based on the extracted maximum shape. It is characterized by including.

The operation of the fifth invention is as follows. That is, the timing calculation can be performed on the database of the placement and routing tool in consideration of the generation of the flattening pattern during the wiring processing, and the timing information does not fluctuate due to the later generation of the flattening pattern. For this reason, the correction process for satisfying the timing constraint after the flattening pattern is inserted after the wiring becomes unnecessary, and the design period can be significantly shortened.

Further, since a dummy pattern obtained by repeating a simple figure is not divided, the figure coefficient and data amount of a flattened pattern can be reduced.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a flattening pattern generating method according to the present invention will be described below with reference to the drawings. There are a plurality of mask layers for manufacturing an LSI, but in the following embodiments, processing is performed on those mask layers.

(Embodiment 1) Hereinafter, a flattening pattern generation method according to Embodiment 1 of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (d) and the flowchart of FIG.

First, after inputting the grid information in step 401, the grid information 101 is initialized as shown in FIG. This initialization is performed by adding the unwired grid information 103 (flag “1”). In the case of a grid-based wiring tool, when the wiring track information is used, the grid interval of the grid information 101 used at this time is usually set to [minimum interval + minimum line width]. No need to do. However, except for grid-based routing tools,
Since it is necessary to consider the separation rule in the next process, the minimum line interval and the minimum grid in the mask process are set to the grid interval.

Next, the initialized grid information and FIG.
The wiring pattern 102 shown in (b) is input to step 402, and the non-wiring grid information 10 as shown in FIG.
3 and the already-wired grid information 104 are generated. At this time,
When the spacing between the wiring pattern 102 and the grid does not satisfy the separation rule, the design rule error does not occur when the flattening pattern is generated by adding the already-wiring grid information 104 to the number of grids required to satisfy the separation rule. To do.

Next, grid information is input to step 403, and the unwired grid information 1 as shown in FIG.
The maximum shape connecting the areas 03 is extracted, and the maximum shape information 105 is added to the maximum shape. At this time, the set non-wiring grid information 103 already has the wiring pattern 1
Since the separation rule is added in consideration of the separation rule of 02, the design rule error does not occur if the outermost lines of the area of the unwired grid information 103 are connected.

Next, in step 404, FIG.
The area ratio in the wiring layer including the wiring shape and the dummy pattern shape as shown in (d) is calculated.

At step 405, it is determined whether or not the area ratio rule is satisfied. If the rule is satisfied, the extracted dummy pattern is used as a flattened pattern as it is. The dummy pattern is reduced so that the area of the dummy pattern is reduced.

Next, in step 407, LPE processing (resistance / capacity extraction processing) including the flattening pattern is performed, and timing calculation is performed in step 408 based on the extracted wiring resistance / capacity information.

As described above, according to the first embodiment, in the step of generating a flattening pattern, a special mask calculation process unique to a mask processing tool is not used.
Since the flattening pattern is generated on the database of the placement and routing tool, the flattening pattern can be easily generated, and the timing calculation and verification can be performed based on the capacitance information including the flattening pattern. An operation failure rate can be reduced. In addition, since the division of the dummy pattern in which the simple figure is repeated as in the case of the related art is not performed, the figure coefficient and the data amount of the flattening pattern can be further reduced as compared with the related art.

(Embodiment 2) Hereinafter, a flattening pattern generation method according to Embodiment 2 of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (c), FIGS. 2 (a) and (b), and the flowchart of FIG.

FIG. 5 is the same as FIG. 4 of the first embodiment, except that the wiring horizontal grid information is rewritten in step 501.
And step 50 of using the wiring horizontal grid information
2,503 is added. FIG.
The same processes as those described above are denoted by the same reference numerals.

In the second embodiment, step 40
2 is the same as that of the first embodiment up to the rewriting process of the wired grid information, and the information rewriting of FIGS. 1A to 1C is performed.

Next, in step 501, the non-wiring grid information 103 is added to add wiring horizontal grid information 201 (flag "2") indicating the wiring horizontal grid.
(Flag “1”) is a portion adjacent to the area of the existing wiring grid information 104 (flag “0”) or grid information corresponding to the wiring width from the adjacent portion.
As (flag "2"), the grid information is rewritten as shown in FIG.

Next, the grid information is input to step 403, and the unwired grid information 1 as shown in FIG.
The maximum shape connecting the area 03 and the area of the wiring horizontal grid information 201 is extracted, and the maximum shape information 105 is added to the maximum shape.

Next, at step 404, FIG.
The area ratio in the wiring layer including the wiring shape and the dummy pattern shape as shown in FIG.

Then, in step 405, it is determined whether or not the area ratio rule is satisfied. If the area ratio rule is satisfied, the extracted dummy pattern is used as it is as a flattening pattern. The dummy pattern is reduced so that the area of the dummy pattern is reduced.

Here, in the area reduction processing of step 502, first, the area 203 including only the wiring horizontal grid information 201
Is calculated, and if the area ratio exceeds a predetermined value, only the region 203 is deleted. If the area ratio is exceeded, a region consisting of the wiring horizontal grid information 201 and the non-wiring grid information 103 is calculated. The area of the region 204 is calculated if the area ratio exceeds a predetermined value.
4 are sequentially deleted, and the deletion process ends when the maximum area ratio is satisfied.

Next, in step 503, the area ratio is determined again. If the area is satisfied, the extracted dummy pattern is used as a flattened pattern. If the area is not satisfied, the excess area is reduced in step 406. The dummy pattern is reduced as described above.

The subsequent steps 407 and 408 are the same as in the first embodiment.

As described above, according to the second embodiment, in the step of generating a flattening pattern, a special mask calculation process unique to a mask processing tool is not used.
Since the flattening pattern is generated on the database of the placement and routing tool, the flattening pattern can be easily generated, and the timing calculation and verification can be performed based on the capacitance information including the flattening pattern. An operation failure rate can be reduced.

Since the division of the dummy pattern in which the simple figure is repeated as in the case of the prior art is not performed,
The figure coefficient and data amount of the flattening pattern can be further reduced than before.

Further, since a flattening pattern is generated in a region having a high wiring density and a large amount in a region having a low wiring density, the influence on the signal delay can be suppressed lower than that in the first embodiment.

(Embodiment 3) Hereinafter, a flattening pattern generation method according to Embodiment 3 of the present invention will be described with reference to FIG.
This will be described with reference to the flowcharts of FIGS. 3A to 3C, FIGS. 3A and 3B, and FIG.

FIG. 6 is different from FIG. 4 of the first embodiment in that a step 601 of rewriting wiring horizontal grid information in consideration of timing information and steps 602 and 603 using wiring horizontal grid information are added. Is equivalent to something. Note that the same processes as those in FIG. 4 are denoted by the same reference numerals.

In the third embodiment, step 40
2 is the same as that of the first embodiment up to the rewriting process of the wired grid information, and the information rewriting of FIGS. 1A to 1C is performed.

Next, at step 601, grid information (flags "2" to "5") indicating the timing tightness (wiring timing requirement) of a signal passing through the adjacent wiring is added to the horizontal wiring grid. , Already-wired grid information 1 of unwired grid information 103 (flag “1”)
04 (the flag “0”) or the grid information corresponding to the wiring width from the adjacent part to the timing tightness information 301 to 304 of the adjacent wiring (flag “2” to
As “5”), the grid information is rewritten as shown in FIG.

FIG. 3A shows that the wiring adjacent to the wiring pattern 102 is the wiring with the strictest timing (the highest level of wiring timing requirement) and the timing tightness information 304 (flag “5”) is added. Hereinafter, the state in which the timing constraint is loosened is shown in order. Timing tightness information 303 (flag “4”) → 302 (flag “3”) → 301 (flag “2”).

Next, grid information is input to step 403, and the unwired grid information 1 as shown in FIG.
03 area and timing tightness information 301 to 304
The maximum shape information 305 connecting the regions is extracted.

Next, in step 404, FIG.
The area ratio in the wiring layer including the wiring shape and the dummy pattern shape as shown in FIG.

Then, in step 405, it is determined whether or not the area ratio rule is satisfied. If the area ratio rule is satisfied, the extracted dummy pattern is used as a flattened pattern as it is. The dummy pattern is reduced so that the area of the dummy pattern is reduced.

Here, in the area reduction processing in step 602, first, the area of the region 306 indicated by the timing tightness information 304, 303 indicating that the timing tightness of the adjacent wiring is the severest is calculated, and the area ratio becomes a predetermined value. If so, delete only that area. Further, when the area ratio exceeds a predetermined value, the area is calculated for a region 307 including the timing tightness information 304 indicating that the timing tightness is severe and the non-wired grid information 103, and the area ratio is changed to the predetermined value. A process is performed to determine whether the number has exceeded the limit. Hereinafter, similarly, the processing is sequentially performed on the areas 308, 309, and 310 from the side where the timing tightness information is severe to the side where the timing tightness information is loose.

When the area ratio rule is satisfied in the course of sequentially reducing the area of the dummy pattern, the plurality of divided regions 310 in the class belonging to the class to be reduced are sequentially deleted. The deletion process ends when the maximum area ratio is satisfied.

Next, in step 503, the area ratio is determined again. If the area ratio is satisfied, the extracted dummy pattern is used as a flattened pattern as it is. If not, the dummy pattern is reduced in step 406 so that the excess area is reduced.

The subsequent steps 407 and 408 are the same as in the first embodiment.

As described above, according to the third embodiment, in the step of generating a flattening pattern, a special mask calculation process unique to a mask processing tool is not used.
Since the flattening pattern is generated on the database of the placement and routing tool, the flattening pattern can be easily generated, and the timing calculation and verification can be performed based on the capacitance information including the flattening pattern. An operation failure rate can be reduced.

Since the division of the dummy pattern in which the simple figure is repeated as in the case of the prior art is not performed,
The figure coefficient and data amount of the flattening pattern can be further reduced than before.

Further, the flattening pattern is reduced so that the presence of the flattening pattern is reduced in a portion adjacent to the wiring with high timing tightness, and the flattening pattern is increased in the vicinity of the wiring with low timing tightness. Since the modified pattern is generated, the influence on the signal delay can be further reduced than in the second embodiment.

(Embodiment 4) A flattening pattern generation method according to Embodiment 4 of the present invention will be described with reference to FIG.
A description will be given with reference to the flowcharts of (a) to (d), FIG. 7 (a) and FIG.

FIG. 8 corresponds to FIG. 4 of the first embodiment in which a step 801 of changing (dividing) the extracted shape is added after step 403 of extracting the maximum dummy pattern. Note that the same processes as those in FIG. 4 are denoted by the same reference numerals.

In the fourth embodiment, step 40
The processing up to the process of extracting the maximum dummy pattern No. 3 is the same as that of the first embodiment, and the information rewriting of FIGS. 1A to 1D is performed.

Next, in step 801, the area of the maximum shape information (dummy pattern) 105 and the wiring pattern 1
In order to reduce the capacitance between the wiring pattern 102 and the wiring pattern 102, a pattern 702 in which a slit 701 is formed in a direction perpendicular to the wiring pattern 102 is generated, as shown in FIG. This pattern is generated by determining whether or not the area of the maximum shape information (dummy pattern) 105 is present over a plurality of grids in the same direction as the length direction of the wiring pattern. A process of dividing the area of the maximum shape information 105 at intervals or a plurality of grid intervals in the vertical direction with respect to the wiring pattern method is performed, and a slit 701 is generated.

The subsequent steps 405 to 408 are the same as in the first embodiment.

As described above, according to the fourth embodiment, in the step of generating a flattening pattern, a special mask calculation process unique to a mask processing tool is not used.
Since the flattening pattern is generated on the database of the placement and routing tool, the flattening pattern can be easily generated, and the timing calculation and verification can be performed based on the capacitance information including the flattening pattern. An operation failure rate can be reduced.

Further, since a dummy pattern in which a simple figure is repeated as in the case of the prior art is not divided,
The figure coefficient and data amount of the flattening pattern can be further reduced than before.

Further, by providing the slit in the maximum shape, the capacitance between the flattening pattern and the wiring can be reduced, and the influence on the signal delay can be suppressed even lower than in the first embodiment.

The method of dividing the flattening pattern in the fourth embodiment can be applied not only to the first embodiment but also to the flattening patterns generated in the second and third embodiments. Therefore, the wiring capacitance can be further reduced as compared with the respective methods.

(Embodiment 5) Hereinafter, a flattening pattern generation method according to Embodiment 5 of the present invention will be described with reference to FIG.
This will be described with reference to (a), the flowchart of FIG. 9, and FIGS. 10 (a) to (d).

First, after inputting the grid information in step 401, the grid information 101 is initialized as shown in FIG. In the case of a grid-based wiring tool, the grid interval of the grid information 101 used at this time is usually determined by using wiring track information.
Since [minimum interval + minimum line width] is set, there is no need to consider separation rules. However, other than the grid-based wiring tool, it is necessary to consider the separation rule in the next process, so the minimum line interval and the minimum grid in the mask processing are set to the grid interval.

Next, in the wiring processing of step 901, wiring of a wiring pattern 1001 as shown in FIG.

Next, in the grid information rewriting process in step 902, as shown in FIG. 10B, a grid adjacent to the wiring pattern 1001 generated in step 901 or a grid region having a width satisfying the separation rule is determined. Is rewritten to grid information 1002 (flag “2”) indicating the horizontal wiring pattern.

Next, in step 903, LPE processing (resistance / capacity extraction processing) is performed in consideration of the presence of a pattern in the wiring horizontal grid information 1002, and timing calculation is performed in step 904 based on this information.

Next, in step 905, it is determined whether or not all the wiring processes have been completed. If there is an unwiring pattern, the wiring process in step 901 is repeated.
For example, as shown in FIG.
03 is considered as the next wiring route, FIG.
Timing calculation is performed based on the LPE information in consideration of the generation of the dummy pattern 1004 in (c), and if the timing constraint is satisfied, the wiring pattern is determined as shown in FIG. The rewriting process of the grid information is performed to obtain grid information 1005.

After this process is repeated and all the wiring processes are completed, the same processes as those of the first embodiment after step 403 are performed.

As described above, according to the fifth embodiment, the timing calculation can be performed on the database of the placement and routing tool in consideration of the generation of the flattening pattern during the wiring process. The timing information does not fluctuate due to the generation of the timing information. For this reason, the correction process for satisfying the timing constraint after the flattening pattern is inserted after the wiring becomes unnecessary, and the dramatic design period can be shortened.

Since the division of the dummy pattern in which the simple figure is repeated as in the case of the prior art is not performed,
The figure coefficient and data amount of the flattening pattern can be further reduced than before.

[0083]

According to the first flattening pattern generation method, it is possible to generate a flattening pattern at a size and an interval satisfying a design rule for data before timing verification. Verification in consideration of an increase in capacity becomes possible. In addition, since a flattening pattern is generated with a maximum figure for an obtainable area, the number of flattening patterns and the amount of data can be reduced.

According to the second flattening pattern generation method,
As in the case of the first flattening pattern generation method, a flattening pattern that satisfies the design rule can be generated before timing verification, so that the accuracy of timing verification can be improved. Patterns can be reduced in a manner that reduces the increase. As a result, the present invention can be applied to an LSI having relatively strict timing constraints. Further, the data amount of the flattening pattern can be reduced as in the first flattening pattern generation method.

According to the third flattening pattern generation method,
Similar to the first flattening pattern generation method, a flattening pattern that satisfies the design rule can be generated before the timing verification, so that the accuracy of the timing verification can be improved. Furthermore, when the maximum area ratio is exceeded, the pattern can be reduced in a form that effectively reduces the increase in the capacity of the wiring with strict timing constraints, thereby making it applicable to LSIs with strict timing constraints. Become. Further, the data amount of the flattening pattern can be reduced as in the first flattening pattern generation method.

According to the fourth flattening pattern generation method,
Similar to the first flattening pattern generation method, a flattening pattern that satisfies the design rule can be generated before timing verification, so that the accuracy of timing verification can be improved. Further, as a flattening pattern generation shape, a shape in which a load capacitance is not easily attached to the wiring is generated, and the pattern can be reduced in a form in which an increase in the capacitance of the entire wiring is reduced.
As a result, the present invention can be applied to an LSI having relatively strict timing constraints.

According to the fifth flattening pattern generation method,
Capacitance calculation considering the generation of a flattening pattern can be performed during the wiring process by the wiring tool, and the problem of timing violation occurring due to an increase in load capacitance due to the generation of the flattening pattern after completion of wiring can be avoided. Repair man-hours after a violation can be greatly reduced. Also, in order to generate a flattening pattern with the largest figure for the area that can be obtained,
The number of flattening patterns and the amount of data can be reduced.

[Brief description of the drawings]

FIGS. 1A to 1D are process explanatory diagrams showing each process of a flattening pattern generation method according to a first embodiment of the present invention.

FIGS. 2A and 2B are process explanatory diagrams showing each process of a flattening pattern generation method according to a second embodiment of the present invention.

FIGS. 3 (a) and 3 (b) are plan views showing steps of a method for generating a flattening pattern according to Embodiment 3 of the present invention.

FIG. 4 is a flowchart of a flattening pattern generation method according to the first embodiment of the present invention;

FIG. 5 is a flowchart of a flattening pattern generation method according to a second embodiment of the present invention.

FIG. 6 is a flowchart of a flattening pattern generation method according to a third embodiment of the present invention.

FIG. 7 is a process explanatory view showing each process of a flattening pattern generation method according to a fourth embodiment of the present invention.

FIG. 8 is a flowchart of a flattening pattern generation method according to a fourth embodiment of the present invention.

FIG. 9 is a flowchart of a flattening pattern generation method according to a fifth embodiment of the present invention.

FIG. 10 is a process explanatory diagram showing each process of a flattening pattern generation method according to a fifth embodiment of the present invention.

FIGS. 11A to 11D are process explanatory diagrams showing each process of a conventional flattening pattern generation method.

FIGS. 12A to 12C are process explanatory diagrams showing each process of a conventional flattening pattern generation method.

[Explanation of symbols]

 101 Grid information 102 Wiring pattern 103 Unwired grid information (grid information initialization value) 104 Existing wiring grid information 105 Maximum shape information (dummy pattern) 201 Wiring horizontal grid information 202 Maximum shape information 203 Area consisting only of wiring horizontal grid 204 Not yet Wiring / wiring horizontal grid mixed area 301 Timing tightness information 302 Timing tightness information 303 Timing tightness information 304 Timing tightness information 306 Wiring horizontal horizontal grid area 307 Wiring horizontal horizontal grid area 308 Wiring horizontal horizontal grid area 309 Wiring horizontal horizontal grid Area 401 Grid information initialization processing 402 Grid information rewriting processing 403 Dummy pattern extraction processing 404 Area ratio calculation processing 405 Area ratio discrimination processing 406 Dummy pattern reduction processing 407 Resistance / volume Extraction processing 408 Timing calculation processing 501 Wiring horizontal grid information rewriting processing 502 Dummy pattern deletion processing 503 Area ratio discrimination processing 601 Wiring horizontal grid information rewriting processing 602 Dummy pattern deletion processing 603 Area ratio discrimination processing 701 Dummy pattern slit 702 Dummy pattern 801 Dummy pattern Division processing 901 Wiring processing 902 Wiring horizontal grid information rewriting processing 903 Resistance / capacity extraction processing 904 Timing calculation processing 905 Wiring processing determination processing

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Claims (5)

[Claims] A step of identifying a wired grid and a non-wired grid from a wiring pattern and grid information in a wiring region in a wiring layer; and extracting a maximum shape connecting the unwired grids. Generating a flattening pattern based on the determined maximum shape. 2. A step of identifying a wired grid and an unwired grid from a wiring pattern and grid information in a wiring area in a wiring layer, and identifying a wiring horizontal grid based on the wired grid and the unwired grid. Extracting a maximum shape connecting the unwired grid and the horizontal wiring grid; and preferentially deleting from the wiring horizontal grid an extracted shape that is more than necessary in the extracted maximum shape; Generating a flattening pattern based on the maximum shape after the deletion processing. 3. A step of distinguishing between a wired grid and an unwired grid from a wiring pattern in a wiring area and grid information in a wiring layer, and whether a wiring adjacent grid is used in the wiring pattern for the unwired grid. A step of adding flag information of whether or not, and a step of sequentially weighting from a net with strict timing to a net with extra timing based on timing information of adjacent wiring, and a maximum shape connecting the non-wiring grids with each other. An extracting step, a step of preferentially deleting an extracted shape more than necessary in the extracted maximum shape from a wiring adjacent grid of the strict timing net, and generating a flattening pattern based on the maximum shape after the deleting process. And a method for generating a flattening pattern. 4. A step of discriminating between a wired grid and an unwired grid from a wiring pattern and grid information in a wiring area in a wiring layer, and a step of extracting a maximum shape connecting the unwired grids. A flattening pattern generation method, comprising: a step of performing a shape change to reduce a load capacitance to a wiring in the maximum shape thus formed; and a step of generating a flattening pattern based on the changed shape. 5. A step of adding non-wiring flag information to all grids before the wiring processing, a step of rewriting a grid of a wiring path determined at the time of performing a processing of determining a path of each wiring to an already-wiring flag, A step of rewriting a grid next to the wiring to a horizontal wiring flag; and a step of performing a capacitance extraction in consideration of the presence of a flattening pattern by the flag information when calculating capacitance information used for timing calculation when considering the wiring path; Performing a timing calculation based on the obtained capacitance information, restoring the flag information when the wiring route is changed, and extracting the maximum shape connecting the unwired grids remaining after determining all the wiring routes. Generating a flattening pattern based on the maximum shape.