JP4004511B2 - Automatic flattening pattern generation method - Google Patents

Description

  The present invention relates to a method for easily generating a flattening pattern for flattening a wiring layer when a wiring layer formed in a semiconductor integrated circuit such as an LSI is multilayered.

  In recent years, wiring layers have been multilayered for high integration of VLSI.

  However, when the wiring layer is multi-layered, the uneven portion of the lower wiring pattern also affects the upper interlayer insulating film, that is, the interlayer insulating film formed on the wiring layer on which the lower wiring pattern is formed. Therefore, irregularities also appear in the interlayer insulating film. The uneven portions in the interlayer insulating film cause a step coverage failure when forming the upper wiring layer (a printing mistake caused by a step larger than the focal depth on the wafer during pattern exposure using a mask). Problems such as disconnection and defects occur in the wiring layer. For this reason, planarization of the surface of the interlayer insulating film is a necessary technique for realizing a highly reliable multilayer wiring structure.

  A resin coating method or the like has been used as a typical technique for planarizing a conventional interlayer insulating film, but this method has a problem that sufficient planarization cannot be obtained. In view of this, there has been proposed a method of flattening an interlayer insulating film by generating a flattening pattern (auxiliary pattern) using a CAD technique in a gap portion between wirings.

  As a method for generating a flattening pattern using CAD technology, for example, a method disclosed in Japanese Patent Laid-Open No. 9-306996 is known.

  Hereinafter, a conventional method for generating a flattening pattern will be described with reference to the drawings.

  9 (a) to 9 (d) and FIGS. 10 (a) to 10 (c) are process diagrams showing a conventional flattening pattern generation method for generating a flattening pattern in the vicinity of a wiring pattern for propagating a signal. .

  First, the dummy original pattern 1101 shown in FIG. 9A is generated. Next, the wiring pattern 1102 shown in FIG. 9B is enlarged to generate an enlarged wiring pattern 1103 shown in FIG. 9C. Next, a portion overlapping the enlarged wiring pattern 1103 is deleted from the dummy original pattern 1101 to generate a dummy pattern 1104 shown in FIG.

  Next, the dummy pattern 1104 is reduced by a predetermined amount to remove the small dummy pattern, thereby generating a reduced dummy pattern 1205 shown in FIG. Then, the remaining reduced dummy pattern 1205 is enlarged by a predetermined amount to generate a flattened pattern 1206 shown in FIG. Finally, the wiring pattern 1102 and the planarization pattern 1206 are synthesized to generate a final pattern 1207 shown in FIG.

Further, the dummy pattern is generated from dummy source patterns obtained by shifting the dummy source pattern 1101 of FIG. 9A little by little up and down, left and right, and finally the plurality of dummy patterns are combined to increase the area of the planarization pattern. Techniques have also been proposed.
Japanese Patent Laid-Open No. 9-306996

  However, according to the above-described conventional flattening pattern automatic generation method, a flattening pattern is generated by performing a complex mask process after the completion of the wiring process, but this is performed for timing calculation after the pattern generation. Absent.

  When the timing calculation is performed, it takes time for feedback to consider the increase in wiring capacitance due to the planarization pattern. Furthermore, it is difficult to cope with a case where a timing error is detected after performing timing calculation.

  Further, since a shape interval of the dummy original pattern 1101 in which simple figures are repeated is necessary, there is a possibility that a pattern satisfying the area ratio cannot be created.

  The present invention was created in order to solve the above-described problems, and can easily generate flattening pattern information within an automatic placement and routing tool, shorten the flattening pattern information generation processing time, and calculate the timing before timing calculation. It is an object of the present invention to provide a method for automatically generating a flattened pattern that can suppress fluctuations in timing information after pattern information generation by generating flattened pattern information.

The flattening pattern automatic generation method of the first invention of the present application is:
For the database in the automatic place and route tool,
A step of discriminating between the existing wiring grid and the non-wiring grid from the wiring pattern information in the wiring area in the wiring layer and the grid information;
Extracting a region including all of the unwired grid as a maximum shape, and obtaining maximum shape information corresponding to the maximum shape;
Identifying the unwired grid adjacent to the already-routed grid as the wire-adjacent grid based on the already-wired grid and the unwired grid, and obtaining the wire-adjacent grid information corresponding to the wire-adjacent grid; and
In that it comprises a step of generating a flattened pattern information based on the maximum shape information to remove the wiring adjacent grids indicated by the lines adjacent grid information from said maximum shape shown is, the shape information corresponding to the shape of the removed result It is a feature.

  The operation of the first invention is as follows. That is, in the process of generating the flattening pattern information, a special mask calculation process peculiar to the mask processing tool is not used, and immediately after the wiring process using the placement and routing tool is finished, Since the flattening pattern is generated in FIG. 2, the flattening pattern can be easily generated, and the calculation and verification can be performed using the wiring capacitance including the flattening pattern in the subsequent timing calculation. As a result, it is possible to reduce the malfunction rate after manufacturing the LSI. In addition, since the dummy pattern that repeats the simple figure is not divided, the number of flattening patterns and the data amount can be reduced.

  In the first aspect of the invention, in the step of generating the flattening pattern information, a step of obtaining an area ratio including the dummy pattern having the maximum shape and collating with the area ratio rule, or the area ratio exceeds a predetermined value. In this case, it is preferable to include a step of generating a dummy pattern obtained by reducing the dummy pattern by a predetermined amount and then proceeding to the collating step.

When the maximum shape does not satisfy the area ratio rule, the wiring adjacent grid is deleted from the maximum shape, and a flattening pattern is generated based on the shape information corresponding to the deleted shape. As a result, the load capacity on the wiring can be reduced and the influence on the signal delay can be kept low. It can also be applied to LSIs with relatively strict timing constraints.

  In the above, when the wiring adjacent grid is deleted from the maximum shape in the step of generating the planarization pattern information, priority is given to the wiring adjacent grid in the dense area in the density of the existing wiring grid indicated by the wiring adjacent grid information. There is a mode to delete. In this case, the flattening pattern is generated in a small area in a high wiring density and in a large area in a low wiring density. As a result, the load capacity on the wiring can be rationally reduced, and the influence on the signal delay can be kept low.

The flattening pattern automatic generation method of the second invention of the present application is the above first invention,
Based on the already-wired grid and the unwired grid, an unwired grid adjacent to the already-wired grid is identified as a wire adjacent grid, and the wire adjacent to the wire adjacent grid among the unwired grids The method further includes a step of obtaining grid information including timing tightness by adding information indicating timing tightness,
In the step of generating the planarization pattern information, the wiring adjacent grids having higher timing tightness indicated by the grid information including the timing tightness are preferentially deleted from the maximum shape indicated by the maximum shape information, and the deletion is performed. The flattening pattern information is generated based on the resulting shape information. The timing tightness refers to the severity of timing conditions and is also referred to as a wiring timing requirement.

The operation of the second invention is as follows. That is, while exhibiting the same effect as the first aspect of the invention, when the maximum shape does not satisfy the area ratio rule, the wiring adjacent grid with higher timing tightness is deleted preferentially from the maximum shape, and the shape of the deletion result A flattening pattern is generated based on the shape information corresponding to. Therefore, the flattening pattern is generated in a small area in a high timing tightness area and a large number in a low timing tightness area. As a result, the load capacity on the wiring can be rationally reduced, and the influence on the signal delay can be further reduced as compared with the first invention.

  According to the present invention, it is possible to generate a flattening pattern with a size and an interval that satisfy a design rule with respect to data before timing verification, and at the time of timing verification, it is possible to perform verification considering the increase in capacity due to the flattening pattern. . In addition, since the flattening pattern is generated with the maximum figure for the obtainable region, the number of flattening patterns and the data amount can be reduced.

  Embodiments of a method for automatically generating a flattening pattern according to the present invention will be described below with reference to the drawings. There are a plurality of mask layers for manufacturing an LSI. In each of the following embodiments, the processing is performed on these mask layers.

(Embodiment 1)
Hereinafter, a method for automatically generating a flattening pattern according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1D and the flowchart of FIG.

  First, after grid information is input in step 401, the grid information 101 is initialized as shown in FIG. This initialization is performed by adding unwired grid information 103 (flag “1”). In the grid base wiring tool, the grid interval of the grid information 101 used at this time is usually set to [minimum interval + minimum line width] when using the wiring track information. There is no need to do. However, other than the grid-based wiring tool, it is necessary to consider a separation rule in the next process, and therefore the minimum line interval and the minimum grid on the mask process are set as the grid interval.

  Next, the initialized grid information and the wiring pattern information 102 shown in FIG. 1B are input to the step 402, and the unwired grid information 103 and the already-wired grid information 104 as shown in FIG. 1C are generated. To do. At this time, if the interval between the wiring pattern information 102 and the grid does not satisfy the separation rule, the existing wiring grid information 104 is added to the number of grids necessary to satisfy the separation rule, so that the design is performed when the flattening pattern information is generated. Avoid rule errors.

  Next, in step 403, grid information is input, the maximum shape connecting the areas of the unwired grid information 103 as shown in FIG. 1D is extracted, and the maximum shape information 105 is added to the maximum shape. To do. At this time, since the set unwired grid information 103 has already been added in consideration of the separation rule with the wiring pattern information 102, a design rule error can be generated by connecting the outermost area of the unwired grid information 103 area. It will not wake up.

  Next, in step 404, the area ratio in the wiring layer including the wiring shape as shown in FIG. 1D and the dummy pattern having the maximum shape is calculated.

  In step 405, whether or not the area ratio rule is satisfied is determined. If the area ratio rule is satisfied, the extracted dummy pattern is directly used as a flattening pattern. The dummy pattern is reduced so as to be reduced.

  Next, in step 407, LPE processing (resistance / capacitance extraction processing) including a planarization pattern is performed, and timing calculation is performed in step 408 based on the extracted resistance / capacitance information of the wiring.

  As described above, according to the first embodiment, in the step of generating the flattening pattern information, a special mask calculation process unique to the mask processing tool is not used, and the flattening pattern is displayed on the placement and routing tool database. Since it produces | generates, a planarization pattern can be produced | generated easily. In addition, since the timing calculation / verification can be performed based on the capacity information including the flattening pattern, the operation failure rate after the LSI manufacturing can be reduced. Further, since the dummy pattern is not divided by repeating simple figures as in the case of the prior art, the number of flattening patterns and the amount of data can be further reduced as compared with the prior art.

(Embodiment 2)
Hereinafter, an automatic flattening pattern generation method according to the second embodiment of the present invention will be described with reference to FIGS. 1A to 1C, FIGS. 2A and 2B, and the flowchart of FIG. .

  FIG. 5 corresponds to FIG. 4 of the first embodiment in which step 501 for rewriting the wiring adjacent grid information 201 and steps 502 and 503 using the wiring adjacent grid information 201 are added. Yes. In addition, the same code | symbol is attached | subjected to the process similar to FIG.

  In the second embodiment, the processing up to rewriting of the existing wiring grid information 104 in step 402 is the same as that in the first embodiment, and the information rewriting shown in FIGS. 1A to 1C is performed.

  Next, in step 501, in order to add the wiring adjacent grid information 201 (flag “2”) indicating the wiring adjacent grid which is a grid adjacent to the wiring pattern, it corresponds to the unwired grid information 103 (flag “1”). The grid information of the grid adjacent to the area of the existing wiring grid information 104 (flag “0”) (or the grid corresponding to the wiring width from the adjacent grid) is used as the wiring adjacent grid information 201 (flag “2”). The grid information is rewritten as shown in FIG.

  Next, in step 403, grid information is input to extract the maximum shape connecting the unwired grid information 103 area and the wiring adjacent grid information 201 area as shown in FIG. The maximum shape information 105 is added.

  Next, in step 404, the area ratio in the wiring layer including the wiring shape as shown in FIG. 2B and the dummy pattern having the maximum shape is calculated.

  In step 405, whether or not the area ratio rule is satisfied is determined. If the area ratio rule is satisfied, the extracted dummy pattern is used as a flattened pattern as it is. If not, in step 502, the excess area is determined. The dummy pattern is reduced so as to be reduced.

  Here, in the area reduction process of step 502, first, the area of the region 203 (region connecting the flags “2”-“2”) consisting only of the wiring adjacent grid information 201 is calculated, and the area ratio exceeds the predetermined value. For example, if only the area 203 consisting only of the wiring adjacent grid information 201 is deleted and the area ratio is exceeded, the area 204 consisting of the wiring adjacent grid information 201 and the unwired grid information 103 (flag “2” − The area of the area connecting “1” is calculated. The area 204 composed of the wiring adjacent grid information 201 and the unwired grid information 103 is normally divided into a plurality of parts. If the area ratio obtained by the above calculation exceeds a predetermined value, one divided region 204 is deleted.

  Next, an area ratio determination process is performed in step 503. If the area ratio is satisfied, the extracted dummy pattern is used as a flattening pattern as it is. If not, the area is determined to be reduced so that the excess area is reduced in step 406. Perform pattern reduction processing. Further, the area ratio is determined, and the divided areas 204 are sequentially deleted one by one until the area ratio is satisfied. When the maximum area ratio is satisfied, the deletion process is terminated.

  The subsequent steps 407 and 408 are the same as those in the first embodiment.

  As described above, according to the second embodiment, in the step of generating the flattening pattern information, a special mask calculation process unique to the mask processing tool is not used, and the flattening pattern is displayed on the placement and routing tool database. Since it produces | generates, a planarization pattern can be produced | generated easily. In addition, since the timing calculation / verification can be performed based on the capacity information including the flattening pattern, the operation failure rate after the LSI manufacturing can be reduced.

  Further, since the dummy pattern is not divided by repeating simple figures as in the case of the prior art, the number of flattening patterns and the amount of data can be further reduced as compared with the prior art.

  Further, since the flattening pattern information is generated so that the flattening pattern is small in the region where the wiring density is high and the flattening pattern is large in the region where the wiring density is low, the influence on the signal delay is lower than that in the first embodiment. Can be suppressed.

(Embodiment 3)
Hereinafter, a method for automatically generating a flattening pattern according to the third embodiment of the present invention will be described with reference to FIGS. 1A to 1C, FIGS. 3A and 3B, and the flowchart of FIG. .

  FIG. 6 corresponds to FIG. 4 of the first embodiment described above in which step 601 for rewriting wiring adjacent grid information considering timing information and steps 602 and 603 using wiring adjacent grid information are added. is doing. In addition, the same code | symbol is attached | subjected to the process similar to FIG.

  In the third embodiment, the process up to the rewriting process of the existing wiring grid information 104 in step 402 is the same as that in the first embodiment, and the information rewriting shown in FIGS.

  Next, in step 601, in order to add information (flags “2” to “5”) indicating the timing tightness (wiring timing requirement degree) of a signal passing through the wiring adjacent to the wiring adjacent grid, Of the grid corresponding to the unwired grid information 103 (flag “1”), the grid information of the grid adjacent to the area of the already wired grid information 104 (flag “0”) (or the grid corresponding to the wiring width from the adjacent grid) is displayed. The grid information as shown in FIG. 3A is rewritten as the timing tightness information 301 to 304 (flags “2” to “5”) of the adjacent wiring.

  In FIG. 3A, the region adjacent to the wiring pattern indicated by the wiring pattern information 102 is set to the region with the most severe timing (the highest degree of wiring timing requirement), and timing tightness information 304 (flag “5”) is added. In the following, the state where the timing constraints are gradually relaxed is shown. Timing tightness information 303 (flag “4”) → 302 (flag “3”) → 301 (flag “2”).

  Next, the grid information is input to step 403, and the maximum shape connecting the area of the unwired grid information 103 and the area of the timing tightness information 301 to 304 as shown in FIG. Maximum shape information 305 is added to the shape.

  Next, in step 404, the area ratio in the wiring layer including the wiring pattern as shown in FIG. 3B and the dummy pattern having the maximum shape is calculated.

  Then, in step 405, a process for determining whether or not the area ratio rule is satisfied is performed. If the area ratio rule is satisfied, the extracted dummy pattern is used as a flattening pattern as it is. The dummy pattern is reduced so as to be reduced.

  Here, in the area reduction process of step 602, first, the area of the region 306 (region connecting the flags “5” to “4”) indicated by the timing tightness information 304 and 303 indicating that the timing tightness of the adjacent wiring is the most severe. If the area ratio exceeds a predetermined value, only that region is deleted. Further, when the area ratio exceeds a predetermined value, an area 307 (an area connecting the flags “5” to “1”) including the timing tightness information 304 indicating the next severe timing tightness and the unwired grid information 103 ) Is calculated, and a process for determining whether the area ratio exceeds a predetermined value is performed. In the same manner, the regions 308, 309, and 310 are sequentially processed from the strict side to the loose side.

  When the area ratio rule is satisfied in the process of sequentially reducing the area of the dummy pattern, the area 310 belonging to the class that is the target of the reduction process is deleted in order, The deletion process is terminated when the maximum area ratio is satisfied.

  Next, in step 603, area ratio determination processing is performed. When the area ratio is satisfied, the extracted dummy pattern is used as a flattening pattern as it is, and when only the region 311 that is not adjacent to the wiring does not satisfy the maximum area ratio, In step 406, the dummy pattern is reduced so that the excess area is reduced.

  The subsequent steps 407 and 408 are the same as those in the first embodiment.

  As described above, according to the third embodiment, in the step of generating the flattening pattern information, a special mask calculation process unique to the mask processing tool is not used, and the flattening pattern is displayed on the placement and routing tool database. Since it produces | generates, a planarization pattern can be produced | generated easily. In addition, since the timing calculation / verification can be performed based on the capacity information including the flattening pattern, the operation failure rate after the LSI manufacturing can be reduced.

  Further, since the dummy pattern is not divided by repeating simple figures as in the case of the prior art, the number of flattening patterns and the amount of data can be further reduced as compared with the prior art.

  Further, since the flattening pattern information is generated so that there are few flattening patterns in the region with high timing tightness and the flattening pattern is large in the region with low timing tightness, the influence on the signal delay is shown in the second embodiment. Can be kept even lower than the above.

(Embodiment 4)
Hereinafter, a method for automatically generating a flattening pattern according to the fourth embodiment of the present invention will be described with reference to FIGS. 1A and 7 and FIGS. 8A to 8D.

  First, after grid information is input in step 401, the grid information 101 is initialized as shown in FIG. In the grid base wiring tool, the grid interval of the grid information 101 used at this time is usually set to [minimum interval + minimum line width] when using the wiring track information. There is no need to do. However, other than the grid-based wiring tool, it is necessary to consider a separation rule in the next process, and therefore the minimum line interval and the minimum grid on the mask process are set as the grid interval.

  Next, in the wiring process of step 901, wiring of a wiring pattern 1001 as shown in FIG.

  Next, in the rewriting process of the grid information in step 902, as shown in FIG. 8B, the wiring is applied to the grid area adjacent to the wiring pattern 1001 generated in step 901 or the grid area having a width satisfying the separation rule. The grid information 1002 (flag “2”) indicating the adjacent grid is rewritten.

  Next, in step 903, LPE processing (resistance / capacitance extraction processing) is performed in consideration of the presence of a pattern in the wiring adjacent grid information 1002, and timing calculation is performed in step 904 based on this information.

  Next, in step 905, it is determined whether or not all wiring processes have been completed. If there is an unwired pattern, the wiring process in step 901 is repeated. For example, when the wiring pattern 1003 is considered as the next wiring route as shown in FIG. 8B, the timing calculation is performed based on the LPE information considering that the dummy pattern 1004 is generated in FIG. 8C. If the timing constraint is satisfied, the wiring pattern is determined as shown in FIG. 8D, and the grid information is rewritten in step 902. As a result, grid information 1005 is obtained.

  After this process is repeated and all the wiring processes are completed, the same processes as those after step 403 in the first embodiment are performed.

  As described above, according to the fourth embodiment, the timing calculation can be performed in consideration of the generation of the flattening pattern information during the wiring process on the database of the placement and routing tool. There is no variation in timing information, as seen when generating. This eliminates the need for a correction process for satisfying the timing constraint after putting the planarization pattern information after wiring, and can dramatically reduce the design period.

  Further, since the dummy pattern is not divided by repeating simple figures as in the case of the prior art, the number of flattening patterns and the amount of data can be further reduced as compared with the prior art.

(A)-(d) is process explanatory drawing which shows each process of the planarization pattern automatic generation method concerning Embodiment 1 of this invention. (A), (b) is process explanatory drawing which shows each process of the planarization pattern automatic generation method concerning Embodiment 2 of this invention. (A), (b) is a top view which shows each process of the planarization pattern automatic generation method concerning Embodiment 3 of this invention. It is a flowchart of the planarization pattern automatic generation method concerning Embodiment 1 of this invention. It is a flowchart of the planarization pattern automatic generation method concerning Embodiment 2 of this invention. It is a flowchart of the planarization pattern automatic generation method concerning Embodiment 3 of this invention. It is a flowchart of the planarization pattern automatic generation method concerning Embodiment 4 of this invention. It is process explanatory drawing which shows each process of the planarization pattern automatic generation method concerning Embodiment 4 of this invention. (A)-(d) is process explanatory drawing which shows each process of the conventional planarization pattern automatic generation method. (A)-(c) is process explanatory drawing which shows each process of the production | generation method of the conventional planarization pattern.

Explanation of symbols

101 Grid information 102 Wiring pattern 103 Unwired grid information (Grid information initialization value)
104 Already-wired grid information 105 Maximum shape information (dummy pattern)
201 Wiring adjacent grid information 202 Maximum shape information 203 Area 204 consisting only of wiring adjacent grid 204 Unwired / wiring adjacent grid mixed area 301 Timing tightness information 302 Timing tightness information 303 Timing tightness information 304 Timing tightness information 306 Wiring adjacent grid Area 307 Wiring adjacent grid area 308 Wiring adjacent grid area 309 Wiring adjacent grid area 401 Grid information initialization process 402 Grid information rewriting process 403 Dummy pattern extraction process 404 Area ratio calculation process 405 Area ratio determination process 406 Dummy pattern reduction process 407 Resistance / Capacity extraction processing 408 Timing calculation processing 501 Wiring adjacent grid information rewriting processing 502 Dummy pattern deletion processing 503 Area ratio discrimination processing 601 Wiring adjacent grid information rewriting Management 602 dummy pattern deletion process 603 area ratio determination process 901 wiring process 902 interconnect adjacent grid information rewriting process 903 resistance-capacitance extraction processing 904 timing calculation process 905 wiring process determination processing

Claims (3)

For the database in the automatic place and route tool,
A step of discriminating between the existing wiring grid and the non-wiring grid from the wiring pattern information in the wiring area in the wiring layer and the grid information;
Extracting a region including all of the unwired grid as a maximum shape, and obtaining maximum shape information corresponding to the maximum shape;
Identifying the unwired grid adjacent to the already-routed grid as the wire-adjacent grid based on the already-wired grid and the unwired grid, and obtaining the wire-adjacent grid information corresponding to the wire-adjacent grid; and
Deleting the wiring adjacent grid indicated by the wiring adjacent grid information from the maximum shape indicated by the maximum shape information, and generating planarization pattern information based on the shape information corresponding to the shape as a result of the deletion. A method for automatically generating a flattening pattern. The flattening pattern automatic generation method according to claim 1,
When deleting the wiring adjacent grid from the maximum shape in the step of generating the flattening pattern information, the wiring adjacent grid in a dense region in the density of the existing wiring grid indicated by the wiring adjacent grid information is deleted with priority. A method for automatically generating a flattening pattern. The flattening pattern automatic generation method according to claim 1,
Based on the already-wired grid and the unwired grid, an unwired grid adjacent to the already-wired grid is identified as a wire adjacent grid, and the wire adjacent to the wire adjacent grid among the unwired grids The method further includes a step of obtaining grid information including timing tightness by adding information indicating timing tightness,
In the step of generating the planarization pattern information, the wiring adjacent grids having higher timing tightness indicated by the grid information including the timing tightness are preferentially deleted from the maximum shape indicated by the maximum shape information, and the deletion is performed. A flattening pattern automatic generation method, characterized in that the flattening pattern information is generated based on the resulting shape information.

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