JP2000278343A - Clock reproducing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely reproduce a clock synchronized to a base band. SOLUTION: A first phase comparator 11 outputs a phase detecting signal PCO1 on the basis of an I base band and a phase comparator 12 outputs a phase detecting signal PCO2 on the basis of a Q base band. One of phase detecting signals is flattened by a loop filter 33 and inputted to a VCXO 34 as a control signal. A frequency signal corresponding to the control signal is outputted from the VCXO 34 and inputted to the first and second phase comparators 11 and 12 again after frequency division. In the first and second phase comparators 11 and 12, the zero cross of the I and Q base bands is detected, and zero cross detecting signals ZRDT1 and ZRDT2 are inputted to a decoder 13. The zero cross detecting signal to become '1' corresponding to each zero cross is outputted. According to the combination of the zero cross detecting signals ZRDT1 and ZRDT2, respectively correspondent selector signals are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock recovery circuit suitable for use in a quadrature demodulation circuit for digital television broadcasting.

[0002]

2. Description of the Related Art In recent years, a technique for supplying a television broadcast signal as a digital signal has been put to practical use, and digital television broadcast has started commercially. There are two types of digital television broadcasting, one that transmits digital television signals using satellites and one that transmits digital television broadcasting by terrestrial waves. Among them, satellite digital television broadcasting will be described.

FIG. 5 is a diagram showing the structure of one frame of digital data received by a satellite digital broadcast receiver. The digital data includes 39936 symbols in one frame. Here, the symbol means a signal received in synchronization with one clock. The head of one frame is composed of a TMCC signal (transmission multiplex control signal) and a synchronization word signal. The TMCC signal transmits control information related to a slot signal and a transmission method. The number of symbols of the synchronization word signal is a total of 40 symbols. The total number of symbols of the TMCC signal and the synchronization word signal is 192,
It is transmitted as a PSK (Binary PSK) modulation signal.

Following the TMCC signal and the synchronizing word signal, data (video portion, audio portion, etc.) and a carrier clock burst signal are alternately arranged. The number of symbols of each data is 203, and the number of symbols of each burst signal for carrier clock is 4 symbols. The carrier lock burst signal is a BPSK modulation signal.

[0005] Assuming that a data portion composed of 203 symbols and a carrier lock burst signal portion composed of four symbols are one set, a total of four consecutive sets ((203+
4) × 4 symbols) is called one slot.

Each of the slots is modulated by various modulation methods. After frequency pull-in, a synchronization word is detected, frame synchronization is performed, and then the content of the TMCC signal is demodulated, so that it is recognized which data of which modulation scheme is sent and in which order. As modulation methods, 8PSK, QPSK (QPSK: QuadraturePS)
K) and BPSK.

Next, the configuration of a satellite digital broadcast receiver is shown in FIG. The digital television signal transmitted from the satellite is synchronously detected and down-converted in frequency in a tuner 61. Tuner 61
Are demodulated by a quadrature phase demodulation circuit 62 to generate I and Q basebands. Thereafter, the PSK demodulation circuit 63 performs various PSK demodulations according to the I and Q basebands.
Error correction of the SK demodulated signal is performed. Error corrected P
The SK demodulated signal is converted by the signal processing circuit 65 into MPEG1 or MP
It is decoded into moving image data and audio data by the EG2 method.

FIG. 3 shows a specific circuit of the quadrature phase demodulation circuit 62 in a digital broadcast receiver. In FIG. 3, a digital television signal is subjected to quadrature detection in multipliers 1 and 2, and I and Q basebands are output. The multipliers 1 and 2 form a quasi-synchronous detection circuit. The I and Q basebands are respectively limited to predetermined bands by the roll-off filters 3 and 4, and signals of the predetermined bands are passed. The outputs of the roll-off filters 3 and 4 are transmitted to a subsequent circuit.

[0009] The I baseband is used to reproduce a reproduction clock. The I baseband is a phase comparator 31
And compared with the phase of the output of the frequency divider 32. The phase difference of the phase comparison circuit 31 is flattened by the loop filter 33 and converted into a control voltage of the VCXO 34.
The output frequency of the VCXO 34 is changed by the control voltage. The output frequency signal of the VCXO 34 is frequency-divided by the frequency divider 32 and applied to the phase comparator 31 again. The reproduced clock is reproduced by a generally known PLL method, and a reproduced clock synchronized with a clock included in the I baseband is output from the frequency divider 32.

[0010]

FIG. 4A shows a constellation of the QPSK modulation system. In the case of the QPSK modulation scheme, there are code points (A, B, C, D) indicating baseband vectors in four quadrants, and transitions between code points are made according to data. In the circuit of FIG. 3, the phase comparator 31 detects that each code changes with respect to the zero cross of the I baseband, that is, the Q axis, and uses the detection result as a reference signal of the clock recovery circuit.

For example, if the baseband is code point A in FIG.
, The transition to the code point B is made with respect to the Q axis, and the I baseband is zero-crossed. When the baseband transitions from code point A to code point C, I
And Q axis, and both the I and Q basebands cross zero. On the other hand, when the baseband changes from the code point A to the code point D, the baseband changes with respect to the I axis, and zero crossing of the I baseband is not performed.
Here, in general, in the digital modulation operation, energy diffusion is performed by multiplying the transmitted baseband by pseudorandom noise as preprocessing. This lowers the probability of continuous transition between code points A and D or between B and C. Therefore, the probability that the I baseband does not cross zero is extremely low, and it is possible to reproduce the reproduction clock even using only the I baseband.

By the way, in satellite digital television broadcasting, BPSK, QPSK and 8PSK are adopted as modulation systems. FIG. 4A shows a constellation of the BPSK modulation method. Since a zero cross occurs in the I baseband, the clock can be reproduced according to the I baseband even in the BPSK modulation method. However, in the 8PSK modulation method, phase ambiguity occurs at a phase interval of π / 8, which may adversely affect the BPSK modulation method. In satellite digital television broadcasting, B
There are TMCC data and a burst signal modulated by the PSK modulation method. For example, when a transition to the BPSK modulation method is performed after the QPSK modulation method, the phase reproduction loop in the BPSK modulation method is out of phase due to the phase ambiguity of the QPSK modulation method. It is possible to lock.

For example, assume that when shifting from the 8PSK modulation method to the QPSK modulation method, a phase shift of π / 2 occurs as shown in FIG. Then, a transition is performed between the code points A ′ and B ′ in FIG. 4C, a zero cross occurs in the Q baseband, and the zero cross cannot be detected continuously from the I baseband. Therefore, in a conventional circuit for recovering a clock from the I baseband, the phase comparator 31 loses its reference signal.
Gain decreases. Then, in the unlocked state of the clock recovery loop, the pull-in speed to the locked state becomes slow, and in the worst case, the pull-in cannot be performed. Further, in the locked state, the jitter of the reproduced clock becomes large, the latch point with respect to the baseband at the time of signal processing fluctuates, and the bit error rate deteriorates.

[0014]

According to the present invention, in a clock recovery circuit for demodulating a recovered clock from two basebands having an orthogonal relationship, a zero-cross detection circuit for detecting the baseband zero-cross, And a PLL for outputting a reproduction clock based on one of the basebands in accordance with the detection signal.

[0015] The present invention is further characterized in that a decoder is provided which indicates a combination of baseband selections according to the output signal of the zero-cross detection circuit. In particular, the PLL is
A voltage controlled oscillator having a variable output frequency, a first phase comparator for detecting a phase difference between the recovered clock and one baseband, and a second phase comparator for detecting a phase difference between the recovered clock and the other baseband And a selection circuit for selecting one of the first and second phase comparators in accordance with a detection result of the zero-cross detection circuit.
CO is controlled based on an output signal of the selection circuit.

Further, the invention is characterized in that a decoder is provided which outputs a selection signal indicating a combination of selections in the selection circuit in accordance with an output signal of the zero-cross detection circuit.

According to the present invention, a zero cross is detected from each of two base bands, and a bit clock is reproduced based on the base band from which the zero cross was detected.

[0018]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The same reference numerals as in FIG. 3 denote the same circuits as in FIG.

Reference numeral 11 denotes a first phase comparator which uses the I baseband as a reference input, compares the phases of the I baseband and the output of the frequency divider 32, and detects a zero crossing of the I baseband, and 12 denotes a Q baseband. Is a reference input, and the second phase comparator compares the phases of the output of the Q baseband and the frequency divider and detects the zero crossing of the Q baseband. Reference numeral 13 denotes a zero-cross detection signal ZR output from the first and second phase comparators 11 and 12.
The decoder 14, which decodes DT1 and ZRDT2 and outputs a select signal, outputs a first signal in response to the select signal.
MU for selecting one of phase detection signals PCO1 and PCO2 output from second phase comparators 11 and 12
X (multiplexer).

The first phase comparator 11 shown in FIG. 3 outputs a phase detection signal PCO1 based on the phase difference between the I baseband and the output of the frequency divider 32, and the phase comparator 12 outputs the Q baseband and the frequency divider 33. Phase detection signal PCO2 based on the output of
Is output. One of the phase detection signals PCO1 and PCO2 is flattened by the loop filter 33 and VCX
It is input to O34 as a control signal. The output frequency of the VCXO 34 is changed according to the control signal, and the output signal of the VCXO 34 is frequency-divided and then input to the first and second phase comparators 11 and 12 again.

In the first and second phase comparators 11 and 12, zero crossings of I and Q basebands are also detected.
The zero cross detection signals ZRDT1 and ZRDT2 are input to the decoder 13. When a zero cross is detected in the I and Q basebands, a zero-cross detection signal that becomes “1” corresponding to each baseband is output. Then, a selector signal corresponding to each of the combinations of the zero-cross detection signals ZRDT1 and ZRDT2 is output.

As shown in FIG. 7, the zero cross signal ZRD
When only T1 is “1”, for example, 2 composed of “1, 0”
A bit select signal is output, and the phase detection signal PCO1 is selected as the output of the MUX 14. When only the zero-cross signal ZRDT2 is “1”, a select signal of “0, 1” is output, and the phase detection signal PCO2 is selected as the output of the MUX 14. When the zero-cross signals ZRDT1 and ZRDT2 are both "0", the select signal becomes "0, 0", and the previous value data, that is, the previously selected phase detection signal is output from the MUX 14. Further, the zero-cross detection signals ZRDT1 and ZRDT2 are both “1,
1 ", the select signal becomes" 1, 1 "and the MU
The phase detection signal PCO1 is forcibly selected from X14.

For example, assume that the I and Q basebands transition as shown in FIGS. First, when only the I baseband changes to "1", the zero-cross detection signal ZRDT1 is output as shown in FIG. 2C, and the phase detection signal PCO1 is output based on the I baseband as shown in FIG. You. As a result, the phase detection signal PCO1 is output as the output of the MUX 14 as shown in FIG. Next, when the basebands I and Q change to “0” and “1”, respectively, the zero-crossing detection signal ZRDT as shown in FIGS.
1 and ZRDT2, and the phase detection signals PCO1 and PCO2 as shown in FIGS. As a result, the phase detection signal OP1 is forcibly output from the MUX 14.

Further, when only the Q baseband changes to "0", the zero-crossing detection signal ZRDT as shown in FIG.
2 and the phase detection signal PCO2 is output based on the Q baseband as shown in FIG. As a result, the phase detection signal PCO2 is output as the output of the MUX 14 as shown in FIG. Next, baseband I and Q
Does not change, as shown in FIG.
DT1 and ZRDT2 and phase detection signals PCO1 and PC
O2 is not output. As a result, from MUX14,
It reads out the held pre-data and outputs a phase detection signal. The MUX 14 has a function of selecting a phase detection signal every time a select signal is input, resetting the preceding data, and holding the selected phase detection signal again.

The zero-cross detection signals ZRDT1 and ZRDT1
When both RDT2 are "1, 1", the phase detection signal PC
Since both O1 and PCO2 are output, the clock can be recovered even if the phase detection signal PCO2 is forcibly detected.

As described above, even if one of the I and Q basebands does not change, the phase detection signal can be obtained from the MUX 14 substantially in synchronization with the bit rate of the baseband. Therefore, even if one of the I and Q basebands disappears due to a phase shift, a phase detection signal can be reliably obtained. In particular, in the case of the BPSK modulation method, even if a large phase shift occurs and a problem as in the past occurs,
The clock can be reliably reproduced.

[0027]

According to the present invention, since a reference signal can be obtained from the I and Q basebands, the gain of the phase comparator 31 can be improved even if a phase shift occurs. Therefore, when the clock recovery loop is in the unlocked state, it is possible to increase the pull-in speed to the locked state or to perform the pull-in reliably. Further, in the locked state, the jitter of the reproduced clock can be reduced, the latch point with respect to the baseband at the time of signal processing is fixed, and deterioration of the bit error rate can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a characteristic diagram showing a constellation of each modulation scheme.

FIG. 5 is a diagram showing a data sequence of a digital television signal.

FIG. 6 is a block diagram showing a satellite digital television receiver.

FIG. 7 is a state diagram for explaining a state of the decoder 13 of FIG. 1;

[Explanation of symbols]

 11 first phase comparator 12 second phase comparator 13 decoder 14 MUX

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5J106 AA04 BB02 BB04 BB09 CC01 CC30 EE01 EE08 FF01 GG04 GG18 HH10 KK03 KK25 5K004 AA05 FA03 FA05 FA06 FG02 FH01 FH08 FJ14 FJ15 5K047 AA03 GG09 MM33 MM33

Claims (4)

[Claims] 1. A clock recovery circuit for demodulating a recovered clock from two basebands having an orthogonal relationship, wherein: a zero-cross detection circuit for detecting the baseband zero-cross; and one of bases according to the zero-cross detection signal. A clock recovery circuit comprising: a PLL that outputs a recovered clock based on a band. 2. The clock recovery circuit according to claim 1, further comprising a decoder that indicates a combination of baseband selections in accordance with an output signal of the zero-cross detection circuit. 3. The PLL comprises: a voltage-controlled oscillator having a variable output frequency; a first phase comparator for detecting a phase difference between the recovered clock and one of the basebands; A second phase comparator for detecting a phase difference; and the first phase comparator according to a detection result of the zero-cross detection circuit.
2. A clock recovery circuit according to claim 1, wherein said VCO is controlled based on an output signal of said selection circuit. 4. The clock recovery circuit according to claim 3, further comprising a decoder that outputs a selection signal indicating a combination of selections in said selection circuit in accordance with an output signal of said zero-cross detection circuit.