JP2000269430A - Input protective circuit, manufacture of semiconductor substrate, semiconductor device and manufacture of the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To input a large signal potential, even without providing two power sources or voltage conversion circuits in an input protective circuit. SOLUTION: Input signals inputted from an input pad 11 are connected via an input signal line 14 to an input gate 13. To the input signal line 14, this input protective circuit 12 is inserted. The input protective circuit is constituted of one p-n junction diode 20, whose one end is connected to the input signal line 14, and other end is connected to a ground potential VSS. The p-n junction diode 20 is constituted of a p-type silicon substrate 21 and a heavily doped region 23, formed by heavily doping n-type impurities on the surface of the p-type silicon substrate 21. Then, in the silicon substrate 21 at the lower part of the diode 20, a void 24 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit provided on a semiconductor substrate for protecting a semiconductor device. Further, the present invention relates to a method for manufacturing a semiconductor substrate formed using a wafer bonding technique and a method for manufacturing a semiconductor having an SOI structure. Still further, the present invention relates to a semiconductor device having an intrinsic gettering site and a method of manufacturing the same.

[0002]

2. Description of the Related Art In an input circuit of a MOS type integrated circuit, a protection circuit including two PN junction elements is provided to protect the circuit from external noise. FIG. 1 shows a circuit diagram and electrical characteristics of a conventionally used input protection circuit.
6, shown in FIG. The input signal input from the input pad 11 passes through the protection circuit 170 and is input to the input gate 13. The input protection circuit includes two PN junction diodes. The first PN junction diode 171 is connected to the ground potential V _ss and the input signal line 14, and the second diode 172 is connected to the input signal line 14 and the power supply potential. Connected to _Vdd .

[0003] When the potential of the input signal (signal potential) V _in is at the signal between the ground potential V _ss and the power supply potential V _dd, the signal potential V _in is directly transmitted to the input gate. However, if the signal potential V _in is lower than the ground potential V _ss are first diode 171 for the first diode 171 becomes forward biased is turned on, an excessive current in the first diode 171 since flow signal potential V _in does not fall from the ground potential V _ss, the input gate 13 is not destroyed. Conversely, if the signal potential V _in is higher than the power supply potential V _dd is,
The second diode 172 is turned on to prevent the input gate 13 from being broken.

The power supply potential to be used has been reduced due to recent miniaturization of elements. In this case, devices having a plurality of power supply potentials are often connected on a circuit board. The problem in this case is particularly important in the input circuit. For example, when the output of a device having a large external power supply potential is used as an input signal, an excessive current continues to flow through the protection circuit as described above. in this case,
There is a possibility that the heat generation may cause a disconnection or damage to the elements constituting the protection circuit. Therefore, in order to accept a large input, either prepare the internal power supply for the input circuit and the external power supply for supplying the normal gate internally, or provide a voltage conversion circuit inside and handle the two voltages in the same chip. Was to be able to do it.

[0005] In the former case, there is a problem that the operation is not performed unless two types of power supplies are used, so that there is a problem in that the restrictions on use are large.
In the latter case, there is a problem that an area for having a voltage conversion circuit in a chip and unnecessary power consumption for voltage conversion are required, which is not economical.

[0006] In recent years, as a demand for a semiconductor device, a reduction in power consumption has been demanded in addition to an increase in integration and speed. In order to realize low power consumption, the point is to reduce the power supply potential and the parasitic capacitance.

There are several ways to reduce the parasitic capacitance.
Above all, SOI using SOI (Silicon On Insu1ator) substrate
It is most effective to adopt the I structure. In the SOI structure, the extension of the depletion layer of the MOS transistor is suppressed, so that the junction capacitance of the source / drain region can be made much smaller than that of a MOS transistor formed on a silicon substrate. In other words, by employing the SOI structure, power consumption due to parasitic capacitance can be reduced, and thus, power consumption of the semiconductor device can be reduced.

[0008] As a method of forming an SOI substrate, SI
There are MOX (Separation by Implanted Oxygen) technology and wafer bonding technology. SIMOX technology uses single crystal Si
In this method, oxygen ions are implanted into a substrate, and then heat treatment is performed to form a buried oxide film layer in the Si substrate. The wafer bonding technique is a technique in which an oxide film is formed on one of two Si substrates, and after bonding them, one is thinned by polishing to form an SOI structure.

However, since the SIMOX technique forms an insulating film by ion implantation, there is a problem that crystal defects such as dislocations remain in the SOI substrate. on the other hand,
The wafer bonding technique has a problem that although there are few crystal defects in the substrate, it is difficult to control the thickness of the semiconductor layer and it is difficult to form an SOI substrate.

In a semiconductor device, it is well known that impurities such as metal entering a semiconductor substrate during the manufacturing process have a remarkable effect on its electrical characteristics. Although it is natural to pay attention to contamination of impurities such as metals from the viewpoint of improving the yield and reliability of the semiconductor device, it is impossible to always suppress the contamination throughout the entire manufacturing process of the semiconductor device. Therefore, a technique is required in which the contaminant metal impurities are captured in a portion deeper than the surface of the semiconductor substrate on which the element is formed.

This technique is called a gettering technique. As a technique for trapping contaminant metal impurities at a deep position in a semiconductor substrate, there is an intrinsic gettering technique. Intrinsic gettering technology heat-treats a silicon substrate containing oxygen to form a defect-free region near the surface of the semiconductor substrate, and at the same time, a large number of oxygen precipitates, dislocation loops and stacks inside the semiconductor substrate. In this method, a defect or the like is generated, and metal impurities mixed in the semiconductor substrate are collected in a strain field around the defect, thereby suppressing deposition of the metal impurity in the element active region in the defect-free region. Intrinsic gettering technology has recently attracted attention because of its good compatibility with semiconductor manufacturing processes and its excellent gettering ability.

An important point of the intrinsic gettering technique is the selection of a semiconductor substrate. When a normal CZ substrate is used, since a cavity called COP which is introduced into the semiconductor substrate during the crystal growth process and has a density of about 100 nm and a density of about 10 ⁶ cm ^-3 , the gate oxide film withstand voltage and reliability are problematic. Become. Also, if an epitaxial substrate is used to avoid this problem, the oxygen concentration near the surface decreases, so that the gettering ability (the ability to adsorb metal impurities)
Becomes lower.

In general, since the history of the heat treatment process in the manufacturing process differs for each product, when different semiconductor devices are manufactured using the same semiconductor substrate, the size and density of oxygen precipitates in the substrate of the completed semiconductor device are reduced. The interstitial oxygen concentration differs for each semiconductor device. This means that if you want to keep the gettering ability constant, you should design the semiconductor substrate optimally for each semiconductor device to be manufactured,
This means that specifications such as the oxygen concentration of the semiconductor substrate must be changed, which results in an increase in semiconductor device development cost and semiconductor substrate cost.

The above difficulty is that the control of oxygen precipitation depends on the thermal history of the product, and the parameter of the thermal history is also a parameter that determines the electrical characteristics of the product. This is caused by the inability to control the electrical characteristics of the product independently. In addition, as the device becomes finer, the temperature of the semiconductor manufacturing process decreases, and oxygen precipitation hardly occurs. In this sense, control of intrinsic gettering is becoming difficult.

[0015]

As described above, if an excessive current is continuously supplied to the conventional input protection circuit, there is a possibility that heat generation may cause disconnection or destruction of elements constituting the circuit. Therefore, if two power supplies, that is, a power supply for an input circuit and an external power supply for supplying a normal gate, are provided in order to accept a large input signal, there is a problem in that use restrictions are large. Further, if a voltage conversion circuit is provided in a chip to accept a large input, there is a problem that an area for the voltage conversion circuit and unnecessary power consumption for voltage conversion are required.

Further, in the conventional wafer bonding technique used for manufacturing an SOI substrate, there are problems that crystal defects remain in a semiconductor layer in the SOI substrate and that it is difficult to control the thickness of the semiconductor layer.

Further, since the history of the heat treatment process is different for each semiconductor device product, it is necessary to change the specifications such as the oxygen concentration in the semiconductor substrate by designing the semiconductor substrate optimally for each product. However, there is a problem that the price of the semiconductor device and the development cost of the semiconductor device increase. Further, with the miniaturization of the semiconductor element, there has been a problem that the heating temperature in the manufacturing process has become lower, and oxygen precipitation has become less likely to occur, making it difficult to form gettering sites.

An object of the present invention is to provide an input protection circuit capable of inputting a large signal potential without providing two power supplies or voltage conversion circuits.

Another object of the present invention is to provide a method of manufacturing a semiconductor substrate in which the thickness of a semiconductor layer can be easily controlled in a wafer bonding technique. Another object of the present invention is to provide a method of manufacturing a semiconductor device having an SOI structure that can simultaneously suppress crystal defects and improve the controllability of the film thickness of the semiconductor device.

It is another object of the present invention to provide a semiconductor device having a gettering site which does not depend on a thermal process history in a product manufacturing process, and a method of manufacturing the same.

[0021]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object.

(1) The input protection circuit of the present invention (claim 1) has one end connected to a signal line connecting an input pad to which an input signal is input and an input gate, and the other end connected to a ground potential or a power supply. A semiconductor substrate of a first conductivity type, connected to a potential,
A junction diode including a diffusion layer of the second conductivity type formed on the surface of the semiconductor substrate of the first conductivity type; and a junction diode formed in the semiconductor substrate of the first conductivity type below the junction diode. It is characterized by comprising a cavity or a foreign substance made of a different material from the semiconductor substrate embedded in the cavity. It is preferable that the cavity or the foreign matter is formed at a position that can be in contact with a space charge region formed by the junction diode.

(2) In a method of manufacturing a semiconductor device according to the present invention (claim 3), a step of forming a groove in a semiconductor substrate and a step of heating the semiconductor substrate to move atoms or molecules constituting the semiconductor substrate are performed. Closing the opening of the groove and forming a cavity inside the substrate, flattening the surface of the semiconductor substrate, and forming a semiconductor substrate and a substrate having an insulating film formed on at least the surface thereof. The method includes a step of attaching the semiconductor substrate via an insulating film, and a step of polishing the surface of the semiconductor substrate to remove the cavity.

(3) In the method of manufacturing a semiconductor device according to the present invention (claim 4), a step of forming a groove in a semiconductor substrate and a step of selectively forming a material having a different polishing rate from that of the semiconductor substrate in the groove. Heating the semiconductor substrate, moving atoms or molecules constituting the substrate to cover the opening of the groove, and selectively forming the foreign matter inside the semiconductor substrate; and Flattening the surface of the substrate;
A step of bonding a semiconductor substrate and a substrate having an insulating film formed on at least a surface thereof, with the insulating film interposed therebetween, and a step of polishing the surface of the semiconductor substrate to remove the foreign matter, I do.

(4) In the method of manufacturing a semiconductor device according to the present invention (claim 5), a step of forming a groove in the semiconductor substrate and a step of heating the semiconductor substrate to move atoms or molecules constituting the semiconductor substrate are performed. Closing the opening of the groove and forming a cavity inside the substrate; flattening the surface of the semiconductor substrate; forming a semiconductor element on one surface of the semiconductor substrate; One side of the semiconductor substrate and the first
Bonding the substrate, polishing the surface of the semiconductor substrate to remove the cavity, bonding the polished surface of the semiconductor substrate to a second substrate, and peeling the first substrate. And a step.

(5) In the method of manufacturing a semiconductor device according to the present invention (claim 6), a step of forming a groove in the semiconductor substrate and a step of selectively forming a material having a different polishing rate from the semiconductor substrate in the groove are performed. Heating the semiconductor substrate, moving atoms or molecules constituting the substrate to cover the opening of the groove, and selectively forming the foreign matter inside the semiconductor substrate; and Flattening the surface of the substrate, forming a semiconductor element on one surface of the semiconductor substrate, bonding one surface of the semiconductor substrate to a first base, The method includes a step of polishing to remove the cavities or foreign matters, a step of bonding a polished surface of the semiconductor substrate to a second base, and a step of peeling the first base.

(6) In the semiconductor device according to the present invention (claim 7), a semiconductor element formed on the surface of the semiconductor substrate, a depletion layer formed below the semiconductor element in the semiconductor substrate, and formed by the semiconductor element And one or more cavities or foreign matter embedded in the cavities formed at a position deeper than the region.

Preferred embodiments of the present invention (claim 7) are described below. The depth of the cavity or foreign matter does not affect the stress field created by the cavity or foreign matter on the surface of the semiconductor element. The depth at which the cavity or foreign matter is present is at least three times the size of the cavity. At least one set of cavities in which the distance between the cavities or foreign matters is smaller than the depth of the cavities. Dislocation defects that do not reach the surface of the semiconductor element are present in the cavity or the foreign substance itself or in the vicinity thereof. The cavities or foreign substances are formed on the array. A cavity or foreign matter is arranged in a peripheral area of the semiconductor chip. Cavities or foreign substances are arranged avoiding the deepest structure region inside the semiconductor substrate.

(7) In the method of manufacturing a semiconductor device according to the present invention (claim 8), a step of forming a groove in a surface of a semiconductor substrate;
Heating the semiconductor substrate, moving atoms or molecules constituting the semiconductor substrate, closing the opening of the groove, forming a cavity in the semiconductor substrate, and flattening the surface of the semiconductor substrate. And forming a semiconductor element on the surface of the semiconductor substrate.

(8) In the method of manufacturing a semiconductor device according to the present invention (claim 9), a step of forming a groove in a surface of a semiconductor substrate;
Selectively forming a material constituting a foreign substance in the groove, and heating the semiconductor substrate to move atoms or molecules forming the semiconductor substrate to cover an opening of the groove; Forming a foreign substance in the substrate, flattening a surface of the semiconductor substrate, and forming a semiconductor element on the surface of the semiconductor substrate.

Preferred embodiments of the present invention (claims 8 and 9) are described below.

The position and size of the cavity or foreign matter are determined by lithographic means. The depth of the cavity or foreign matter is determined by the depth of the groove. A semiconductor device is manufactured using a semiconductor substrate in which a cavity or a foreign substance is formed.

[Function] The present invention has the following functions and effects by the above configuration.

By forming a cavity or foreign matter in the semiconductor substrate below the junction diode, a kink characteristic appears in the reverse characteristic of the diode and the breakdown voltage is reduced. Therefore, when connecting devices having different power supply potentials, An excessive current does not flow to the protection circuit to cause damage or increase power consumption of another device. Therefore, 2
The power supply operation and the internal voltage conversion circuit become unnecessary. The characteristics can be changed depending on the position of the cavity, and a design suitable for the application can be made. Further, since only one diode is required for the input protection circuit, the area occupied by the protection circuit can be reduced.

The formation depth of the cavity or foreign matter can be controlled by the depth of the groove formed in the semiconductor substrate. And
By selectively forming cavities or foreign substances in the semiconductor substrate in advance, when the semiconductor substrate is polished and thinned, the polishing rate changes on the polished surface having the cavities or foreign substances. Therefore,
By measuring the change in the speed of the polished surface, it is possible to detect the position where a cavity or a foreign substance is present, and thus to know the polishing position.

Therefore, by detecting the polishing rate, it is possible to easily detect the time for removing the voids or foreign substances. If the polishing of the semiconductor substrate is completed at the time of the removal, the thickness of the semiconductor layer is reduced. Can be easily controlled.

Since the size, position, density, and depth of the cavity or foreign matter can be controlled by the position and depth of the groove, it can be easily designed. Since the cavities or foreign matter serve as gettering sites, the gettering sites can be formed without depending on the thermal history of the manufacturing process. Therefore, it is not necessary to prepare a substrate having a different oxygen concentration for each device.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a diagram showing a configuration of an input protection circuit according to a first embodiment of the present invention. FIG. 1A is a diagram illustrating an equivalent circuit of the input protection circuit, and FIG. 1B is a cross-sectional view illustrating a structure of a pn junction diode element used in the input protection circuit.

An input signal input from the input pad 11 is connected to an input gate 13 via an input signal line 14. The input protection circuit 12 is inserted into the input signal line 14. The input protection circuit includes one pn junction diode 20 having one end connected to the input signal line 14 and the other end connected to the ground potential V _ss .

The structure of the pn junction diode 20 will be described with reference to FIG. As shown in FIG. 1B, the pn junction diode 20 is a p-type silicon substrate 21.
And 1 × 1 n-type impurities on the surface of p-type silicon substrate 21.
And a high-concentration impurity region 23 formed by being doped at a high concentration of about 0 ²⁰ cm ⁻³ . The diode 20 is separated from other elements by an element isolation insulating film 22. The diode 20 operates by applying a potential between the p-type silicon substrate 20 and the high-concentration impurity region 23, but an electrode for applying the potential is omitted in this figure. If the p-type silicon substrate 20 was subjected to a voltage higher than the ground potential V _ss to the high concentration impurity region 23 is connected to the ground potential _Vss, and the diode 20 is reverse current flows, this value is usually very small, negligible it can.

A cavity 24 is formed in the silicon substrate 21 below the diode 20. Cavity 24
_Means that the substrate 21 is set to the ground potential _Vss and the high-concentration impurity region 2
3 is formed in the space charge region 25 where no carrier exists when a voltage higher than the ground potential V _ss is applied to 3. The width of the space charge region 25 is about 0.1 to 1 μm, and changes according to the impurity concentration of the substrate 21 and the applied voltage.

Cavity 2 formed in space charge region 25
4, the reverse characteristics of the diode 20 are affected. Diode 20 with cavity or foreign matter in lower part
_Breaks down at a lower voltage _Vbn compared to the breakdown voltage _Vb0 of a normal cavity or a diode free of foreign matter. Further, in the case of a diode having a cavity or foreign matter below, it has been clarified by a simulation by the present inventors that the breakdown voltage _Vbn of the diode decreases when the position where the cavity or foreign matter exists is made shallow. It is sufficient that at least one cavity 24 exists in the space charge region 25, and the cavity 24 may be singular or plural. A similar effect exists not only on foreign matter but also on a cavity whose inner wall surface is covered with oxide.

The vicinity of the cavity taken into the depletion layer of the pn junction is locally broken down due to a high electric field.
As a result, the reverse breakdown voltage decreases. When this element is used, the circuit can be protected by the forward characteristic of the pn junction on the low voltage side and by the reverse breakdown on the high voltage side.

The existence of the cavity 24 in the space charge region 25 affects the reverse characteristics of the diode 20 according to the discovery of the present inventor. And about this phenomenon, Electrochemical Society Procee
dings, semiconductor silicon1998, pp1594-1563, and show by experiments and simulations the fact that the presence of oxygen precipitates in a substrate causes kink characteristics to appear in the reverse characteristics of a diode.

Next, the electrical characteristics of the input protection circuit of the present invention
Is shown in FIG. The potential applied to the input signal line (hereinafter, signal
Signal potential) V_inIs the ground potential V_ssAnd power supply potential V_ddSignal between
, That is, the signal potential V_inIs the breakdown voltage V
_bnIn the following case, the signal potential V _inTo the input gate
Applied.

[0047] However, the signal potential V _in is, the diode of the input protection circuit unit becomes equal to or higher than the breakdown voltage V _bn breaks down, the breakdown voltage V _bn over voltage is not applied to the input gate.

As described above, since the breakdown voltage V _bn of the diode is determined by the depth of the cavity, by controlling the position of the cavity, if the breakdown voltage V _bn of the diode is appropriately selected, good protection characteristics can be obtained. Is obtained.

[0049] For example, the power supply potential V _dd of devices now considered as 2.5V, the power supply potential V _dd of external devices connected thereto to 3.3V. In the conventional input protection circuit, excessive current continues to flow through the diode, and the protection circuit is destroyed. External circuits also consume unnecessary power.

However, if the reverse breakdown voltage V _bn of the diode in the protection circuit of the present invention is set to 4 V,
No excessive current flows through the protection circuit, so there is no destruction. When a voltage of 4 V or more is applied in some accident, the input gate is protected by the reverse breakdown of the diode.

In the case of a diode junction used in a conventional protection circuit, it is designed to have a breakdown voltage V _b0 which is about twice the power supply potential. The breakdown voltage V _b0 in this case becomes 6.6 V, if this much input voltage is applied, the input gate is destroyed.

Next, a method of forming a cavity below a diode used in the present circuit will be described with reference to FIG. FIG. 3 is a process cross-sectional view showing a process for manufacturing a diode used in the input protection circuit according to the first embodiment of the present invention. First, as shown in FIG. 3A, a photoresist pattern 31 is formed on a silicon substrate 21 using a lithography technique, and anisotropic etching is performed on the silicon substrate 21 using the photoresist pattern 31 as a mask.
For example, groove 3 is formed by patterning using RIE.
Form 2 Next, as shown in FIG. 3B, after removing the photoresist pattern 31, a cavity 24 is formed in the silicon substrate 21 by high-temperature annealing in a non-oxidizing atmosphere, for example, a 100% hydrogen atmosphere. Then, as shown in FIG. 3C, the heat treatment at a high temperature is continuously performed to flatten the surface of the silicon substrate 21.
The flattening of the surface of the silicon substrate 21 may be performed by laminating a silicon epitaxial film, or may be performed by CMP.
(Chemical Mechanical Polishing). After the planarization, an element isolation insulating film and impurity diffusion are performed to form a diode.

When the cavity 24 is formed, the depth and size of the cavity can be controlled simultaneously by changing the depth and width of the groove. Further, in order to cover the inner surface of the cavity with the oxide or to fill the cavity with the oxide, annealing may be performed in an oxygen atmosphere after the step of forming the groove.

Next, the relationship between the aspect ratio of the groove and the cavity formed in this embodiment will be described. In FIG.
The result when annealing is performed on grooves having different aspect ratios is shown in a schematic diagram. FIG. 4A shows a groove shape before the heat treatment. Here, the aspect ratios of the grooves 41, 42 and 43 are 1, 5 and 10, respectively.

For these grooves 41 to 43, 10OO
FIG. 4B shows the result of heat treatment at 10 ° C. for 10 minutes in a hydrogen atmosphere at 10 Torr. FIG. 4B shows a state where the surface of the substrate 40 is flattened. As shown in FIG. 4B, grooves 4 having an aspect ratio as small as 1
In the case of 1, a cavity cannot be formed. On the other hand, in the case of the groove 42 having an aspect ratio of 5, one cavity 44 is formed below the groove. In the case of the groove 43 having a larger aspect ratio, three cavities 45 are formed at equal intervals from below the groove.
Is formed. It can be seen that in order to form a cavity as described above, it is necessary to form a groove having an aspect ratio of a certain degree or more.

The number of cavities formed below the diode constituting the input protection circuit is not limited to one, and a plurality of cavities 24a to 24d may be formed as shown in FIG. In this case, variations in characteristics are reduced. There is an advantage that the voltage applied to the input gate can be kept lower by increasing the current flowing when the reverse breakdown occurs. In FIG. 5, the same parts as those in FIG. 1 are denoted by the same reference numerals. Note that this embodiment is not limited to the above-described embodiments.

In the first and second embodiments, the case where the other end of the diode is connected to the ground potential has been described.
A configuration in which the other end of the diode is connected to the power supply potential is also possible.

In the following embodiments, a method for manufacturing a bonded SOI substrate that facilitates controlling the thickness of a semiconductor layer of the SOI substrate will be described.

[Second Embodiment] FIG. 6 is a process sectional view showing a manufacturing process of an SOI substrate according to a second embodiment of the present invention. First, as shown in FIG. 6A, after a silicon oxide film 61 is deposited on a first single crystal silicon substrate 60, the silicon oxide film 61 is formed using a resist formed in a desired pattern as a mask. On the other hand, patterning is performed by performing anisotropic etching. After removing the resist,
Using the silicon oxide film 61 as an etching mask, the first single crystal silicon substrate 60 is anisotropically etched to form a groove 62 having a depth of about 5 μm.

Next, as shown in FIG. 6B, the first single crystal silicon substrate 60 is subjected to a heat treatment at 1100 ° C. in an H ₂ atmosphere which is a non-oxidizing atmosphere. By performing the heat treatment, the opening of the groove 62 of the first single-crystal silicon substrate 60 is closed by the surface migration of Si, and the cavity 6 is formed in the first single-crystal silicon substrate 60.
3 is formed. Thereafter, the silicon oxide film 61 is peeled off with, for example, a diluted hydrofluoric acid aqueous solution.

Next, as shown in FIG. 6C, the first single-crystal silicon substrate 60 and the second single-crystal silicon substrate 65 on which the silicon oxide film 64 is formed in advance are Paste it through.

Next, as shown in FIG.
The first single crystal silicon substrate 60 where 3 is present is cut away by, for example, CMP. At this time, in the region where the cavity 63 exists, the density of the Si to be removed changes.
Polishing rate changes. In a CMP apparatus, a change in the polishing rate can be detected as a change in the torque because the polishing rate is inversely proportional to the torque of the motor that rotates the table. In other words, the polishing time to the region where the cavity exists can be monitored by the change in the polishing rate,
In addition, the remaining film of the first single-crystal silicon substrate 60 (semiconductor layer of the SOI substrate)
Can be controlled. The depth at which the cavity 63 exists can be controlled by the etching depth of the silicon substrate and the heat treatment conditions. Therefore, a desired semiconductor layer thickness can be defined by controlling the depth at which the cavity is formed. Further, FIG.
As shown in (e), the surface of the first single-crystal silicon substrate 60 is polished so as to eliminate irregularities on the surface.

As described above, by using the present invention, it is possible to form a bonded SOI substrate having excellent controllability of the thickness of the semiconductor layer. In the present embodiment,
Although the pattern shape of the groove formed in the silicon substrate was not touched, it may be either a line shape or a hole shape. Further, in bonding the silicon substrates, the bonding may be performed after the surface of the silicon substrate in which the cavities are embedded is oxidized by thermal oxidation.

[Third Embodiment] FIG. 7 is a process sectional view showing a manufacturing process of an SOI substrate according to a third embodiment of the present invention. First, as shown in FIG. 7A, as in the second embodiment, a silicon oxide film 61 is deposited on a first single-crystal silicon substrate 60, and then a groove 62 is formed. Then
As shown in FIG. 7B, the first single crystal silicon substrate 6
For example, after forming a silicon nitride film 73 on the entire surface,
The silicon nitride film 73 is etched back using phosphoric acid to leave the silicon nitride film 73 only in the groove 62.

[0065] Then, as shown in FIG. 7 (c), by heat treatment of 1100 ° C. in an H ₂ atmosphere, Si
Causes surface migration. By this heat treatment, a structure in which the silicon nitride film 73 is embedded in the substrate 60 is obtained. Thereafter, the silicon oxide film 61 is peeled off with, for example, a diluted hydrofluoric acid aqueous solution.

Next, as shown in FIG. 7D, a first single crystal silicon substrate 60 and a new silicon oxide film 64 are formed.
Are bonded together with the surface of the second single crystal silicon substrate 65 formed on the surface. Next, as shown in FIG. 7E, the substrate 60 on which the silicon nitride film 73 is present is
For example, it is cut from the back side by CMP. At this time,
In the region where the silicon nitride film 73 exists, the density of Si to be removed changes, and the polishing rate of CMP changes, so that the remaining film of the silicon substrate 60 can be controlled. Further, as shown in FIG. 7 (f), the surface is polished until the silicon nitride film disappears. Therefore, according to the present invention, it is possible to provide a method for manufacturing a bonded substrate having excellent controllability of the thickness of a semiconductor layer.

In this embodiment, a silicon nitride film is selected as a material to be embedded in the substrate. However, it is possible to embed a material having a different polishing rate into single crystal silicon. Further, in this embodiment, wet etching using phosphoric acid is selected as a method for leaving the silicon nitride film after silicon etching, but it is also possible to combine dry etching, CMP and the like.

[Fourth Embodiment] FIGS. 8 and 9 are sectional views showing the steps of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

First, as shown in FIG. 8A, as in the second embodiment, after a silicon oxide film 61 having a predetermined pattern is formed on a single-crystal silicon substrate 60, the silicon substrate is etched to form a silicon oxide film 61. Then, a groove 62 of about 5 μm is formed.

Further, as shown in FIG. 8 (b), by performing a heat treatment at 1100 ° C. in an H ₂ atmosphere,
By the surface migration, a cavity 63 existing in the substrate 60 is formed. Thereafter, the silicon oxide film 61 is peeled off with, for example, a diluted hydrofluoric acid aqueous solution.

Next, as shown in FIG. 8C, element isolation and MOS transistors are formed on the silicon substrate 60 having the cavity 63 therein. Further, a layer including a wiring and a contact for electrically connecting the transistors is formed thereon. Thus, the semiconductor element layer 81 is formed on the silicon substrate 60 in which the cavity 63 is buried.

Thereafter, as shown in FIG. 8D, a silicon oxide film 82 formed on the single crystal silicon substrate 83 is formed on the surface of the first single crystal silicon substrate 60 opposite to the semiconductor element layer 81. paste. If there is no problem in adhesion, the silicon substrate 83 may be directly bonded to the surface of the first single crystal silicon substrate 60 on the side opposite to the semiconductor element layer 81 without using the silicon oxide film 82.

Next, as shown in FIG.
The first single crystal silicon substrate 60 where 3 is present is cut from the back side to the region where the cavity 63 is present by, for example, CMP. At this time, in the region where the cavity 63 exists, the density of Si to be cut changes, and the polishing rate of CMP changes, so that the remaining film of the silicon substrate 60 can be controlled. And further, as shown in FIG.
The surface of the first single crystal silicon substrate 60 is polished so that surface irregularities are eliminated.

Thereafter, as shown in FIG. 9G, the surface of the silicon oxide film 84 formed on the surface of the single crystal silicon substrate 85 is bonded to the polished surface of the first single crystal silicon substrate. wear. Next, as shown in FIG. 9H, the silicon substrate 83 and the silicon oxide film 82 are removed by, for example, polishing.

As described above, by using the present invention, an SOI structure can be formed even after a semiconductor device is formed on a substrate.

[Fifth Embodiment] FIG. 10 shows a fifth embodiment of the present invention.
1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. As shown in FIG. 10, a MOSFET is formed on the surface of a p-type silicon substrate 101. The MOSFET and other elements are separated by an element isolation region 102.
The MOSFET region has a gate oxide film 103 formed on the surface of the semiconductor substrate 101, a gate electrode 104 having a gate length of, for example, 0.2 mm formed thereon, and an impurity formed by using the gate electrode 104 as a mask and having an impurity of 1 × 10 ²⁰ cm. ^-3
A diffusion layer 105 is formed which is heavily doped. In FIG. 10, the wiring layer, the protective film layer of the element, and the like are omitted.

The lower part of the MOSFET formed on the surface of the semiconductor substrate 101 made of, for example, silicon, and M
At least one cavity 106 having a diameter of 0.2 μm exists at a depth of 0.6 μm, which is a position deeper than the depletion layer region formed by the OSFET. Note that the inner wall of the cavity 106 may be covered or filled with oxide.

The semiconductor substrate 101 around the cavity 106 usually has a strain field. In some cases, a minute dislocation defect or the like may be present. In any case, contaminant metals such as iron and copper are gettered in the strain field formed in the semiconductor substrate 101 by the cavity 106. Therefore, the surface of the semiconductor substrate 101 can be kept clean.

The shape of the cavity 106 may be a sphere, a regular octahedron, a disk, or a deformation or combination thereof. The strain field created by the cavity is more important than the shape itself.

The size D _{i of the} cavity and the existing depth D _p are:
It is an important parameter of the strain field formed. Cavity 10
When the strain field formed by 6 reaches the surface of the semiconductor substrate 101, the contaminant metal impurities caught around the cavity 106 may affect the device characteristics. Also, the cavity 106
May itself affect the electrical characteristics of the element formed on the surface.

The magnitude of the strain field existing around the cavity 106 substantially depends on the size of the cavity 106. Generally, when the distance is affected by a distance of 3 to 5 times the size of the cavity 106, You can think.

Although it is difficult to define the size of the cavity 106 depending on the shape, the diameter of a sphere having a shape substantially equal to the volume of the cavity 106 is used. In this embodiment,
The size D _{i of the} cavity is 0.2 μm, and the depth D _p is 0.6 μm. In this case, the strain field of the cavity does not affect the surface of the semiconductor substrate. If the size D _{i of the} cavity is about 0.2 μm, the depth D
_p is O. Any depth may be used as long as the depth is 6 μm or more, but the gettering effect increases as the depth decreases. Depending on the diffusion length of the metallic impurities, present depth D _p of the cavity 106 is larger effect if 10μm or less.

[Sixth Embodiment] A sixth embodiment of the present invention will be described with reference to FIG. Description of the same parts as in FIG. 10 is omitted. The feature of this embodiment is that the plurality of cavities 10
6 (106a, 106b) exist adjacent to each other. The depth at which the cavity 106 exists is 1 μm. The distance L between the two cavities 106a and 106b is 0.4 μm.
m. Although a dislocation defect exists between the two cavities 106, the dislocation defect does not reach the semiconductor surface.

When the distance L between adjacent cavities is reduced,
The strain fields of the cavities can interfere with each other to form a larger strain field. In some cases, transition between cavities may occur. This transition enables gettering of the impurity metal more strongly. In addition, since the stress on the surface of the semiconductor substrate is alleviated by this transition, the electrical characteristics of the device are improved.

The problems of the structure of the present embodiment are that the generated dislocations are located on the surface of the semiconductor substrate and deteriorate the electrical characteristics of the device. The condition that the transition does not reach the semiconductor substrate surface is that the distance between the cavities is smaller than the cavity depth. Although the depths of the cavities may vary slightly, it is preferable that the cavities are substantially uniform. Note that even if the depths of the cavities vary, it is considered that a difference in depth within a difference of about the size of the cavities is permissible and may be regarded as substantially the same depth.

[Seventh Embodiment] FIG. 12 shows a seventh embodiment of the present invention.
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. FIG. 12 is a cross-sectional view of the vicinity of the surface of the semiconductor device. The device is the same as that shown in FIGS.

An example when a plurality of cavities exist is shown.
In this case, cavities having a size of 0.1 μm are arranged at a depth of 0.6 μm and a position of 1 μm at an interval of 0.4 μm. By forming such a large number of cavities, a metal impurity can be gettered more strongly. When viewed from the cross section of the device, it is preferable that the cavities are aligned in the horizontal and vertical directions in order to uniformly control the occurrence of defects such as dislocations.

FIG. 13 is a plan view showing a cavity seen through the surface of the semiconductor substrate. Patterns of elements and the like are omitted. Here, a cavity 136 (136) having a size of 1 μm is used.
a to 136i) are arranged on the array at an equal interval of 10 μm. If the gettering capabilities of the individual cavities are sufficiently high, it is also possible to increase the spacing in this way. It is also an effective method to prepare a semiconductor substrate having such a cavity as a standard and use it in common for the manufacture of various semiconductor devices in consideration of economic efficiency.

FIG. 14 shows a semiconductor chip 141. Most of the center of the chip 141 is an element forming region 142 in which elements are arranged. Around the chip 141, a dicing area 1 which is a cutting margin for cutting a chip from a wafer.
There are 43. A cavity 146 is arranged in the dicing region 143. This is effective in the case of a metal having a relatively high diffusion rate such as copper. The influence of the presence of the cavity 146 on the device characteristics can be avoided by the above-described method. However, according to the arrangement of the present invention, a semiconductor device can be manufactured without considering the influence on the elements at all.

FIG. 15 is a plan view of the cell structure of the DRAM. Adjacent to element region 151, trench capacitor portion 1
52 are present. The cavity 156 is disposed near the center of the element region 151.

FIG. 15A is a sectional view taken along the line AA ′ of FIG.
(B). A trench capacitor section 152 exists adjacent to the element region 162 of the semiconductor substrate 161. The trench capacitor portion 152 includes a capacitor insulating film 163,
It consists of a storage node 164. Other structures are omitted. The depth of trench capacitor portion 152 is 6 μm, and cavity 156 is formed at a position of 4 μm in depth. In FIG. 15B, reference numeral 165 denotes an element isolation insulating film.

If the cavity 156 is arranged at an arbitrary position, it contacts the trench capacitor portion. Therefore, the cavity 156 must be arranged in a portion other than the trench capacitor portion 152. Semiconductor devices sometimes use a process with a deep structure such as a trench. By placing a cavity at a position shallower than this deep structure, electrical characteristics such as junction leakage characteristics can be significantly improved. Can be. For example, it leads to improvement in device performance such as improvement in retention characteristics of DRAM.

The formation of the cavities or foreign substances serving as gettering sites is the same as the method described in the first embodiment, and will not be described here.

According to the present embodiment, the intrinsic gettering, which was conventionally difficult to control due to the oxygen concentration of the semiconductor substrate and the heat history of the manufacturing process, is replaced by the gettering and lithography means, the substrate etching means, and the annealing means.
You now have full control over the size, location, and density of your site.

Further, if the substrate on which the getter link site has been formed in advance is facilitated and stocked, the getter link site can be obtained.
The manufacturing time required to form the site can be substantially reduced. It can be used for production of various varieties without considering gettering, and cost can be reduced.

The present invention is not limited to the above embodiment, but can be implemented in various modifications without departing from the scope of the invention.

[0097]

As described above, according to the present invention, since a reverse breakdown voltage of a diode is reduced by forming a cavity or a foreign substance in a semiconductor substrate below a junction diode, only one kind of diode can be used. An input signal higher than the internal voltage can be received.

According to another aspect of the present invention, a cavity or foreign matter can be formed at a predetermined depth by annealing after forming a groove, and by detecting a polishing rate,
It is easy to control the thickness of the semiconductor layer.

According to still another aspect of the present invention,
By annealing after forming the groove, it is possible to form a gettering site which is formed of a cavity or a foreign substance at a predetermined position and depth and does not depend on the heat history of the manufacturing process.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an input protection circuit according to a first embodiment.

FIG. 2 is a characteristic diagram showing electrical characteristics of the input protection circuit shown in FIG.

FIG. 3 is a process sectional view illustrating a method of manufacturing a cavity formed below a diode constituting the input protection circuit illustrated in FIG. 1;

FIG. 4 is a sectional view showing a cavity formed when annealing is performed on grooves having different aspect ratios.

FIG. 5 is a diagram showing a modification of the first embodiment.

FIG. 6 is a process cross-sectional view showing a manufacturing process of the SOI substrate according to the second embodiment.

FIG. 7 is a process cross-sectional view showing a manufacturing process of the SOI substrate according to the third embodiment.

FIG. 8 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the fourth embodiment.

FIG. 9 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device according to the fourth embodiment;

FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment.

FIG. 11 is a sectional view showing a configuration of a semiconductor device according to a sixth embodiment;

FIG. 12 is a sectional view showing a configuration of a semiconductor device according to a seventh embodiment;

FIG. 13 is a plan view of a semiconductor substrate according to a seventh embodiment, as seen through a cavity from the surface of the semiconductor substrate.

FIG. 14 is a plan view showing the configuration of a chip according to a seventh embodiment.

FIG. 15 is a plan view showing a cell structure of a DRAM according to a seventh embodiment.

FIG. 16 is a circuit diagram showing a configuration of a conventional input protection circuit.

FIG. 17 is a characteristic diagram showing electrical characteristics of the input protection circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Input pad 12 ... Input protection circuit 13 ... Input gate 14 ... Input signal line 20 ... Junction diode 21 ... Type silicon substrate 22 ... Element isolation insulating film 23 ... High concentration impurity region 24 ... Cavity 25 ... Space charge region 31 ... Photo Resist pattern 32 groove 60 first single crystal silicon substrate 61 silicon oxide film 62 groove 63 cavity 64 silicon oxide film 65 second single crystal silicon substrate 101 semiconductor substrate 103 gate oxide film 104 Gate electrode 105 ... Diffusion layer 106 ... Cavity

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/8242 H01L 29/90 D 27/12 29/91 A 29/786 C 21/336 29/866 21 / 329 29/861 (72) Inventor Kazuaki Nakajima 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa F-term (reference) 5F038 BH04 BH05 CA13 CD02 CD04 EZ01 EZ06 EZ15 EZ17 EZ20 5F048 AA02 AC10 BA01 BD01 CC06 CC12 CC15 CC18 5F083 AD15 GA30 LA02 5F110 AA30 CC02 DD05 DD25 FF02 GG02 GG12 NN62 QQ11 QQ16 QQ28

Claims (9)

[Claims] A first conductive type semiconductor substrate having one end connected to a signal line connecting an input pad to which an input signal is input and an input gate, and the other end connected to a ground potential or a power supply potential; A junction diode including a second conductivity type diffusion layer formed on the surface of the first conductivity type semiconductor substrate; and a junction diode formed in the first conductivity type semiconductor substrate below the junction diode. An input protection circuit comprising a cavity or a foreign substance made of a different material from the semiconductor substrate embedded in the cavity. 2. The input protection circuit according to claim 1, wherein the cavity or the foreign matter is formed at a position that can contact a space charge region formed by the junction diode. 3. A step of forming a groove in a semiconductor substrate, and heating the semiconductor substrate to move atoms or molecules constituting the semiconductor substrate to cover an opening of the groove and form a cavity in the substrate. A step of forming; a step of flattening the surface of the semiconductor substrate; a step of bonding the semiconductor substrate and a substrate having an insulating film formed on at least the surface so as to interpose the insulating film; Polishing the surface of the semiconductor substrate while measuring the temperature, and removing the cavity. 4. A step of forming a groove in a semiconductor substrate, a step of selectively forming a material having a different polishing rate from that of the semiconductor substrate in the groove, and heating the semiconductor substrate to form atoms forming the substrate. Or a step of selectively forming the foreign matter inside the semiconductor substrate by moving molecules to cover the opening of the groove; and a step of flattening the surface of the semiconductor substrate; Bonding a substrate on which an insulating film is formed through the insulating film, and polishing the surface of the semiconductor substrate while measuring a change in polishing rate to remove the foreign matter. A method for manufacturing a semiconductor substrate, comprising: 5. A step of forming a groove in a semiconductor substrate, and heating the semiconductor substrate to move atoms or molecules constituting the semiconductor substrate, thereby closing an opening of the groove, and forming a cavity in the substrate. A step of forming; a step of flattening the surface of the semiconductor substrate; a step of forming a semiconductor element on one surface of the semiconductor substrate; and a step of bonding one surface of the semiconductor substrate to a first base. Polishing the other surface of the semiconductor substrate while measuring a change in the polishing rate to remove the cavity; and a polished surface of the semiconductor substrate and an insulating film formed on a surface of the second base. And a step of peeling the first substrate. 6. A step of forming a groove in a semiconductor substrate, a step of selectively forming a material having a different polishing rate from that of the semiconductor substrate in the groove, and heating the semiconductor substrate to form atoms forming the substrate. Or moving the molecules to cover the opening of the groove and selectively forming the foreign matter inside the semiconductor substrate; and flattening the surface of the semiconductor substrate; and one of the semiconductor substrates. Forming a semiconductor element on a surface; bonding one surface of the semiconductor substrate to a first base; polishing the other surface of the semiconductor substrate while measuring a change in polishing rate; A semiconductor, comprising: a step of removing foreign substances; a step of bonding a polished surface of the semiconductor substrate to an insulating film formed on a surface of a second base; and a step of peeling the first base. Device manufacturing method. 7. A semiconductor device formed on a surface of a semiconductor substrate, and one or more semiconductor devices formed below the semiconductor device in the semiconductor substrate and deeper than a depletion layer region formed by the semiconductor device. A semiconductor device comprising a cavity or a foreign substance embedded in the cavity. 8. A step of forming a groove in the surface of the semiconductor substrate, heating the semiconductor substrate to move atoms or molecules constituting the semiconductor substrate, and to cover the opening of the groove, A method of manufacturing a semiconductor device, comprising: forming a cavity therein; flattening the surface of the semiconductor substrate; and forming a semiconductor element on the surface of the semiconductor substrate. 9. A step of forming a groove in a surface of a semiconductor substrate, a step of selectively forming a material forming a foreign substance in the groove, and heating the semiconductor substrate to form atoms forming the semiconductor substrate. Alternatively, a step of closing the opening of the groove by moving molecules to form the foreign matter in the semiconductor substrate; a step of flattening the surface of the semiconductor substrate; and forming a semiconductor element on the surface of the semiconductor substrate. A method of manufacturing a semiconductor device.