JP2000267776A - Centralized bus communication equipment and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a centralized bus communication equipment and a method capable of performing high speed communications by reducing the load capacity driven by each electronic part with a simple constitution. SOLUTION: A one-chip semiconductor integrated circuit is provided with an internal bus, and this semiconductor integrated circuit is provided with bus buffers 710-750 for realizing communications through the internal bus. Each electronic part is connected with the bus buffers 710-750 in a star form so that bus type communications are performed only inside the semiconductor integrated circuit. Therefore, it is possible to realize high speed communications by reducing the load capacity driven by each electronic part with a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a centralized bus communication device and a centralized bus communication method, and more particularly to a centralized bus communication device and a centralized bus communication method for enabling high-speed bus-type communication between electronic components. .

[0002]

2. Description of the Related Art In recent years, CPUs have been used in computer systems.
Has reached an operating speed of about 400 to 500 MHz, and is further improved day by day. However, the operating speed of the bus is about 66 to 100 MHz,
The progress has been slower than the increase in the operating speed of U. Here, if the operation of the bus is slow even if the operation of the CPU is fast,
The operation of the CPU is restricted by the bus, and the processing speed of the entire system is reduced. Therefore, it is important to improve the operation speed of the bus in order to improve the processing speed of the entire system.

FIG. 4 shows an example of the configuration of the most general computer board. In FIG. 4, a CPU 902 and memories 903, 90
4 and electronic components such as I / Os 905 and 906. All of these electronic components are connected by a bus 908 to perform bus-type communication.

That is, each electronic component of the CPU 902 to the I / O 906 has a bidirectional buffer, and each electronic component sends a signal to the bus 908 by controlling the bidirectional buffer with a control signal. The signal is received.

[0005] In the above-mentioned general configuration, a technique for improving the operation speed of the bus is not adopted. In view of the above, there has been conventionally devised a technique for improving the operation speed of a bus, and an example thereof is a technique disclosed in Japanese Patent Application Laid-Open No. 9-274527. FIG.
1 is a configuration example of a bus wiring system according to the technology disclosed in Japanese Patent No. 274527. In the figure, the electronic components are group A,
The three groups B and C are formed, and these three groups are connected by ring-shaped buses 908a to 908c. These buses are connected to switches TS1 to TS3.
Are combined and separated from each other.

In such a configuration, the control circuit 910 includes:
When data is exchanged only in one block group, all switches TS1 to TS3 are turned off. On the other hand, for example, when exchanging data between the group A and the group B, the control circuit 10 turns on only the switch TS1. When the bus is divided and communication is performed using only necessary buses, the wiring capacity is reduced as compared with the case where the bus is not divided.

[0007]

However, the above-mentioned conventional centralized bus communication device has the following problems. That is, in general, the load capacity that each electronic component must drive is the sum of the bus wiring capacity and the terminal capacity, and the operating speed of the bus is inversely proportional to the load capacity.
Here, in the former technique, since the bus is routed from end to end on the computer board, the wiring length increases, and the wiring capacity increases in proportion thereto.

[0008] The way of wiring differs depending on the method of arranging each component on the computer board.
The wiring length in the case of FIG. 4 is approximately the width × (2/3) +
Vertical width x (1/4) x number of parts. Since the terminal capacitances are all the terminal capacitances of the components connected to the bus, the terminal capacitances increase in proportion to the number of components. Therefore, in the former conventional example, the bus cannot be driven at high speed.

In the latter technique, only the bus required for communication is used, so that the wiring capacity is reduced. However, since it is necessary to determine which block performs communication and perform switch control, the control is performed. The circuit is required and the system becomes complicated. Further, when the number of divided buses is increased to four or more, a bypass for connecting non-adjacent buses is required, which further complicates the system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a centralized bus communication apparatus and a centralized bus communication capable of performing high-speed communication by reducing the load capacity driven by each electronic component with a simple configuration. The aim is to provide a method.

[0011]

According to a first aspect of the present invention, there is provided a signal line in which signal lines from a plurality of electronic components provided on a substrate are connected in a concentrated manner to form a star. A connection terminal, a bus line arranged in a region where signal lines are concentrated in a star shape at a signal line connection terminal, and bidirectional communication can be performed between the bus line and the concentrated signal line. And communication control means.

That is, in the present invention, a plurality of electronic components for communication are arranged on one substrate, and the signal line connection terminals connect these signal lines to one place and connect them in a star shape. A bus line is provided at a portion where these signal lines are connected in a concentrated manner, and the communication control means enables bidirectional communication between the bus line and the concentrated signal line. .

Here, the electronic component is a device that generally communicates via a bus line in a computer device, and is an I / O for communicating with a CPU, a memory, and an external device.
O and the like. Here, in the conventional bus-type communication, a sufficiently large driving force is required so that each electronic component can also transmit data to an electronic component arranged at a distant portion in consideration of a long bus line.

However, in the present invention, the bus lines are arranged at one place concentrated in a narrow area, and the distance is short. Therefore, the wiring capacity of this bus line is so small that it can be ignored. Therefore, the wiring capacitance is greatly reduced.

[0015] Further, as an example suitable for performing bus-type communication in one centralized location as described above, in the invention according to claim 2, the centralized bus communication device according to claim 1 is connected to a signal line connection. The terminal, the bus line, and the communication control means are constituted by a one-chip semiconductor integrated circuit.

That is, the signal line connection terminal, the bus line, and the communication control means in the present invention are constituted by a one-chip semiconductor integrated circuit, and the signal lines from each electronic component are connected to the one-chip semiconductor integrated circuit. Is input to the signal line connection terminal, which is the input terminal of. Therefore, the one-chip semiconductor integrated circuit is the above-mentioned concentrated area.

According to a third aspect of the present invention, there is provided a centralized bus communication device according to the second aspect, wherein bus type communication is enabled using the one-chip semiconductor integrated circuit. Has a configuration in which an internal bus is provided in a one-chip semiconductor integrated circuit, and bus-type communication is performed only within the semiconductor integrated circuit.

That is, this one-chip semiconductor integrated circuit has an internal bus line, and performs bus-type communication only in an area inside the semiconductor integrated circuit, which is very small compared to the size of a conventional bus line. Therefore, this bus line has almost negligible wiring capacity as compared with the conventional bus line.

Further, the communication control means only has to be an interface between the internal bus line and the signal line connection terminal and control each electronic component so as to perform bus-type communication via the internal bus line. As a specific example of the configuration, the invention according to claim 4 is the centralized bus communication device according to any one of claims 1 to 3, wherein the communication control means controls a signal between each electronic component and a bus line. Is provided with a plurality of bidirectional buffers for transmitting and receiving data.

That is, in general bus-type communication,
A bidirectional buffer is provided as an interface between the bus line and each electronic component. A signal is transmitted to and received from the bus line while a control signal is input to the bidirectional buffer. Therefore, in the present invention, a bidirectional buffer for communicating each electronic component is constituted by the semiconductor integrated device of the one-chip semiconductor integrated circuit. Therefore, each electronic component only needs to connect necessary signal lines to this one-chip semiconductor integrated circuit.

Further, when performing bus-type communication, generally, the bit width of a signal line required by each electronic component is determined. Therefore, as a specific example suitable for coping with such a situation, the invention according to claim 5 is directed to the centralized bus communication device according to claim 4, wherein each of the bidirectional buffers included in the communication control means includes It is configured to be a buffer having a minimum required bit width for each electronic component to be manufactured.

That is, by forming each of the bidirectional buffers provided in the communication control means with a buffer having a minimum bit width for each of the connected electronic components, a one-chip semiconductor integrated circuit can be realized. There is no need to configure useless signal lines, and there is no need to configure useless elements for the bidirectional buffer.

As described above, the method of connecting the signal lines from the respective electronic parts in a star shape at one place and performing the bus-type communication only at such a position can be regarded as the invention of the method. For this reason, the invention according to claim 6 is a centralized bus communication method for connecting a plurality of electronic components provided on a substrate to a buffer and performing bidirectional communication via the buffer. A bidirectional buffer and an internal bus line are formed in a semiconductor integrated circuit, the electronic components are connected in a star configuration to the one-chip semiconductor integrated circuit, and bus-type communication is performed only within the one-chip semiconductor integrated circuit. The configuration allows bidirectional communication between components. In other words, there is no difference in that the present invention is not necessarily limited to a substantial device and is also effective as a method.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a board using a centralized bus communication device according to the present invention. In FIG.
CPU 0, memories 300 and 400, and I / O
500 and 600 and a centralized bus communication device 700 are provided. Each of these electronic components has a signal line 810.
At 850, the connection is connected in a star shape to the connection terminals of the centralized bus communication device 700.

Here, the CPU 200 is a central processing unit that controls the entire computer system while performing bus-type communication using the centralized bus communication device according to the present invention.
The memories 300 and 400 are electronic components capable of storing information, and may be configured as a read-only or read-write memory, such as a RAM or a ROM.

The I / Os 500 and 600 are interfaces that enable communication with electronic components provided outside the computer board 100, and are connected to, for example, a hard disk and a display. Therefore, this I / O50
0,600 enables two-way communication with these external electronic components.

FIG. 2 is a diagram showing a schematic configuration inside the centralized bus communication device 700. In the figure, the centralized bus communication device 700 is constituted by a one-chip semiconductor integrated circuit,
Bus buffers 710 to 750... Are provided by the number of electronic components to be connected, and these bus buffers 710 to 750 are connected to the bus line 800.

By transmitting and receiving data to and from the bus line 800 via the bus buffers 710 to 750,
Each electronic component connected to the bus buffers 710 to 750 can communicate bidirectionally. further,
Each of the bus buffers is provided with a bidirectional buffer corresponding to the number of signal lines.
It is shown as 1. That is, the bus buffer 710 is composed of a plurality of bidirectional buffers, one of which is the bidirectional buffer 711, and the bus buffer 710 has an X bus width by collecting X bidirectional buffers 711. .

In this bidirectional buffer, the transmission and reception timing of data to and from the bus line 800 is controlled by a predetermined control signal, and data communicated by each signal line is transmitted only through the bus line 800 inside the centralized bus communication device 700. Type communication is performed. In this sense, the bus buffers 710 to 750 constitute the communication control means.

As described above, these bus buffers 710
Since signal lines from external electronic components are connected to 750, each signal line is physically separated from the bus line 800 and electrically connected. Therefore, in the present invention, the load capacity driven by each electronic component disposed on the computer board is minimized, and the bus can be driven at a high speed.

Hereinafter, the load capacity of the CPU 200 will be described more specifically. In FIG. 1, a signal line 810 from the CPU 200 disposed on the computer board 100 is connected only to the centralized bus communication device 700 disposed at the center of the computer board 100.

Here, the wiring capacity of the bus line 800 in the centralized bus communication device 700 is so small that it can be ignored. Therefore, the load capacity that must be driven by the CPU 200 here depends on the wiring capacity of the signal line 810 between the CPU 200 and the centralized bus communication device 700 and the central bus communication device 700.
Is the sum of the terminal capacities of the bus buffers 710 in the internal memory.

This signal line 810 is connected to the computer board 1
If the computer board 100 is wired from the substantially left end to the approximate center of the computer board 100,
(Vertical width ＾ 2 + width ＾ 2) ＾ (１ ／) / 2. This wiring length is one in which the wiring capacity is greatly reduced as compared with the conventional method in which the bus lines are routed from one end of the computer board to the other.

In the conventional bus wiring system, the terminal capacitances of all the components connected on the bus line are all added, whereas in the configuration of the present invention, only the terminal capacitances of the directly connected centralized bus communication device are added. As a result, the terminal capacity can be greatly reduced. Memory 300, 400 and I
The same applies to / O500 and / O500. here,
Since the operation speed of the electronic components is inversely proportional to the load capacity, the operation speed of the bus is greatly improved as a result of reducing the load capacity driven by each electronic component as described above.

In the above configuration, in order for the CPU 200 to perform transmission, a predetermined information signal is transmitted to the signal line 810. Then, the bus buffer 7 of the centralized bus communication device 700
These information signals are sent to the bidirectional buffer 10, and the contents of these transmission information signals are held in the bidirectional buffer 711 until a predetermined control signal is input to the bidirectional buffer 711 to which one signal line is connected.

Here, when the control signal is input, the information signal held in the bidirectional buffer 711 is transmitted to the bus line 800, and the bidirectional buffer in the bus buffer to which the electronic component of the communication partner is connected is driven. To get this information. Communication is performed by transmitting an information signal from the bidirectional buffer to the electronic component of the communication partner. When receiving by the CPU 200, the CPU 200
However, the situation is the same as long as it operates as the electronic component of this communication partner.

As described above, each of the electronic components performs bus-type communication only with the bus line 800 provided inside the one-chip semiconductor integrated circuit. There is. Therefore, in such a case, as a preferred embodiment, the bus width of the bus buffer may be reduced to a necessary minimum in advance according to the electronic components to be connected.

FIG. 3 is a diagram showing a schematic configuration of the centralized bus communication device in this embodiment. In the figure, a centralized bus communication device 701 composed of a one-chip semiconductor integrated circuit is provided with bus buffers 712 to 741 for the number of electronic components to be connected. 741 is connected to the bus line 801. The bus line 801 has n bits.

Further, each of the bus buffers is provided with a bidirectional buffer for the number of signal lines having a minimum bus width required for the connected electronic components. For example, an electronic component connected to the bus buffer 712 requires n bits as the bus width X, and n bidirectional buffers 713 are provided. The electronic components connected to the bus buffer 741 require x bits (x <n) as the bus width X, and x bidirectional buffers are provided.

That is, in the present embodiment, each bus buffer is provided with only the minimum number of bidirectional buffers necessary for electronic components connected to the bus buffer to perform communication. Even in such a configuration, since each electronic component is connected to the bus line 801 via a bus buffer having a bus width necessary for communication, bidirectional communication can be performed in the same manner as the above operation.

As described above, in the present invention, an internal bus is provided in a one-chip semiconductor integrated circuit, and a bus buffer is provided inside the semiconductor integrated circuit to enable communication via the internal bus. By connecting each electronic component to the bus buffer in a star configuration, bus-type communication is performed only inside the semiconductor integrated circuit. Therefore, with a simple configuration, the load capacity driven by each electronic component can be reduced and high-speed communication can be performed.

[0042]

As described above, in the present invention,
With a simple configuration, the load capacity driven by each electronic component can be reduced and high-speed communication can be performed. Further, according to the invention of claim 2, it is possible to concentrate the places for performing the bus-type communication in one place with a simple configuration.

Further, according to the third aspect of the present invention,
With a simple configuration, the locations for performing bus-type communication can be concentrated in one place. Further, according to the invention of claim 4, bus-type communication can be easily performed inside the semiconductor integrated circuit.

Further, according to the invention of claim 5,
Since it is only necessary to provide the minimum necessary communication path, the number of manufacturing steps of the semiconductor integrated circuit can be reduced. Further, according to the invention of claim 6, it is possible to reduce the load capacity driven by each electronic component with a simple configuration and perform high-speed communication.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a board using a centralized bus communication device according to the present invention.

FIG. 2 is a diagram showing a schematic configuration inside a centralized bus communication device.

FIG. 3 is a diagram illustrating a schematic configuration inside a centralized bus communication device according to a second embodiment.

FIG. 4 is a block diagram illustrating a configuration example of a general computer board.

FIG. 5 is a diagram showing a configuration example of a bus wiring system according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 100 computer board 200 CPU 300, 400 memory 500, 600 I / O 700 centralized bus communication device 710 to 750 bus buffer 711 bidirectional buffer 800 bus line 810 to 850 signal line

Claims (6)

[Claims] 1. A signal line connection terminal for concentrating signal lines from a plurality of electronic components disposed on a substrate and connecting them in a star shape, and a signal line connection terminal in a region where the signal lines are concentrated in a star shape. A centralized bus communication device, comprising: a bus line disposed in the communication line; and communication control means for enabling bidirectional communication between the bus line and the centralized signal line. 2. The centralized bus communication device according to claim 1, wherein the signal line connection terminal, the bus line, and the communication control means are connected to one another.
A centralized bus communication device comprising a semiconductor integrated circuit of a chip. 3. The centralized bus communication device according to claim 2, wherein said centralized bus communication means includes an internal bus in a one-chip semiconductor integrated circuit, and performs bus-type communication only within said semiconductor integrated circuit. A centralized bus communication device characterized by the above-mentioned. 4. The centralized bus communication device according to claim 1, wherein said communication control means includes a plurality of communication units for transmitting and receiving signals between each electronic component and a bus line. A centralized bus communication device comprising a bidirectional buffer. 5. The centralized bus communication device according to claim 4, wherein each of the bidirectional buffers included in said communication control means has a minimum bit width required for each of the connected electronic components. A centralized bus communication device, being a buffer. 6. A centralized bus communication method for connecting a plurality of electronic components provided on a substrate to a buffer and performing bidirectional communication via the buffer, comprising: A buffer and an internal bus line are formed, the electronic components are connected to the one-chip semiconductor integrated circuit in a star configuration, and bus-type communication is performed only inside the one-chip semiconductor integrated circuit, thereby enabling bidirectional communication between the electronic components. A centralized bus communication method characterized in that: