JPS61288254A - Data transmitting and receiving circuit - Google Patents

Abstract

PURPOSE:To make a circuit small-sized and inexpensive by constituting a FIFO with a one-chip microcomputer and a RAM as a buffer provided for data transmission/reception between a CPU and a terminal. CONSTITUTION:When data from a host CPU or terminals 6 and 7 is written in a RAM 3, the write routine of the internal ROM of the one-chip microcomputer 1 is started to write data in the prescribed area of the RAM 3, and the value of a pointer of a write pointer area provided in the internal RAM of the microcomputer 1 is updated by +1. When data to be transmitted to the host CPU or terminals 6 and 7 is read out from the RAM 3, a read routine is started similarly to read out data from a prescribed area of the RAM 3, and the value of a read pointer is simultaneously updated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmitting and receiving circuit for transmitting and receiving data between a CPU and a terminal.

[Conventional technology]

Conventionally, when transmitting and receiving data between a CPU and a terminal,
Since the operating speeds of both are different, a dedicated FIFO device is used as a buffer.

This was done to avoid reducing the processing power of the CPU.

[Problem that the invention seeks to solve]

However, when a dedicated FIFO device is used as a buffer, there are the following drawbacks.

(1) The capacity of one FIFO device is 84x4
It is fixed in bits and s, and even if you try to change the buffer capacity later, it cannot be changed. In other words, the buffer capacity cannot be freely increased or decreased.

(2) Depending on the configuration of the data bus and the size of the buffer capacity, it may be necessary to use two or more dedicated FIFO devices in parallel and connect them in several stages, resulting in limited usage. However, there is a risk that it will occupy a large amount of mounting space. That is, especially when increasing the buffer capacity, the mounting area of the circuit must be sacrificed, making it impossible to miniaturize the circuit.

(3) Since FIFO devices are more expensive than FIFO devices, it is difficult to make them economical.

[Means for solving problems]

The present invention does not use a dedicated FIFO device as a buffer provided when transmitting and receiving data between a CPU and a terminal, but instead uses a one-chip microcomputer and RAM.
By configuring an IFO, the circuit can be made smaller and less expensive.

That is, the data transmitting/receiving circuit of the present invention includes an external RAM as a data buffer, a ROM, and a RAM.
The present invention is characterized by comprising a one-chip microcomputer having means for providing the external RAM with a FIFO function.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data transmitting/receiving circuit according to the present invention.

SIO(Serial Input 0output
): 17 Troller 4 has two boats, R9
Bidirectional communication is performed with the terminal 6.7 via the -2320 signal lines 51+52, and the ROM,
The operating mode is determined by a one-chip microcomputer 1 with a built-in RAM. Data sent and received between the upper CPU (not shown) and the terminal 6.7 is transmitted and received between the upper CPU and the terminal 6.7.
The external RAM 3, which is a buffer between the SI
Writing to and reading from the O controller 4 is performed. In the RAM 3, areas for writing and reading are provided individually and for each terminal 6° and 7°. The internal ROM of the one-chip microcomputer l includes RAM3.
A write routine is started when writing data from the host CPU or data sent from the terminal 6.7 to the RAM 3, and a write routine is started when reading data to be sent from the RAM 3 to the host CPU or the terminal 6.7. A read routine is stored in the internal RAM, and a write control flag that controls writing of data to RAM3, a read control flag that controls reading of data from RAM3, a write pointer, and a read pointer are stored in the internal RAM. A pointer area and a read pointer area are provided.

Next, data from the host CPU or terminal 6 is stored in RAM3.
, 7 will be explained with reference to the flowchart of the write routine shown in FIG.

First, one RAM in the one-chip microcomputer 1
Based on the write control flag in the area, it is determined whether or not data can be written (process 11). If not, the process moves on to other processes; if it is possible, the data is written to a predetermined location in RAM 3, and at the same time Update (+1) the value of the pointer read from the write pointer area provided in the RAM inside the chip microcomputer l (process 12) 0
Next, it is determined whether or not data is written beyond a predetermined area in RAM 3 (step 13), and if not, the updated pointer value is transferred to the area of the write pointer in the one-chip microcomputer l. Store and process! 5) If possible, clear the value of the write pointer. Process 14). Store the pointer value in the write pointer area inside the one-chip microcomputer (Process 15). Next, clear the stored write pointer. Compare the value of the read pointer provided separately in the RAM inside the one-chip microcomputer (processing IB), and if they are equal, set the write control flag to disabled (processing 17). At the time of configuration, it is set as possible.

Finally, the RA inside the one-chip microcomputer 1
The read control flag provided in M is enabled (process 18). In other words, this read control flag allows reading since data has been written, and is disabled at the time of initial setting.

Note that when reading data to be sent from the RAM 3 to the host CPU or data to be sent to the terminal 6.7, the read routine is activated in the same way. Conversely, it is the same as reading the read pointer as the write pointer, the write control flag as the read control flag, and conversely the read control flag as the write control flag.

〔Effect of the invention〕

As explained above, the present invention controls the SIO and sends and receives data between the terminal and the host CPU using a one-chip microcomputer with built-in ROM and RAM, and the host CPU
By providing one memory device instead of using a FIFO device as a buffer between the U and the terminal, and realizing the FIFO function of this memory device with a one-chip microcomputer, the terminal interface circuit can be made smaller and cheaper. This has the effect of realizing economicization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the data transmitting/receiving circuit of the present invention, and FIG. 2 is a flowchart of a write routine. 1: One-chip microcomputer, 2: Data path, 3: RAM. 4: SIO controller, 51+s, : R9-232G compliant signal line. 6.7: Terminal. Patent Applicant NEC Corporation - Agent Patent Attorney Susumu Uchihara 1, 2,' Figure 1 Figure 2

Claims (1)

[Claims] A data transmitting and receiving circuit for transmitting and receiving data between a CPU and a terminal, comprising: an external RAM as a buffer for the data; a ROM;
1. A data transmitting/receiving circuit comprising: a one-chip microcomputer having a built-in RAM and means for providing the external RAM with a FIFO function.