JP2938052B2 - Semiconductor mounting system and semiconductor chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor chip in which a semiconductor integrated circuit is packaged, and a semiconductor mounting system including a plurality of semiconductor chips.

[0002]

2. Description of the Related Art In recent years, a demand for high-speed data transfer in a semiconductor integrated circuit (LSI) mounting system (hereinafter, referred to as a semiconductor mounting system) has been increasing. For that purpose, it is necessary to operate each signal line at a high frequency in the semiconductor mounting system. In order to achieve this, it is necessary to take measures against skew between signals, especially clock skew.

Conventionally, there are the following methods as measures against skew during high frequency operation. One is to provide a pin only on one side (one side) of a semiconductor device (IC chip) (for example, US Pat. No. 5,408,1).
twenty three). If the pins are provided on only one side of the IC chip, the physical lengths of the signal lines from the controller (master chip) to the IC chip can be made uniform,
The difference in delay between the signals can be reduced.

Alternatively, a clock line is provided so as to reciprocate along the entire length of the data bus, and clock skew is reduced by aligning the direction of clock signal transfer with the direction of data transfer (for example, US Pat. No. 5,432,823). .
The skew between signals is reduced by controlling the output timing of each signal from the IC chip.

[0005]

However, in the configuration of the first conventional example, the pins are provided only on one side (one side) of the IC chip, and the number of pins that can be arranged is limited. Further, it is difficult to improve the transfer rate by increasing the number of pins. Further, when the mounting of the IC chip becomes complicated, it becomes difficult to align the transfer directions of the clock signal and the data depending on the layout of the signal wiring.

The present invention has been made in view of the above problems, and has as its object to provide a semiconductor chip and a semiconductor mounting system which realize a high transfer rate and reduce clock skew. An object of the present invention is to provide a semiconductor chip and a semiconductor mounting system in which data transfer between IC chips can be performed without clock skew by controlling a transfer path of a clock signal.

[0007]

Means for Solving the Problems A semiconductor mounting system of the present invention includes a first semiconductor chip and the first semiconductor integrated circuit is packaged, the second semiconductor integrated circuit packaging, the first semiconductor A semiconductor mounting system including a second semiconductor chip for controlling a chip , wherein the first semiconductor chip has a plurality of first pins formed on a first surface and a plurality of first pins formed on a second surface. A plurality of second pins, wherein the second semiconductor chip includes a plurality of third pins formed on a third surface and a plurality of fourth pins formed on a fourth surface. The semiconductor mounting system has a first wiring that electrically connects the plurality of first pins and the plurality of third pins, a plurality of second pins, and a plurality of fourth wires. Second to electrically connect the pin
And the length of the first wiring is substantially equal to the length of the second wiring. Thereby, the above object is achieved. The first surface may be adjacent to the second surface, and the third surface may be adjacent to the fourth surface.

[0008] The first surface may be opposed to the second surface, and the third surface may be opposed to the fourth surface.

[0009] The semiconductor mounting system further includes a first substrate on which the first wiring is formed, and a second substrate on which the second wiring is formed. At least one of the two substrates may have a groove for mounting at least one of the first semiconductor chip and the second semiconductor chip.

The first semiconductor chip further has a plurality of first pads electrically connected to the plurality of first pins via a plurality of first wires, and the second semiconductor chip has a plurality of first pads.
The semiconductor chip further has a plurality of second pads electrically connected to the plurality of second pins via a plurality of second wires, and each of the plurality of first wires May be substantially equal to the length of each of the plurality of second wires.

[0011]

According to another aspect of the present invention, there is provided a semiconductor mounting system in which a first semiconductor chip packaged with a first semiconductor integrated circuit functioning as a master and a second semiconductor integrated circuit functioning as a slave are packaged. A second semiconductor chip, wherein each of the plurality of second semiconductor chips comprises:
The plurality of first pins formed on the first surface, the plurality of second pins formed on the second surface adjacent to the first surface, and the plurality of first pins are respectively input to the plurality of first pins. A synchronization circuit that synchronizes the plurality of signals with each other and outputs the synchronized plurality of signals to the plurality of second pins, thereby achieving the above object.

[0013] A clock signal may be input to one of the plurality of first pins, and the synchronization circuit may perform a synchronization operation according to the clock signal.

Each of the plurality of second semiconductor chips includes a first path for electrically connecting each of the plurality of first pins and each of the second pins, and a plurality of first paths for electrically connecting each of the plurality of first pins. The semiconductor device may further include a selection circuit that selects one of the second paths that electrically connects each of the pins to the second semiconductor integrated circuit.

[0015] The selection circuit may select one of the first path and the second path according to a selection signal supplied from the first semiconductor chip.

[0016] Each of the plurality of second semiconductor chips further includes a plurality of terminating resistors corresponding to the plurality of first pins, respectively, and each of the plurality of terminating resistors is operated in accordance with the selection signal. , May be connected to a corresponding one of the plurality of first pins.

[0017] The first semiconductor integrated circuit may be a memory controller, and the second semiconductor integrated circuit may be a memory.

A semiconductor chip according to the present invention is a semiconductor chip in which a semiconductor integrated circuit is packaged, wherein a plurality of first pins formed on a first surface and a second surface adjacent to the first surface are provided. The plurality of second pins formed on the first and second pins are synchronized with each other, and the plurality of signals respectively input to the plurality of first pins are synchronized with each other, and the synchronized plurality of signals are output to the plurality of second pins, respectively. With a synchronous circuit,
Thereby, the above object is achieved.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) In Embodiment 1, a semiconductor chip in which a semiconductor integrated circuit is packaged (hereinafter referred to as a semiconductor chip).
A semiconductor mounting system including at least two IC chips will be described. The IC chip has a plurality of pins formed on a first surface and a plurality of pins formed on a second surface. Here, the first surface and the second surface of the IC chip
Is the side surface of the IC chip. The side surface of the IC chip refers to a surface of the IC chip other than the surface having the largest area.

FIG. 1A shows a configuration of a semiconductor mounting system 100 according to the first embodiment of the present invention. As shown in FIG. 1A, a semiconductor mounting system 100 includes an IC chip 1, an IC chip 2, a plurality of pins formed on a first surface of the IC chip 1, and a first surface of the IC chip 2. And a plurality of pins formed on the second surface of the IC chip 1 and a plurality of pins formed on the second surface of the IC chip 2 are electrically connected to each other. Is included. The wiring 5 is formed on the printed circuit board 3. The wiring 6 is formed on the printed circuit board 4. The IC chip 1 is, for example, a memory.
The IC chip 2 is, for example, a memory controller that controls the memory.

In the following description, it is assumed that the IC chip 1 is a memory and the IC chip 2 is a memory controller.

In order to realize data transfer to the IC chip 1 at a high rate, it is necessary to operate each signal line with a clock signal of a higher frequency. However, when a plurality of signal lines are operated at a high frequency, clock skew occurs because the lengths of the signal lines are different. In order to prevent such a clock skew, the length of each signal line may be made uniform. As described above, in the conventional method, pins are provided only on one side (one side) of the IC chip, so that an increase in the number of pins is limited, and it is difficult to improve a signal transfer rate.

In this embodiment, a plurality of pins are provided on each of two sides of the IC chip 1, and a plurality of pins are provided on each of two sides of the IC chip 2. I
The C chip 1 and the IC chip 2 are mounted such that the plane on which the wiring 5 is formed (printed board 3) and the plane on which the wiring 6 is formed (printed board 4) are substantially perpendicular. In the IC chips 1 and 2, two side surfaces on which a plurality of pins are provided are adjacent to each other. With this configuration, the length of the wiring 5 becomes substantially equal to the length of the wiring 6.

More specifically, the pins of IC chip 1 and I
All the pins are arranged equidistant from the corresponding pins of the C chip 2. Accordingly, the length of the wiring 5 is substantially equal to the length of the wiring 6. This prevents clock skew from occurring due to differences in wiring length,
And by increasing the number of pins and the number of wires,
The data transfer rate between the IC chip 1 and the IC chip 2 can be improved.

As shown in FIG. 1A, when the IC chip 1 and the IC chip 2 are mounted three-dimensionally,
In order to accurately match the length of the wiring 5 with the length of the wiring 6, the IC chip 1 and the IC chip 2 must be
It is important to mount them exactly vertically.

FIG. 1B shows an example of a printed circuit board 4 having a groove 7. The groove 7 is formed in the printed circuit board 4 so as to extend in a direction perpendicular to the direction in which the wiring 6 extends. After the printed circuit board 3 and the printed circuit board 4 are mounted so as to be perpendicular to each other, the IC chip 1 and the IC chip 2 are inserted along the grooves 7 formed in the printed circuit board 4. This makes it easy to mount the IC chip 1 and the IC chip 2 exactly and vertically on the printed circuit board 3. As a result, it is easy to accurately match the length of the wiring 5 with the length of the wiring 6.

Further, the groove 7 may be formed not only on the printed board 4 but also on the printed board 3. By forming the grooves 7 in both the printed circuit board 4 and the printed circuit board 3, it becomes easy to arrange the IC chips 1 and 2 more accurately.

In the example shown in FIGS. 1A and 1B, a plurality of pins are provided on two adjacent side surfaces of the IC chip. However, the surface on which the plurality of pins are provided is not limited to this. For example, a plurality of pins may be provided on opposing side surfaces of the IC chip.

FIG. 2 shows a semiconductor mounting system 200 including an IC chip 11 and an IC chip 12 provided with a plurality of pins on two opposing side surfaces.

As shown in FIG. 2, the semiconductor mounting system 200 includes an IC chip 11, an IC chip 12,
Plural pins and IC formed on the first surface of C chip 11
A wiring 5 for electrically connecting a plurality of pins formed on the first surface of the chip 12 with a plurality of pins formed on the third surface of the IC chip 11 and a plurality of pins formed on the third surface of the IC chip 12; And a wiring 9 for electrically connecting the plurality of pins to each other. Here, the first surface and the third surface are opposed to each other.

It should be noted that the expression “third surface” is used to distinguish it from the second surface of the IC chip in the semiconductor system 100 described above. The wiring 5 is formed on the printed circuit board 3. The wiring 9 is formed on the printed circuit board 8.
The IC chip 11 is, for example, a memory. The IC chip 12 is, for example, a memory controller that controls a memory.

As shown in FIG. 2, the printed circuit board 3 and the printed circuit board 8 are arranged in parallel with each other. IC chips 11 and 12 between printed circuit board 3 and printed circuit board 8
And are mounted. In the IC chip 11 and the IC chip 12, a plurality of pins are arranged on upper and lower side surfaces in FIG. By arranging the printed board 3 and the printed board 8 three-dimensionally, it is possible to increase the number of wirings and to make the length of the wiring 5 and the length of the wiring 9 between the IC chip 11 and the IC chip 12 equal. it can.

In the semiconductor mounting system 200, similarly to the semiconductor mounting system 100, the IC chip 11 and the I
In order to facilitate positioning of the C chip 12, a groove (not shown) may be provided in one or both of the printed board 3 and the printed board 8.

FIG. 3 shows the internal configuration of the IC chip 1.
The IC chip 1 has a silicon substrate 1 '.

A plurality of pins 13 are provided along the first side of the IC chip 1 so as to protrude outside the IC chip 1. A plurality of pins 14 are provided along a second side adjacent to the first side of the IC chip 1 so as to protrude outside the IC chip 1.

A plurality of pins 13 are provided on the silicon substrate 1 '.
Are arranged along a first side of the IC chip 1, and a plurality of pads 16 corresponding to a plurality of pins 14 are arranged along a second side of the IC chip 1. Each of the plurality of pins 13 is connected to a corresponding pad 15 via a bonding wire W1.
Each of the plurality of pins 14 is connected to a bonding wire W2.
Is connected to the corresponding pad 16 via the.

The distance D between the pad and the corresponding pin is set constant, and the length of the bonding wire W1 is substantially equal to the length of the bonding wire W2. Thus, skew between signals due to a difference in wiring length is reduced.

The IC chip 2 has the same internal configuration as the IC chip 1 shown in FIG. The internal configurations of the IC chips 11 and 12 shown in FIG. 2 are the same as the internal configurations of the IC chips 1 and 2 except for the arrangement of pads and pins.

(Embodiment 2) FIG. 4 shows a configuration of a semiconductor mounting system 300 according to Embodiment 2 of the present invention. The semiconductor mounting system 300 includes an IC chip 20 functioning as a master and an IC chip 10a functioning as a slave.
To 10h. In the following description, the IC chip 20
Denotes a memory controller, and IC chips 10a to 1
Assume each of 0h is a memory.

Memory controller 20 and memory 10
a to 10h are arranged in a matrix on one plane. Compared to the conventional linear arrangement in which a plurality of IC chips are arranged linearly (one-dimensionally), the planar arrangement of the present embodiment in which a plurality of IC chips are arranged two-dimensionally (two-dimensionally) There is an advantage that the layout of the chip is less restricted and the driving load capacity is small. However, in the planar arrangement, it is necessary to eliminate a skew difference between a signal transferred at an inside corner and a signal transferred at an outside corner of the IC chip. In the present embodiment, the IC
By providing a synchronization circuit in the chip, a skew difference between signals transferred between IC chips is eliminated. The synchronization circuit will be described later with reference to FIGS. 10A and 10B.

As shown in FIG. 4, each of the memory controller 20 and the memories 10a to 10h has a plurality of pins formed on side surfaces adjacent to each other.

The memory 10a has a plurality of pins 13a formed on the lower side surface in FIG. 4 and a plurality of pins 14a formed on the right side surface in FIG. The same applies to the other memories 10b to 10h.

The memory controller 20 has a plurality of pins 13i formed on the lower side surface in FIG. 4 and a plurality of pins 14i formed on the right side surface in FIG.

In the example shown in FIG. 4, the number of pins formed on the side surface of the IC chip is fifteen. However, the number of pins formed on the side surface of the IC chip is not limited to this. Any number of pins can be formed on the side surface of the IC chip. The semiconductor mounting system 300 has wirings V1 to V3 extending in the vertical direction in FIG. 4 and wirings H1 to H3 extending in the horizontal direction in FIG. As described above, the direction in which the wirings V1 to V3 extend is different from the direction in which the wirings H1 to H3 extend. Preferably, the wirings V1 to V
3 extends in a direction perpendicular to the direction in which the wirings H1 to H3 extend.

The wirings V1 to V3 and the wirings H1 to H3 are formed on different layers formed on a printed circuit board.
The wirings V1 to V3 and the wirings H1 to H3 are electrically insulated from each other.

A plurality of pins 13i provided in the memory controller 20, a plurality of pins 13a provided in the memory 10a, and a plurality of pins 13b provided in the memory 10b are connected to the wiring V1. You. Wiring V1
Pass under the memory controller 20 and the memory 10b.

Similarly, a memory 10c,
Plural pins 13c, 13 corresponding to 10d and 10e
d and 13e are connected, and the memory 10 is connected to the wiring V3.
f, a plurality of pins 13f corresponding to 10g and 10h,
13g and 13h are connected.

A plurality of pins 14i provided in the memory controller 20, a plurality of pins 14e provided in the memory 10e, and a plurality of pins 14h provided in the memory 10h are connected to the wiring H1. You. Wiring H1
Pass under the memory 10e and the memory 10h.

Similarly, the memory 10b,
Plural pins 14b, 14 corresponding to 10d and 10g
d and 14g are connected, and the memory 10 is connected to the wiring H3.
a, a plurality of pins 14a corresponding to 10c and 10f,
14c and 14f are connected.

The number of conductive lines included in each of the wirings V1 to V3 and H1 to H3 is equal to the number of pins provided on one side surface of each IC chip.

FIG. 5 shows the connection between the memory 10d and the wirings V2 and H2 in detail. The same applies to the connection state between the other IC chip and the wiring.

The number of pins 13d of the memory 10d is determined by the wiring V
2 is equal to the number of conductive lines VL2 included. Memory 1
The pin 13d of 0d is connected 1: 1 to the conductive line VL2. The number of pins 14d of the memory 10d is determined by the wiring H
2 is equal to the number of conductive lines HL2 included. Memory 1
The 0d pin 14d is connected 1: 1 to the conductive line HL2.

The wiring V2 connected to the pin 13d and the wiring H2 connected to the pin 14d are respectively connected to the memory 1
It passes from one side of the memory 10d to the opposite side through the lower side of 0d. The wiring V2 and the wiring H2 are formed in different layers formed on a printed board. Wiring V2 and H
2 is formed so as not to be short-circuited. Referring to FIG. 4 again, the operation of semiconductor mounting system 300 when memory controller 20 accesses memory 10b will be described.

The memory controller 20 outputs an address signal, a clock signal, and a control signal to the pin 13i. The address signal, the clock signal, and the control signal output from the memory controller 20 are input to the pin 13b of the memory 10b through the wiring V1 connected to the pin 13i. In response to the control signal, the memory 10b outputs the data stored in the memory 10b to the wiring V1 via the pin 13b. The position of the data stored in the memory 10b is specified by an address signal. The memory controller 20 receives the data output from the memory 10b from the wiring V1. Thereby, one access to the memory 10b by the memory controller 20 ends.

The pins 13a to 13i provided on the first side surface of each IC chip are collectively called pins 13. Each IC
The pins 14a to 14i provided on the second side surface adjacent to the first side surface of the chip are collectively referred to as pins 14.

FIG. 6 shows an example of a clock signal transfer path and a data signal transfer path in the semiconductor mounting system 300. The clock signal is indicated by the arrow 3 shown in FIG.
01 along with the memory 10 from the memory controller 20.
a to 10 h. The state in which the memory controller 20 accesses any of the memories 10a to 10h is referred to as a "standard access state".

The memory controller 20 supplies the clock signal to the memory 10b via the wiring V1, and supplies the clock signal to the memory 10e via the wiring H1. The clock signal supplied to the memory 10b is thereafter transferred to the memories 10a, 10c, and 10f in that order. The clock signal supplied to the memory 10b is further transferred to the memories 10d and 10g in this order. Further, the clock signal supplied to the memory 10e is further transferred to the memory 10h.

As described above, between the memories 10c to 10e,
Not directly connected by a clock signal. Similarly, the memories 10f to 10h are not directly connected by the clock signal.

In the example shown in FIG. 6, the pin assigned to the clock signal for supplying and transferring the clock signal is the pin closest to the lower right corner of the IC chip. However, the arrangement of the pins assigned to the clock signal is not limited to this. Any pin of the IC chip can be assigned to a clock signal. When transferring the data signal along the transfer direction of the clock signal, it is not necessary to consider the influence of the delay time between the clock signal and the data signal. For example, it is assumed that a clock signal transfer path is formed along arrow 301 shown in FIG. In this case, when a data signal is transferred from the memory controller 20 to the memory 10g, the direction of the data signal transfer path (indicated by the arrow A in FIG. 6) is the same as the direction of the clock signal transfer path. Also when transferring a data signal from the memory 10a to the memory 10f, the direction of the data signal transfer path (indicated by the arrow B in FIG. 6) is the same as the direction of the clock signal transfer path.

FIG. 7 shows an example of a clock signal transfer path and a data signal transfer path in a state different from the standard access state. For example, when transferring a data signal from the memory 10a to the memory 10h, the data signal is transferred along the transfer path indicated by the arrow C in FIG.
0h are transmitted in this order. In this case, the clock signal is
When the transfer is performed along the transfer path of the clock signal indicated by the arrow 301, a delay difference may occur between the clock signal and the data signal. If such a delay difference occurs, the memory may malfunction. For example, the memory 10g has the memory 10b
And a data signal is transferred via the memory 10d.
The transfer path of this data signal is indicated by an arrow 301 in FIG.
Is different from the transfer path of the clock signal indicated by.
A data signal is transferred from the memory controller 20 to the memory 10h only through the memory 10e. This data signal transfer path is different from the clock signal transfer path indicated by arrow 301 in FIG.

In order to eliminate the delay difference between the clock signal and the data signal, the transfer path of the clock signal may be changed as shown by an arrow 302 in FIG. In this case, after the clock signal is transferred from the memory controller 20 to the memory 10a via the memory 10b, the clock signal is transferred along the same direction as the data signal transfer path (indicated by the arrow C in FIG. 7). 10a, 10c, 1
0f, 10g, and 10h are transmitted in this order. Since the clock signal and the data signal are transferred in the same direction, a delay difference between the clock signal and the data signal can be eliminated. Thus, malfunction of the memory can be prevented.

The selection and setting of the transfer path of the clock signal are performed during the setup period before the transfer of the data signal. During the setup period, the wirings V1 to V3, H1
To H3, the transfer information of the data signal is stored in the memory 10a to
Sent to 10h. The transfer path of the clock signal is determined by the selection circuits provided in the memories 10a to 10h according to the transfer information of the data signal. Memory 10a-10
The details of the selection circuit provided in h will be described later.

The memory controller 20 and the memory 1
The skew between the memories when transferring the clock signal between 0a and 10h may be estimated, and the transfer path of the clock signal may be determined according to the estimation.
The estimation of such a skew is performed by, for example, supplying a clock signal from the memory controller 20 to the memories 10a to 10h via a clock signal line, and
0h is performed by sending the clock signal back to the memory controller 20 via one different data signal line among the plurality of data signal lines.
The data signal line used to send back the clock signal can be selected by, for example, a select switch.
As a result, the skew between the memories on the transfer path of the clock signal can be estimated at once.

FIG. 8 shows a transfer path of a clock signal when a data signal is transferred in a direction opposite to a normal transfer path of a clock signal supplied from the controller 20 (hereinafter referred to as a forward transfer path). In FIG. 8, the transfer path of the clock signal is indicated by an arrow 303.

For example, when a data signal is transferred from the memory 10g to the memory controller 20 along the path indicated by the arrow A in FIG. 8, or when the data signal is transferred from the memory 10f to the memory 10a along the arrow B shown in FIG. Consider the case of transferring a signal. In this case, the memory 10 at the forward end of the clock signal transfer path 303
At f, 10g and 10h, the clock signal is reversed. For example, a transfer path for the clock signal in the reverse direction may be formed by using a pin (and a corresponding signal line) adjacent to the pin to which the clock signal in the forward direction is supplied. As a result, the clock signal transfer path 303 becomes bidirectional.
Therefore, no matter which direction the data signal is transferred on the clock signal transfer path 303, it is possible to prevent the occurrence of skew between the data signal and the clock signal.

FIG. 9 shows the internal configuration of the memory 10a.
The memories 10b to 10h have the same internal configuration as the memory 10a.

The memory 10a includes a silicon substrate 10a '. On a silicon substrate 10a ', a memory block 26 having a plurality of memory cells (not shown) and a peripheral circuit 27 for controlling access to the memory block 26
And a selection circuit 21 are formed. Peripheral circuit 27 includes at least a sense amplifier and a decoder. Memory 10a
A plurality of pins 13a are provided so as to protrude to the outside of the memory 10a along the first side of the memory 10a. Memory 10a
Along the second side adjacent to the first side of the memory 10a
A plurality of pins 14a are provided so as to protrude to the outside.

On the silicon substrate 10a ', a plurality of pads 15 corresponding to the plurality of pins 13b are arranged along a first side of the memory 10a, and a plurality of pads 16 corresponding to the plurality of pins 14a are formed on the memory 10a. Are arranged along the second side of the. Each of the plurality of pins 13a is connected to a corresponding pad 15 via a bonding wire W1. Each of the plurality of pins 14a is connected to a corresponding pad 16 via a bonding wire W2.

The pads 15 are connected to the selection circuit 21 via the wiring 22. The pads 16 are connected to the selection circuit 21 via the wiring 24. The selection circuit 21 is connected to the peripheral circuit 27 via the wiring 23.

Next, the operation of the selection circuit 21 will be described.

For example, when the memory is arranged at the position of the memory 10b shown in FIG.
b. Hereinafter, the selection circuit 21 of the memory 10b
Will be described.

The signal input to pin 13b is input to selection circuit 21 via bonding wire W1, pad 15, and wiring 22. When the input signal is a signal for accessing the memory 10b, the selection circuit 21 electrically connects the wiring 22 to the wiring 23. As a result, the input signal is supplied to the memory block 26 via the wiring 23 and the peripheral circuit 27. In this way,
The memory block 26 in the memory 10b is accessed. On the other hand, when the input signal is not a signal for accessing the memory 10b but a signal to be transferred to the adjacent memory 10d via the memory 10b (the transfer path of the data signal indicated by the arrow A in FIG. 6). ), The selection circuit 21 electrically connects the wiring 22 to the wiring 24. As a result, the input signal is transmitted to the wiring 24, the pad 16
And output from the pin 14b via the bonding wire W2.

For example, if the memory is located at the location of the memory 10f shown in FIG.
Input from f. Hereinafter, the selection circuit 21 of the memory 10f
Will be described.

The signal input to the pin 14f is input to the selection circuit 21 via the bonding wire W2, the pad 16 and the wiring 24. When the input signal is a signal for accessing the memory 10f, the selection circuit 21 electrically connects the wiring 24 to the wiring 23. As a result, the input signal is supplied to the memory block 26 via the wiring 23 and the peripheral circuit 27. In this way,
The memory block 26 in the memory 10f is accessed. On the other hand, when the input signal is not a signal for accessing the memory 10f but a signal to be transferred to the adjacent memory 10g via the memory 10f (the transfer path of the data signal indicated by the arrow C in FIG. 7). ), The selection circuit 21 electrically connects the wiring 24 to the wiring 22. As a result, the input signal is applied to the wiring 22, the pad 15
And output from the pin 13f via the bonding wire W1.

FIG. 10A shows the configuration of the selection circuit 21.
Wirings 22, 23 and 24 are connected to data signal D
It includes n data signal lines carrying data (1) to Data (n) and one clock signal line carrying clock signal CLK.

The selection circuit 21 includes a synchronization circuit 33. The synchronization circuit 33 outputs the data signal Data (1)
.. Data (n) and the clock signal CLK are synchronized with each other, and the synchronized signals are output to the wiring 24.
Further, the synchronization circuit 33 outputs the data signal Dat on the wiring 24.
a (1) to Data (n) and the clock signal CLK are synchronized with each other, and the synchronized signals are output to the wiring 22. Such a synchronization function is achieved by latching the data signals in the latch circuits 33-1 to 33-n in response to the clock signal CLK.

In this manner, a plurality of signals input to the plurality of pins 13a (FIG. 9) can be synchronized, and these synchronized signals can be output to the plurality of pins 14a (FIG. 9). Further, it is possible to synchronize a plurality of signals input to the plurality of pins 14a (FIG. 9) and output these synchronized signals to the plurality of pins 13a (FIG. 9). Such a synchronization function is an essential function when a plurality of memories are arranged in a plane. With such a synchronization function, it is possible to eliminate a skew generated between signal lines according to a position where a pin is arranged.

FIG. 10B shows another configuration of the selection circuit 21. The selection circuit 21 shown in FIG. 10B includes selectors 32-0 to 32-n in addition to the configuration shown in FIG.
And a selector control circuit 36 for controlling the selectors 32-0 to 32-n.

Each of selectors 32-0 to 32-n includes three switches. By controlling the open / close state of these switches, the signal path can be changed.

The selector control circuit 36 responds to a control signal supplied from the memory controller 20,
The connection relation between 23 and 24 is controlled. For example, wiring 2
2 is supplied to the wiring 23, the selector control circuit 36 controls the selector so that the wiring 22 and the wiring 23 are electrically connected and the wiring 22 and the wiring 24 are electrically insulated. 32-0 to 32-n are controlled. Wiring 22
When the above signal is supplied to the wiring 24, the selector control circuit 36 operates such that the wiring 22 and the wiring 24 are electrically connected and the wiring 22 and the wiring 23 are electrically insulated. The selectors 32-0 to 32-n are controlled.

The control signal supplied from the memory controller 20 is input to the selector control circuit 36 via the wiring 22 or 24 during the setup period before transferring the data signal, and is held there. Alternatively, the selector control circuit 36 responds to the chip select signal CS
The connection relationship between the wirings 22, 23 and 24 may be controlled. The chip select signal CS is a signal that defines the activation / inactivation of the IC chip to which it is input. When the chip select signal CS is active, the selector control circuit 36 selects the selector 32- so that the wirings 22 and 23 are electrically connected and the wirings 22 and 24 are electrically insulated. 0-32-n are controlled. When the chip select signal CS is inactive, the selector control circuit 36 operates such that the wirings 22 and 24 are electrically connected and the wirings 22 and 23 are electrically insulated. The selectors 32-0 to 32-n are controlled.

As described above, the selectors 32-0 to 32-32
-N indicates a plurality of pins 13a (FIG. 9) and a plurality of pins 14a.
(FIG. 9) and a second path for electrically connecting the plurality of pins 13a (FIG. 9) or the plurality of pins 14a (FIG. 9) to the memory block 26. Choose one of them. Thereby, the signal path can be changed.

As described above, in the present embodiment,
A selection circuit 21 is provided in each IC chip, and a connection relationship between pins 13 and 14 and memory block 26 is set by a control signal given before data transfer. In an IC chip serving as a data transfer path, a signal input from pin 13 (or 14)
(Or 13) is output as it is. As described above, according to the semiconductor mounting system 300 of the present embodiment, the transfer of the clock signal and the data signal is performed by the wiring V
This is performed using an IC chip in which the pin 13 and the pin 14 are short-circuited by the selection circuit 21 using the 1 to V3 and the wirings H1 to H3.

Further, as described above, the first or second wiring connecting the pin on one side of the IC chip to the corresponding pin on the side of the adjacent IC chip has the same length, and the clock signal and the data The signals are transferred via the same signal path. The difference in the wiring length between the pins in the IC chip is sufficiently smaller than the difference in the wiring length between the IC chips. In the present embodiment, the synchronization circuit 33 is provided in each IC chip.
Is provided. The data to be transferred is output from the IC chip used as the transfer path by the synchronization circuit 33 in synchronization with the clock signal.

Accordingly, it is possible to provide a semiconductor mounting system in which the wiring lengths between the pins are made uniform and the skew and clock skew due to the wiring length difference are reduced without limiting the number of pins provided on each IC chip.

(Embodiment 3) In general, when a low-amplitude signal is transferred at high speed in a semiconductor mounting system, a resistor is inserted at the end of each wiring in order to improve transfer accuracy, and a high potential state (for example, , 5 V). If the signal transfer path is fixed as in the prior art, it is sufficient to dispose a resistor at the end of the wiring. However, when the route of the clock signal is changed according to the data transfer route as in the second embodiment (for example,
6 to 8), the terminal ends are not constant. Therefore, in this embodiment, according to the switching of the transfer path of the clock signal,
A case where the termination resistance is switched will be described.

FIG. 11 shows a configuration of a semiconductor mounting system 400 according to the third embodiment of the present invention. The semiconductor mounting system 400 has nine IC chips 4 as in the second embodiment.
0, 30a to 30h. Each IC chip is provided with terminating resistors Ra to Ri. In the following description, IC
It is assumed that the chip 40 is a memory controller (or a clock signal source), and the IC chips 30a to 30h are memories. In the state before the signal is input to the semiconductor mounting system 400 (initial state), as shown in FIG. 11, the terminating resistors corresponding to all the IC chips are connected.

FIG. 12 shows an example of the transfer path of the clock signal and the transfer path of the data signal in the standard access state. 12, a solid arrow 401 indicates a transfer path of a clock signal. In FIG. 12, a path indicated by a dotted line (for example, 30
e) is not used. The transfer path of the data signal is represented by arrow 402. In such a standard access state, the terminating resistors Rf to Rh are connected to the memories 30f to 30h which are the ends of the transfer path of the clock signal, respectively, and the other memories 30a to 30e and the terminating resistors Ra to Re and Ri
Disconnect. In FIG. 12, the terminating resistors connected to the IC chip are indicated by solid lines, and the terminating resistors separated from the IC chip are indicated by broken lines. In this way, by controlling the connection and disconnection of the terminating resistor, the resistor can be connected only to the IC chip that terminates the clock signal path. Thereby, signal transfer is performed with high accuracy. Next, consider the case where a data signal is transferred from memory to memory.

FIG. 13 shows an example of a transfer path of a clock signal and a transfer path of a data signal. In FIG.
A solid arrow 403 indicates a transfer path of the clock signal. In FIG. 13, a path indicated by a dotted line (for example, the memory 3
The path from 0d to 30e) is not used. The transfer path of the data signal is represented by arrow 404. The data signal is transferred from the memory 30a to the memory 30h.
The memories 30d and 3 that are the ends of the clock signal transfer path
0e and 30h are respectively connected to terminating resistors Rd, Re and Rh, and the other memories 30a to 30c, 3
Terminating resistors Ra to Rc, Rf, Rg, and Ri are separated from 0f, 30g and the memory controller 40. FIG.
In 3, the terminating resistor connected to the IC chip is a solid line and I
The terminating resistor separated from the C chip is indicated by a broken line. In this way, by controlling the connection and disconnection of the terminating resistor, the resistor can be connected only to the IC chip that terminates the clock signal path. Thereby, signal transfer is performed with high accuracy.

FIG. 14 shows the internal configuration of the memory 30a having the function of switching the terminating resistor described above. Memory 30
b to 30h and the memory controller 40
It has the same internal configuration as Oa.

In FIG. 14, the same components as those shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

The memory 30a includes a silicon substrate 30a '. On the silicon substrate 30a ', a first termination resistance switching circuit 37 is formed between the pad 15 and the selection circuit 21, and a second termination resistance switching circuit 38 is formed between the pad 16 and the selection circuit 21. Have been.

The first termination resistance switching circuit 37 is connected to the pad 15 via the wiring 22 and to the selection circuit 21 via the wiring 22 '. Similarly, the second termination resistance switching circuit 38 connects the pad 16
And to the selection circuit 21 via a wiring 24 '.

FIG. 15 shows the internal configuration of the termination resistance switching circuit 37. The termination resistance switching circuit 38 has the same internal configuration as the termination resistance switching circuit 37.

The terminating resistor R is composed of a plurality of resistance elements 43 provided corresponding to the wiring 22 (22 '). In the example shown in FIG. 15, the resistance element 43 is provided inside the termination resistance switching circuit 37. Alternatively, the resistance element 43 may be provided outside the termination resistance switching circuit 37. As long as the resistance element 43 is connected to the wiring 22 (22 ′) via the termination resistance selector 41,
Can be located at any position.

The terminating resistance switching circuit 37 includes a resistance element 4
3 has a terminating resistor selector 41 for selectively connecting the terminating resistor 3 to the wiring 22 (22 ′), and a resistor control circuit 42 for controlling the operation of the terminating resistor selector 41.

The switching of the terminating resistor R (resistance element 43) is performed during the setup period before transferring the data signal, similarly to the switching of the selectors 32-0 to 32-n in the selection circuit 21 described in the second embodiment. This is performed by inputting a control signal for switching the terminating resistance from the wiring 22 to the resistance control circuit 42. When the terminating resistor R is connected to the IC chip, all bits of the control signal are at H level, and when the terminating resistor R is separated from the IC chip, any one bit of the control signal is at L level. .

The resistance control circuit 42 includes an AND circuit 42a
And a switch 42b and a latch circuit 42c. The chip select signal CS is input to the switch 42b. When the chip select signal CS is active, the switch 42b is closed. As a result, the control signal on the wiring 22 is input to the latch circuit 42c via the AND circuit 42a and the switch 42b, and is held in the latch circuit 42c. While the chip select signal CS is active,
The control signal held in the latch circuit 42c is supplied to the termination resistor selector 41. The termination resistor selector 41 is, for example, an NMOS transistor.

When the IC chip is at the end of the clock signal transfer path, the chip select signal CS input to the IC chip is active. In this case, a control signal that is at H level for all bits is input to the resistance control circuit 42. As a result, the chip select signal C
While S is active, the terminating resistor selector 41 is turned on. In this manner, the plurality of resistance elements 43 are
(22 ').

(Embodiment 4) In this embodiment, a case will be described in which the three-dimensional mounting of the IC chip described in Embodiment 1 is applied to the semiconductor mounting system of Embodiment 2.

FIG. 16A shows a configuration of a semiconductor mounting system 500 according to the fourth embodiment of the present invention. The semiconductor mounting system 500 includes the semiconductor mounting system 300 shown in FIG.
By mounting the IC chips 10a to 10h and 20 three-dimensionally, more preferably substantially perpendicularly to the wirings V1 to V3. Wirings H1 to H3
(Printed circuit board) 502 on which is formed the wiring V1
To V3 are substantially perpendicular to the plane (printed circuit board) 501 on which V3 is formed. As shown in FIG.
C-tips 10a-10h and 20 are preferably substantially perpendicular to plane 501 and plane 502
Are mounted substantially in parallel with each other.

According to semiconductor mounting system 500, effects similar to those of semiconductor mounting system 300 in the second embodiment are realized. Further, wirings V1 to V3 and wiring H1
It is not necessary to multiply the printed circuit board forming H3 for insulation between wirings, and the mounting area can be reduced.

FIG. 16B shows a semiconductor mounting system 51.
0 is shown. The semiconductor mounting system 510 is shown in FIG.
In addition to the components of the semiconductor mounting system 500 shown in (a), a printed circuit board 503 on which wirings V2 'and V3' are formed is further provided. As shown in FIG. 16 (b), it is possible to provide a plurality of pins 13 'on another side surface of the IC chips 10a to 10h and 20.
In this case, two IC chips (for example, IC chip 10
c and the wiring V2 and V2 ′ between the IC chip 10d)
Can be equal in length. Therefore, the same effect as the effect described in the first embodiment can be obtained.

FIG. 17 has the same arrangement of IC chips as the semiconductor mounting system 500 shown in FIG.
The semiconductor mounting system 600 in which the connection of the pins is changed is shown. Similar to the semiconductor mounting system 500, the semiconductor mounting system 600 includes a first wiring formed on the first printed circuit board 601 and a second printed circuit board 602 arranged vertically on the first printed circuit board. And a second wiring. In the semiconductor mounting system 600, two pins 51 and 5 of pins (lateral pins) corresponding to the second printed circuit board 602 of each IC chip 10 are provided.
2 is connected to the first wiring (vertical wiring) on the first printed circuit board. Such pins 51 and 52
Is because a signal delay occurs due to a wiring difference from other pins (pins provided in a downward direction) connected to the first wiring.
It can be used as a signal that operates at a low speed, for example, a ground line, a power supply line, or a control signal line in setup. Not only the pins 51 and 52 shown in FIG. 17 but also a pin corresponding to a line whose signal speed is slower than other wirings in mounting may be used as a pin for inputting a signal of a low-speed operation as described above. it can.

FIGS. 18A and 18B show a semiconductor mounting system 700 in which a plurality of IC chips 50 having pins on four sides are mounted. As shown in FIG. 18A, each of the IC chips 50 is disposed substantially perpendicular to the first substrate 702, and each of the IC chips 50 and the printed substrate 702 provided vertically to the first printed substrate 701. 7
03 is mounted diagonally. In FIG. 18A, the upper substrate (fourth substrate 70
4) is omitted. FIG. 18B is a diagram of the semiconductor mounting system 700 viewed from above, except for the upper substrate.
By mounting in this manner, the number of wirings can be increased, and thereby the data transfer rate can be improved.

FIG. 19A is a perspective view of the semiconductor mounting system 700 as viewed from the outside, and FIG. 19B is a diagram in which the substrate is partially cut away for easy understanding.

Semiconductor mounting system 5 according to the present embodiment
According to 00 to 700, the skew due to the wiring difference is reduced by making the wiring lengths between the IC chips (devices) uniform, and the number of signal lines of the wiring (the number of pins of the IC chip) is also increased to increase the transfer rate. Can be improved.

[0109]

As described above, according to the present invention,
A plurality of pins are provided on two side surfaces of an IC chip, and two pins are provided.
By making the wiring length between the C chips uniform, it is possible to reduce the skew due to the wiring difference and to improve the transfer rate. In particular, by forming the printed board three-dimensionally along a plurality of pins provided on the side surface of the IC chip, it is possible to reduce skew, achieve a high data transfer rate, and reduce a mounting area by equal wiring lengths. it can.

By selecting the transfer path of the clock signal according to the transfer path of the data signal, the direction in which the clock signal is transferred and the direction in which the data signal is transferred can be made the same. Thus, the clock skew can be reduced even when the data signal is transferred along any path.

[Brief description of the drawings]

FIG. 1A is a diagram illustrating a configuration of a semiconductor mounting system according to a first embodiment of the present invention, and FIG. 1B is a diagram illustrating an example of an IC chip mounting method in the semiconductor mounting system illustrated in FIG. .

FIG. 2 is a diagram illustrating a configuration of a semiconductor mounting system according to the first embodiment of the present invention;

FIG. 3 is a diagram showing an internal configuration of an IC chip according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a semiconductor mounting system according to a second embodiment of the present invention;

5 is a diagram showing a connection relationship between the IC chip shown in FIG. 4 and wiring.

FIG. 6 illustrates a transfer path of a clock signal and a transfer path of a data signal in a standard access state.

FIG. 7 is a diagram showing a transfer path of a clock signal and a transfer path of a data signal when a data signal is transferred between memories.

FIG. 8 is a diagram illustrating a transfer path of a clock signal and a transfer path of a data signal when data is transferred in the reverse direction.

FIG. 9 is a diagram illustrating an internal configuration of an IC chip including a selection circuit according to a second embodiment of the present invention.

FIG. 10A is a block diagram illustrating an internal configuration of a selection circuit.

FIG. 10B is a block diagram showing an internal configuration of a selection circuit.

FIG. 11 is a diagram illustrating a configuration of a semiconductor mounting system according to a third embodiment of the present invention;

FIG. 12 is a diagram showing an arrangement of a clock signal transfer path and a terminating resistor in a standard access state.

FIG. 13 is a diagram showing a transfer path of a clock signal and an arrangement of terminating resistors when data is transferred between memories.

FIG. 14 is a diagram illustrating an internal configuration of an IC chip including a termination resistance switching circuit according to a third embodiment of the present invention.

FIG. 15 is a diagram illustrating a configuration of a termination resistance switching circuit.

FIGS. 16A and 16B are diagrams illustrating a configuration example of a semiconductor mounting system in which an IC chip is mounted three-dimensionally.

FIG. 17 is a diagram illustrating another configuration example of a semiconductor mounting system in which an IC chip is mounted three-dimensionally.

FIGS. 18A and 18B are diagrams illustrating a configuration example of a semiconductor mounting system in which an IC chip is mounted three-dimensionally.

FIGS. 19A and 19B are diagrams illustrating a configuration example of a semiconductor mounting system in which an IC chip is mounted three-dimensionally.

[Explanation of symbols]

 1, 2 IC chip 3, 4 Printed circuit board 5, 6 Wiring 7 Groove 100 Semiconductor mounting system

Claims (12)

(57) [Claims] 1. A semiconductor device comprising: a first semiconductor chip in which a first semiconductor integrated circuit is packaged; and a second semiconductor chip in which a second semiconductor integrated circuit is packaged and controls the first semiconductor chip. A semiconductor mounting system, wherein the first semiconductor chip has a plurality of first pins formed on a first surface and a plurality of second pins formed on a second surface. The second semiconductor chip has a plurality of third pins formed on a third surface and a plurality of fourth pins formed on a fourth surface. A first wiring that electrically connects the plurality of first pins and the plurality of third pins, and a second wiring that electrically connects the plurality of second pins and the plurality of fourth pins. The length of the first wiring is the length of the second wiring Semiconductor packaging system substantially equivalent to: 2. The semiconductor mounting system according to claim 1, wherein said first surface is adjacent to said second surface, and said third surface is adjacent to said fourth surface. 3. The semiconductor mounting system according to claim 1, wherein said first surface is opposed to said second surface, and said third surface is opposed to said fourth surface. 4. The semiconductor mounting system further comprises: a first substrate on which the first wiring is formed; and a second substrate on which the second wiring is formed. At least one of the second substrates
2. The semiconductor mounting system according to claim 1, further comprising: a groove for mounting at least one of the first semiconductor chip and the second semiconductor chip. 3. 5. The semiconductor device according to claim 1, wherein the first semiconductor chip includes a plurality of first semiconductor chips.
Further comprising a plurality of first pads electrically connected to the plurality of first pins via wires, wherein the second semiconductor chip comprises a plurality of second wires via a plurality of second wires. A plurality of second pads electrically connected to the plurality of second pins, wherein a length of each of the plurality of first wires is equal to a length of each of the plurality of second wires. 2. The semiconductor mounting system according to claim 1, wherein the length is substantially equal to the length. 6. A first semiconductor chip packaged with a first semiconductor integrated circuit functioning as a master, and a plurality of second semiconductor chips packaged respectively with a second semiconductor integrated circuit functioning as a slave. A semiconductor mounting system, wherein each of the plurality of second semiconductor chips is formed on a plurality of first pins formed on a first surface, and on a second surface adjacent to the first surface. A plurality of second pins, and a synchronization circuit that synchronizes a plurality of signals respectively input to the plurality of first pins with each other, and outputs the synchronized plurality of signals to the plurality of second pins, respectively. A semiconductor mounting system comprising: 7. The clock signal to one of said plurality of first pin is input, the synchronization circuit performs the synchronous operation in accordance with the clock signal, the semiconductor mounting system of claim 6. The method according to claim 8, wherein each of the plurality of second semiconductor chip, the first path for electrically connecting the respective respectively the second pin of said plurality of first pin of said plurality 7. The semiconductor mounting system according to claim 6 , further comprising a selection circuit that selects one of a second path that electrically connects each of the one pin and the second semiconductor integrated circuit. 8. Wherein said selection circuit, in accordance with a selection signal supplied from the first semiconductor chip, selecting one of said second path and said first path, according to claim 8 Semiconductor mounting system. The method according to claim 10, wherein each of the plurality of second semiconductor chip, said plurality of further comprises a plurality of terminating resistors corresponding to each of the first pin, each of the plurality of termination resistors, said selecting According to a signal, the plurality of first
9. The semiconductor mounting system according to claim 8 , wherein said semiconductor mounting system is connected to a corresponding one of said pins. 11. The semiconductor mounting system according to claim 6 , wherein said first semiconductor integrated circuit is a memory controller, and said second semiconductor integrated circuit is a memory. 12. A semiconductor chip packaged with a semiconductor integrated circuit, comprising: a plurality of first pins formed on a first surface; and a plurality of first pins formed on a second surface adjacent to the first surface. And a synchronization circuit that synchronizes a plurality of signals respectively input to the plurality of first pins with each other, and outputs the synchronized plurality of signals to the plurality of second pins, respectively. Semiconductor chip.