JPS62212860A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To attain high speed data transfer by separating an internal data bus part connecting between specific function blocks requiring high speed data transfer from an internal data bus part unnecessary for the data transfer. CONSTITUTION:Bus switching circuits 7, 8 are arranged so that an internal data bus B connecting these circuits 7, 8 is set up as short as possible. The bus switching circuits 7, 8 are constituted of transfer gates for bi-directional transmission, and when a control line F is turned to '0', a data line X is separated from a data line Y, the status of the line X side exerts no influence upon the line Y side and the status of the line Y side also exerts no influence upon the line X side. Consequently, wiring capacity and wiring resistance of the X side can be also separated from that of the Y side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer circuit, and particularly to a data transfer circuit using an internal data bus that connects functional blocks within a semiconductor integrated circuit.

[Conventional technology]

The recent development of LSI has been remarkable, and with improvements in manufacturing technology, it has become possible to manufacture high-performance, large-scale L8I. For this reason, the chip size of LSI has become larger, and there is a noticeable tendency for the internal wiring length to become longer.

On the other hand, although the demand for high-speed operation is becoming stronger and stronger,
This is a demand that cannot be met with the increase in wiring length mentioned above.

In general, the basic configuration of an LSI such as a micro converter is that it has an internal data bus, and uses this internal data bus to store ROM, RAM, ALU (operating unit 2 nits),
By combining functional blocks such as various internal registers 2 and input/output '1 buffers, -I! We are giving and receiving numbers.

Inside this LSI with a complicated configuration, there are two and one, for example, ALU.
Conventionally, when data is transferred from a computer to a RAM, a data read signal is simply used to transfer the signal to an internal data bus that is commonly connected to all functional blocks on the sending side, and this signal is When the point on the internal data bus where the receiving functional block exists is sufficiently built up, a five-way process is taken to latch it into the receiving side register using a write signal.

[Problem that the invention seeks to solve]

However, as mentioned above, as the integration of LSIs progresses, more and more functions are incorporated into LSIs, and as a result, the number of functional blocks connected to the internal data bus increases, and the internal data bus for connecting these blocks increases. As a result,
The demand for high-speed data transfer is becoming stronger due to both the deterioration of the build-up characteristics of transmission waveforms due to increased leakage current due to bus wiring capacitance and wiring resistance, and the signal delay due to increased propagation time. Despite the fact that
The situation is such that achieving this goal is becoming increasingly difficult.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pig transfer circuit which obviates the above-mentioned disadvantages of the prior art.

[Means for solving problems]

The data transfer circuit of the present invention includes ROM and RAM.

A bus switching circuit with a transfer gate t that allows internal data buses that interconnect functional blocks such as ALUs (arithmetic unit) to be disconnected/connected midway, and data transfer control for controlling disconnection/connection of the circuit. A circuit is provided so that an internal data bus portion that connects specific functional blocks that require high-speed data transfer can be separated from an internal data bus portion that does not require high-speed data transfer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, ROMI, ALU (arithmetic unit) 2, status register 3, RAM 4, data bus buffer 5
, data transfer control circuit 6. Bus switching circuit 7. Bus switching circuit 8. Internal data bus A, internal data bus B, internal data bus C? and an external data bus D.

These include each functional block built into one chip of a semiconductor integrated circuit, and its
and an internal data bus that connects them to each other. This IC is designed to exchange high-speed data with an external data bus D via the data bus buffer 5.

In this embodiment, high-speed reading of the contents of the status register 3 to the outside is strongly required.

In this embodiment, eight status registers 3 are located so as to be connected to the data bus buffer 5 by a relatively short internal data bus B.
i, ROM1jJ and ALU via bus switching circuit 71
It is connected to a relatively long internal data line that connects the second and other functional blocks, and is further connected to the RAM
Relatively long internal data bus C connecting functional blocks of 4th class
is connected to.

The above-described bus switching circuit 78 and bus switching circuit 8 are arranged so that the internal data bus B that connects them is as short as possible. As shown in FIG. 2, the bus switching circuit 78 and the bus switching circuit 8 are composed of transfer gates for bidirectional transmission, and the control line F is
Then, data line X and data line Y are separated, and the state of line X has no effect on line do not have. As a result, when the control line P becomes @0'', the wiring capacitance and wiring resistance on the X@ and Y sides are also separated.

In this embodiment, the operation of reading the contents of the status register 3 to the external data bus D via the data bus buffer 5 is as follows.

The data transfer control circuit 6 normally supplies an 11" signal to the bus switching circuits 7 and 8 via the control twin F,
These disconnection circuits are connected, but if there is a request to read the contents of the status register 3, a 0'' signal is supplied to the bus switching circuits 7S and 8 via the control line F. As mentioned above, the internal data bus input and internal data bus C are separated from internal data bus B, the load for driving internal data bus B is reduced, and the waveform output to data bus B is thereby reduced. Improves build-up characteristics and achieves high-speed data transfer.

As a control method by the data transfer control circuit 6,
As mentioned above, usually each internal data bus is connected and
Only when a request for high-speed data transfer between the status register 3 and the data bus buffer 5 occurs, the bus A8 and the bus C are controlled as separate units from the bus B.1. R1! is disconnected from the internal data bus la and internal data bus C, and the data bus buffer 5 and the status register 30 are always kept in a state where high-speed transfer is possible. For example, it is conceivable to consider a system in which the necessary switching circuits 7 and 8 are connected only when it is necessary to transfer data from the ALU 2 to the RAM 4, and control is performed so that the data transfer is performed. The latter method is
It is suitable for further increasing the speed of data transfer between the status register 3 and the data bus buffer 5.

It should be noted that one or more embodiments of the present invention are shown, and the present invention is not limited to the above embodiments.

For example, in the present embodiment, the configuration is such that particularly high-speed transfer can be performed between the data bus buffer 5 and the status register 3, but this is merely an example.

In particular, functional blocks that require high-speed transfer are arranged so that they can be connected using relatively short internal data buses.
It is also possible to connect a portion that does not require such high-speed transfer to an internal data bus via a bus switching circuit, and place the functional blocks therebelow. Therefore, the number of internally included bus switching circuits can be any number as required.

Furthermore, path switching circuits are placed at appropriate points on the internal data bus, and when transferring data between one functional block, the internal data bus portions that are unnecessary for this data transfer are within the range allowed by the above-mentioned arrangement of the bus switching circuit. It is also possible to adopt a method in which the data transfer control circuit is controlled from the necessary part as much as possible with the data transfer control circuit inside the X.

〔Effect of the invention〕

As described above, the present invention provides a bus switching circuit using a transfer gate that allows the internal data bus of a semiconductor integrated circuit to be disconnected/connected midway, and a data transfer circuit for controlling disconnection/connection of this circuit. Control circuit and seven provided between specific functional blocks, thereby featuring high-speed data transfer! High-speed data transfer is achieved by separating the connected internal data bus section from the internal data bus section that is unnecessary for this data transfer, reducing the load for driving the data bus section, and improving the build-up characteristics of the transmission waveform. It can be realized.

The present invention is particularly effective when applied to cases where high-speed data transfer is required between specific functional blocks within a semiconductor integrated circuit.

[Brief explanation of drawings]

ff, FIG. 1 is a block diagram showing an embodiment of the present invention. Figure Wc2 is a circuit diagram showing details of the bus cut* circuit used in this embodiment. 1.--.. LE OM, 2.--.MU LU (operation unit), 3.--.Status register, 4.--.
...14AM, 5...Data bus buffer, 6...Data transfer control circuit, 7.8...
...Path switching circuit.

Claims (1)

[Claims] A bus switching circuit having a transfer gate capable of electrically disconnecting/connecting at least a part of an internal data bus that interconnects functional blocks such as ROM, RAM, and ALU (arithmetic unit); cutting/
It has a data transfer control circuit for controlling connections, and an internal data bus section that connects specific functional blocks that require high-speed data transfer and an internal data bus section that does not require high-speed data transfer are electrically connected. A data transfer circuit characterized by being separable.