JPH0262141A - Inter-block transfer control system - Google Patents

Abstract

PURPOSE:To efficiently execute data transfer between plural blocks by individually controlling a gate circuit by a transfer control part. CONSTITUTION:A bidirectional data bus 4 is provided through gate circuits 3-1 to 3-n of respective inter-block control parts 2-1 to 2-n at plural blocks 1-1 to 1-n and corresponding to the number of transfer bits and a transfer direction, a transfer control part 5 individually controls gate circuits 3-1 to 3-k. For example, between a block 1-1 and a block 1-2, data are transferred by using a part of the bus 4, simultaneously, the remaining part of a spring 4 is used, data can be transferred, the transfer direction can be also controlled in units of the bit, the bus is used at the same time, in the different transfer direction or by the combination of the number of the transfer bit and data can be transferred efficiently between blocks. By such a constitution, even in the multiplexing device to accommodate the media of respective types of speed, the use efficiency of the data bus can be improved by optimizing the data set to the inter-block control part.

Description

[Detailed Description of the Invention] [Summary] Regarding a data transfer control method for transferring data between multiple blocks in a time division multiplexing device, the purpose of this method is to efficiently transfer data between blocks. A bidirectional data bus connects the plurality of blocks through a gate circuit of an inter-block control section provided in each block, and the gate circuits are individually transferred according to the number of transfer bits and the transfer direction. It is configured to be controlled by a control section.

[Industrial application field]

The present invention relates to a data transfer control method for transferring data between a plurality of blocks in a time division multiplexing device.

In order to accommodate a large number of channels, a time division multiplexing device is composed of multiple blocks, and each block is connected by a bidirectional data bus that transfers data in parallel. There is a need to further improve the efficiency of data transfer between blocks in a time division multiplexing device having such a configuration.

[Conventional technology]

A conventional time division multiplexing device has, for example, a configuration shown in FIG. 8, where 31 is a time division multiplexing device, and 32
is a terminal device, 33 is a private branch exchange, 34 is a telephone, 35-
1 to 35-n are blocks, 36 is a common control unit, 37 is a data bus, 38-1 to 38-n are inter-block control units, 3
9-1 is a line interface section, and 39-2 to 39-n are terminal interface sections. Blocks 35-1 to 35
-n is generally composed of an arbitrary number of cards, and cards are implemented according to the required functions of the block.

In addition, additional blocks are installed in response to changes in the number of lines accommodated.

Further, between each block 35-1 to 35-n, inter-block control units 38-1 to 38-n are connected via a data bus 37 capable of bidirectional transmission.
38-n, data is transferred in parallel.

The block 35-1 receives and processes the data transferred from the blocks 35-2 to 35-n via the data bus 37 using the inter-block control unit 38-1, multiplexes the data, and transmits the data via the line interface unit 39-1. and distributes the multiplexed data received via the line interface section 39-1 from the inter-block control section 38-1 to the blocks 35-2 to 35-n via the data bus 37. It is.

Inter-block control unit 38 of each block 35-1 to 35-n
-1 to 38-n have the configuration shown in FIG. 9, for example,
Gate circuit 41 1a to 4l-k including a lotus driver etc.
a, a gate circuit 41-1 b including a bus receiver, etc.
4l-kb is reciprocally controlled by the direction control circuit 43 by the inverter 42, and data is transferred from the internal bus to the data bus side or from the data bus to the internal bus side.

Information for controlling such gate circuits is provided by the common control section 3.
Transferred from 6.

[Problem to be solved by the invention]

Since the media accommodated in the multiplexing device 31 is not a single type such as only audio, but there are many types including image information, etc., and the transmission speeds differ accordingly.
The multiplexing device 31 also needs to have a configuration that corresponds to the type of storage media. However, when manufacturing the multiplexing device 31 with a configuration compatible with the storage media, high-mix low-volume production is required, resulting in an increase in costs.

In addition, since the inter-block control units 38-1 to 38-n of the conventional example only collectively control the transfer direction by the direction control circuit 43, the number of parallel transfer bits is smaller than the data bus width, as in low-speed data. Even in this case, data transfer is performed by occupying the entire data bus 37. Therefore, there is a drawback that the transfer efficiency of the data bus 37 is reduced. In particular, the number of implemented blocks 35-1 to 35-n increases,
When a mixture of high-speed data and low-speed data is transferred via the data bus 37, the data bus 37 cannot be used effectively, resulting in a drawback that the number of channels that can be accommodated is limited.

An object of the present invention is to efficiently transfer data between blocks.

[Means to solve the problem]

The inter-block transfer control system of the present invention allows a data bus to be divided and used, and will be explained with reference to FIG.

Gate circuits 3-1 to 3- for inter-block control units 2-1 to 'l-n provided in a plurality of blocks 1-1 to 1-n, respectively.
block 1-1 by bidirectional data bus 4 via k
.about.l-n, and individually control gate circuits 31 to 3-k according to the number of transfer bits and the transfer direction.
It is controlled by

[Effect]

Gate circuits 3-1 to 2-n of inter-block control units 2-1 to 2-n
3-k individually by the transfer control unit 5, for example, data can be transferred between block ti and block 1-2 using a part of the data bus 4, and at the same time, the data can be transferred between block t-i and block 1-2. The remainder of data bus 4 can be used to transfer data between block 1-1 and block 1n.

Furthermore, the transfer direction can also be controlled on a bit-by-bit basis. Therefore, the data bus side can be used effectively.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is an explanatory diagram of the inter-block control section of the embodiment of the present invention, which controls gate circuits 7-1a to 7-ka and 7 lb to 7-kb connected to data buses 4-1 to 4-k. , can be individually controlled by a transfer control section 5, and control information is added from a common section 6 of the multiplexing device.

FIG. 3 is an explanatory diagram of gate circuit control. When data buses 4-1 to 4-8 of 8-bit width are provided, transfer control unit 5 to gate circuits 7-1a to 7-8a (1a) to ( 8a
), only the gate circuits 7-1a to 7-4a are opened at time t1, and 4 bits can be sent in parallel to the data buses 4-1 to 4-4. At this time, if a gate control signal is applied to the gate circuits 7-5b to 7-8b, 4-bit parallel data can be taken in from the data buses 4-5 to 4-8 at the same time t1.

Also, at time t2, only gate circuits 7-5a to 7-8a are opened and 4-bit parallel data is transferred to data buses 4 to 5 to 4.
-8. Also, at time t3, all gate circuits 7-1a to 7-8a are opened and 8-bit parallel data can be sent to data buses 4-1 to 4-8. Also, at time t4, gate circuits 7-1a to 7-8a
are all closed, and the data buses 4-1 to 4-8 are used by other blocks. At time L5, only gate circuit 7-1a is opened and 1-bit data is sent to data bus 4-1.

As mentioned above, since the gate circuits can be controlled individually,
For example, as shown in FIG. 4, data A of 4 bits b1 to b4 between blocks at time t4, time t. 1, if it is necessary to transfer data B of 4 bits b1 to b4 between other blocks, at the same time t, 8 bits b
It can be transferred as data A and B of 1 to b8.

Therefore, at the next time tjl, it becomes possible to transfer other data, and the data bus 4 can be used effectively.

Figure 5 shows a processing flowchart of the common part, in which a setting start is input from the outside, and a specified card (multiplexing processing card, code conversion processing card, etc.) in the specified block and other specified blocks are input according to the media type, etc. When the transfer conditions (transfer direction, number of transfer bits, etc.) with the specified card are input, the common unit 6 of the multiplexing device sets the required setting conditions to 61! ■ Calculate the setting data of the inter-block control section ■. That is, the data to be set in the inter-block control section is calculated in accordance with the conditions under which the data bus 4 can be used effectively, taking into consideration the data transfer conditions between other blocks. Set the calculated data in the random access memory etc. of the inter-block control section.■
, ends the process. Then, the inter-block control section controls the gate circuit according to the set data.

FIG. 6 is a block diagram of the main parts of the multiplexing device according to the embodiment of the present invention, in which blocks 11-1 to 11-3 are blocks 12-1 to 12-1.
-3 is an inter-block control unit, 13-1.13-2 is a compression/expansion processing unit, 14-11 to 14-1m, 14-21 to 14
-2m is an interface section, 15-1 to 15-3 are internal buses, 16 is a path setting section, 17-1.17-2 is a line interface section, 18 is a data bus, and each section can be configured as a card. can. In addition, the common part is omitted from illustration, and the inter-block control parts 12-1 to 12-3 include a fifth
The data calculated by the process described with reference to the figure is set.

Switching equipment and interface unit 14-11 to which illustration is omitted
14-1m, 14-21~14-2m are connected, and the interface parts 14-11~14-1m, 14-21~
The audio signal between the 14-2m and the compression/expansion processing unit 13-1.13-2 connected via the internal bus 15-1.15-2 is transferred as a 64 K b/s PCM signal, for example. The data is compressed to, for example, 32 Kb/s by the compression/decompression processing unit 13-1.13-2, and then sent to the inter-block control unit 12 via the internal bus 15-1.15-2.
-1.12-2 as 32 Kb/s data, and is transferred from the inter-block control section 12-1.12-2 to the inter-block control section 12-3 of the block 11-3 via the data bus 18. Transferred as 32 Kb/s data.

In block 11-3, the internal bus 1 is
Line interface section 17-1.17- via 5-3
2, and the line interface section 17-1.17-
2 to the line. Also, line interface section 17
-1.17-2 The data received via internal bus 1
5-3 to the path setting unit 16, where it is controlled according to call control data, etc., and transferred to the inter-block control unit 12-3 via the internal bus 15-3, and from the inter-block control unit 12-3. The data is transferred to the inter-block control unit 12-1.12-2 via the data bus 18.

In the block 11-1.11-2, the compression/expansion processing section 13-1.
The 32 Kb/s data transferred to 13-2 via the internal bus 15-1 and 15-2 is 64 Kb
/s PCM signal, and the internal bus 15-1.
Interface units 14-11 to 14- via 15-2
1m, transferred to 14-21 to 14-2m.

FIG. 7 is an explanatory diagram of data transfer. At time Tl, all the gate circuits of the inter-block control units 12-1 to 12-3 of each block 11-1 to 11-3 are closed, and the block Internal bus 1 between cards in 11-1 to 11-3
Data is transferred via 5-1 to 15-3.

At the next time T2, from block 11-1 to data bus 1
8 is used to send data A1, and block 11
-2 to data B1 using the remaining half of the data bus 18.
In block 11-3, data AI and Bl are simultaneously received from different blocks 11-1 and 11-2. In this case, the transfer directions of data AI and Bl can also be reversed.

At the next time T3, data A2 is transferred using all data buses 18 between blocks 11-1 and 11-3, and at next time T4, all data buses 18 are used between blocks 11-211-3. This shows the case where data B2 is transferred using .

As mentioned above, at time T2, the inter-block control unit 1
By individually controlling the gate circuits 2-1 to 12-3, different data can be transferred at the same time via the data bus 18, as shown in FIG.

Therefore, internal bus 15- of block 11-1-11-3
Since it is possible to separate blocks 1 to 15 to 3 from the data bus 18 and operate each block 11-1 to 11-3 independently, the same program including compression/decompression processes 513-x and 13-2 can be used. Even if the number of data transfers between cards increases, throughput can be prevented from decreasing.

Furthermore, the bit width of the data bus 18 is increased to enable high-speed data transfer, and for low-speed data, the data bus 18 can be divided to transfer multiple types of data at the same time. That is, the data bus 18 can be effectively used to transfer data between blocks.

〔Effect of the invention〕

As explained above, the present invention allows the data bus 4 to be transferred in different transfer directions or in different combinations of transfer bit numbers at the same time by individually controlling the gate circuits 3-1 to 3-k by the transfer control unit 5. Since it can be used, it becomes possible to efficiently transfer data between the plurality of blocks 1-1 to 1-n. Therefore, even in a multiplexing device that accommodates media of various speeds, the inter-block control section 2-1
By optimizing the data set to 2-n, the usage efficiency of the data bus 4 can be improved and the number of accommodated channels can be easily increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a diagram explaining the inter-block control section of the embodiment of the present invention, FIG. 3 is a diagram explaining gate circuit control, FIG. 4 is a diagram explaining individual control, and FIG. 6 is a block diagram of main parts of a multiplexing device according to an embodiment of the present invention, FIG. 7 is an explanatory diagram of data transfer, and FIG. 8 is an explanatory diagram of a time division multiplexing device. FIG. 9 is an explanatory diagram of a conventional inter-block control section. 1-1 to -1-n are blocks, 2-1 to 2-rl are inter-block control units, 3-1 to 3- are gate circuits 4-1 to 4 are data buses, and 5 is a transfer side opening. , 6 is the common part, 7-1 a ~ 7 ka. b to 7-kb are gate circuits.

Claims (1)

[Claims] A gate circuit (3-1) of an inter-block control section (2-1 to 2-n) provided in each of a plurality of blocks (1-1 to 1-n).
1 to 3-k), the plurality of blocks (1-1 to 1-n) are connected by a bidirectional data bus (4), and the gates are connected in accordance with the number of transfer bits and the transfer direction. An inter-block transfer control method characterized in that the circuits (3-1 to 3-k) are individually controlled by a transfer control unit (5).