JP2000252868A - Cdma communication equipment and its automatic gain control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce circuit scale and to decrease power consumption by limiting a dynamic range of each circuit configuring a reception system of equipment, especially for each circuit after a secondary demodulation section so as to reduce the required number of bits. SOLUTION: This CDMA communication unit is provided with a 1st AGC circuit 18, that properly keeps a signal level of a received digital signal outputted from an A/D converter 14, and additionally, with a 2nd AGC circuit 19. The input signal lever to a correlator 16 is variable controlled on the basis of an output signal level of a digital filter 15, so as to keep an input signal level to the correlator 16 at a proper value by the 2nd AGC circuit 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, Code Division Multiple Access (CDMA).
s) The present invention relates to a CDMA communication device used in a cellular mobile communication system employing the system and an automatic gain control circuit thereof.

[0002]

2. Description of the Related Art In recent years, a CDMA system has attracted attention as a wireless access system between a base station and a mobile station in a mobile communication system. The CDMA system is a system in which different codes are assigned to a plurality of channels, and information signals of each channel are spread using the codes to transmit the signals using a common frequency band.

In a CDMA communication apparatus used as a base station or a mobile station in this type of system, automatic gain control (AGC) of a received signal is performed in order to perform stable despreading and data demodulation. It is essential.

FIG. 6 shows a conventional CDM having an AGC circuit.
FIG. 2 is a circuit block diagram illustrating a configuration example of a communication device A. In FIG. 1, a spread spectrum signal received by an antenna 1 is frequency-converted to an intermediate frequency or a baseband frequency by a radio unit 2, an unnecessary wave component is removed by a filter 3, and then analog / digital (A / D / A / D). ) Converted to a digital signal by the converter 3. Then, the received digital signal is input to the correlator 6 after the noise component outside the desired frequency band is removed by the digital filter 5. In the correlator 6, the received digital signal is subjected to a despreading process using a spreading code corresponding to a channel to be received by itself. The primary modulation signal obtained by the correlator 6 is primary-demodulated by the data demodulation unit 7, whereby digital data is reproduced.

The A / D converter 4 converts a signal from the radio unit 2 into a digital signal having a predetermined number of bits. If the input level of the received signal to the A / D converter 4 is low, The converted digital signal is represented by only lower-order bits, resulting in a very large quantization error, and as a result, data quality deteriorates. Conversely, if the input level of the received signal is too high, the signal overflows beyond the dynamic range of the A / D converter 4, which also leads to data quality degradation.

FIG. 7 shows a relationship between an input level of a received signal to the A / D converter 4 and a received digital signal output from the A / D converter 4. Here, A
The / D converter 4 has a conversion level of 3 bits and performs conversion by 2's complement.

First, when a reception signal of an appropriate level is input as shown in FIG. 7 (a), the reception digital signal after conversion can take eight levels that can be expressed by three bits. Therefore, the quantization noise is -6d per bit.
The B conversion is -18 dB or less, which is equivalent to 3 bits, and the A / D converter 4 does not cause an overflow, so that the 3-bit A / D converter 4 can be effectively used.

On the other hand, when the input level of the received signal is low as shown in FIG. 7 (b), the A / D converter 4 uses only the lower bits although the number of bits is three.
For example, in FIG. 7B, substantially only one or two bits are used. For this reason, the quantization noise becomes -12 dB or more, resulting in a quality deterioration of 6 dB or more despite the use of the 3-bit A / D converter 4.

Conversely, when the input level of the received signal is high as shown in FIG. 7C, the A / D converter 4 causes an overflow. Therefore, only three-level digital values can be obtained despite the use of the 3-bit A / D converter 4, which also degrades data quality.

Therefore, an AGC circuit 8 is provided.
The C circuit 8 always keeps the input level to the A / D converter 8 at an appropriate value. That is, the A / D converter 4
The power value of the received digital signal output from is calculated by the power calculator 8b, and the averaging circuit 8c calculates the average power of a predetermined section based on the calculated power value. In the comparison circuit 8d, the value of the average power is compared with a predetermined threshold value, and the difference signal is integrated by the loop filter 8e with a predetermined time constant, and then given to the variable gain amplifier 8a as a gain control signal. Therefore, the variable gain amplifier 8a
Of the A / D converter 4 from the radio unit 2
Is always kept at a constant value.

FIG. 8 shows a configuration of a conventional CDMA communication apparatus using another AGC circuit. This A
The GC circuit 9 has a function of not only adjusting the input level to the A / D converter 4 but also controlling the subsequent input level to the circuit including the correlator 6 to an appropriate value. That is, the power value of the output signal of the correlator 6 is calculated by the power calculator 9b, and the average value is obtained by the averaging circuit 9c. Then, the difference between the average power value and the threshold value is obtained by the comparison circuit 9d, and the difference output is provided to the variable gain amplifier 9a via the loop filter 9e, and the level of the received signal level is adjusted. Even with such an AGC circuit, the input signal level to the A / D converter 4 can be stabilized at an appropriate value.

[0012]

However, the above-mentioned conventional AGC circuit is configured in accordance with an AGC circuit used in a communication device such as a TDMA system.
When used in a CDMA communication device for DMA, there is a problem to be solved.

That is, in a TDMA system device, A /
It is assumed that an interference wave existing in a band other than the desired band of the signal input to the D converter is sufficiently suppressed by the filter of the radio unit.

FIG. 9 is a schematic configuration diagram of a radio unit to which the super heterodyne system is applied. The radio frequency signal received by the antenna 1 is sequentially passed through filters 2a, 2b, and 3 to out of a desired band. Is suppressed.

In a cellular radio communication system adopting the TDMA system, since the total number of channels used for communication is generally large, by combining base station arrangement and frequency arrangement, adjacent channels are not used between base stations close in distance. Like that. Therefore, in the mobile station, it is possible to design a system on the assumption that there is no large-strength signal in the adjacent channel, and the signal to be suppressed by the filters 2a, 2b, 3 is the next adjacent channel signal. FIG. 10 (a),
(B) shows the situation. Even if a signal larger by several tens of dB is added to the signal of the next adjacent frequency band, the interference wave U1 of the next adjacent frequency band is filtered by the filter (total frequency) of the radio unit. With response F1)
As shown by 1 ', the signal is sufficiently suppressed, and the signal D1 in the desired frequency band is dominant in the input signal level to the A / D converter.

On the other hand, in a cellular radio communication system adopting the CDMA system, the number of frequency bands to be used is very small, and therefore, a frequency arrangement is set such that adjacent base stations do not use adjacent frequency bands. It is very difficult to take. For this reason, a high-power received signal is input also in an adjacent frequency band. FIG. 11 (a)
(C) shows the situation. Assuming that the signal U2 in the adjacent frequency band is several tens of dB higher than the signal D2 in the desired frequency band, the filters 2a, 2b, and 3 (frequency response F2) of the radio unit use the signal U2 in the adjacent frequency band. Cannot be sufficiently removed, and the signal U2 'in the adjacent frequency band remains as a signal having a higher level than the signal D2' in the desired frequency band even after passing through the filter. In this case, the input to the A / D converter 4 is a signal obtained by adding the signal U2 'of the adjacent frequency band to the signal D2' of the desired frequency band, and the power of the input signal is the signal component U2 'of the adjacent frequency band. Becomes dominant.

In response to such an input, the conventional AGC
In order for the CDMA communication device including the circuit 8 or 9 to perform stable despreading processing and data demodulation processing, it is necessary to set an excessive dynamic range in the correlator 6 and the data demodulation unit 7 at the subsequent stage.

That is, the AGC circuit 8 shown in FIG.
The input level is adjusted to an appropriate level based on the output level of the A / D converter 4. Therefore, when the signal level of the adjacent frequency band is sufficiently low, the AGC circuit 8 performs an operation of maintaining the signal level of the desired frequency band at an appropriate level. However, when the signal in the adjacent frequency band is largely dominant, the AGC circuit 8 performs an operation of maintaining the signal level in the adjacent frequency band at an appropriate level. Therefore, the signal level in the desired frequency band becomes a very small value.

On the other hand, as the digital filter 5, a filter which has a very good matching to a signal in a desired frequency band is usually used. This is because the digital filter 5 can relatively easily form a high-order filter, and does not need to consider an error margin due to variations in components as in an analog circuit. For this reason, when the output signal of the A / D converter 4 is passed through a digital filter 5 having a frequency response F3 matched with the frequency characteristics of the desired frequency band, as shown in FIG. Is output from the digital filter 5 as it is and supplied to the correlator 6.

Therefore, when the signal level of the adjacent frequency band is extremely small, a signal of a sufficiently large level is output from the A / D converter 4 and passes through the digital filter 5 as it is and is input to the correlator 6. Conversely, when the signal level of the adjacent frequency band is very high, the AGC circuit 8 outputs a signal of a very low level in the desired frequency band from the A / D converter 4, which passes through the digital filter 5 as it is. And input to the correlator 6. That is, the signal level of the desired frequency band input to the correlator 6 greatly varies depending on whether the signal level of the adjacent frequency band is high or not.

In order to stably operate each circuit downstream of the correlator 6 in response to such a change in the input signal level, the dynamic range of each circuit downstream of the correlator 6 must be set sufficiently large. For this purpose, the number of bits in each circuit after the correlator 6 must be significantly increased from the number of bits normally required. For example, when trying to secure a dynamic range of 30 dB, the correlator 6 and the data demodulation unit 7 downstream of the digital filter 5 need to extend the dynamic range of 5 bits more than the normally required number of bits. .
If the dynamic range of each circuit subsequent to the correlator 6 is set to be large as described above, the circuit scale is increased and power consumption is increased, which is not preferable.

On the other hand, the second AGC circuit 9 performs AGC control so as to keep the output of the correlator 6 at an appropriate level. However, when the signal of the adjacent frequency band is not considered, the A / D control is performed.
When the input level of the converter 4 is saturated or the input level is excessively lowered, quantization noise increases.
Although the correlator 6 and the data demodulation unit 7 may have a normal number of bits, the dynamic range of the A / D converter 4 and the digital filter 5 must be set wide accordingly.
Also in this case, an increase in circuit size and an increase in power consumption are unavoidable.

The present invention has been made in view of the above circumstances, and has as its object to reduce the number of necessary bits by limiting the dynamic range of a circuit, thereby reducing the circuit scale and reducing power consumption. And an automatic gain control circuit for the CDMA communication device.

[0024]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a radio receiving section for receiving a code division multiplexed spread spectrum signal and outputting the received signal, and a radio signal output from the radio receiving section. An analog / digital converter for converting the received signal into a digital signal; a digital filter for extracting a signal corresponding to a desired frequency band from the received digital signal output from the analog / digital converter; A secondary demodulation unit for despreading the output signal and outputting a primary modulation signal, and a primary demodulation unit for demodulating the primary modulation signal output from the secondary demodulation unit. A first automatic gain control circuit and a second automatic gain control circuit.

Then, by the first automatic gain control circuit,
In order to keep the level of the received digital signal output from the analog / digital converter in a predetermined range, the signal is input from the wireless receiver to the analog / digital converter based on the output signal level of the analog / digital converter. The level of the received signal is variably controlled, and the second automatic gain control circuit controls the level of the input signal to the secondary demodulation section based on the output signal level of the digital filter so as to maintain the input signal level in a predetermined range. The input signal level to the secondary demodulation unit is variably controlled.

Therefore, according to the present invention, even if the level of the received signal output from the radio receiver changes, the level of the input signal to the analog / digital converter is always set to an appropriate value by the first automatic gain control circuit. Will be retained.

In addition, at the subsequent stage of the digital filter,
Two automatic gain control circuits are provided. Therefore, even if the received signal level of the desired frequency band output from the digital filter fluctuates greatly according to the level of the received signal level of the adjacent frequency band, this fluctuation is absorbed by the second automatic gain control circuit, and the fluctuation is absorbed. As a result, the signal level input to the secondary demodulation unit is kept at an appropriate value. Therefore, it is not necessary to set the dynamic range of the correlator or the matched filter constituting the secondary demodulation section and the dynamic range of the subsequent primary demodulation section wide. The circuit scale after the section is greatly reduced,
In addition, power consumption can be reduced.

Further, according to the present invention, the second automatic gain control circuit includes a first gain control circuit for maintaining an input signal level to a secondary demodulation unit within a predetermined range based on an output signal level of a digital filter. A first gain control unit for generating an amount, and a second gain for maintaining an input signal level to the secondary demodulation unit within a predetermined range based on a level of the primary modulation signal output from the secondary demodulation unit. A second gain control unit for generating a control amount; and a first gain control amount generated by the first gain control unit and a second gain control amount generated by the second gain control unit. And a first level variable circuit that variably controls the level of an input signal to the secondary demodulation unit based on the total gain control amount.

With this configuration, in the second automatic gain control circuit, in addition to the output level of the digital filter, the output level of the secondary demodulation unit is taken into consideration, and the input signal level control to the secondary demodulation unit is performed. Is performed. For this reason, even if the noise level included in the received signal input to the secondary demodulation unit changes due to a change in channel quality or the presence or absence of interference, the signal is input to the secondary demodulation unit by the operation of the second gain control unit. The level of the received signal is always kept at an appropriate value. Therefore, it is not necessary to provide a large dynamic range to the circuits subsequent to the secondary demodulation unit. As a result, the number of bits of the circuits subsequent to the secondary demodulation unit is further reduced, and the circuit scale and power consumption are further reduced. Becomes possible.

Further, according to the present invention, the second automatic gain control circuit includes a first gain control circuit for maintaining an input signal level to a secondary demodulation unit within a predetermined range based on an output signal level of a digital filter. A first gain control unit for generating an amount, and a third gain control unit for maintaining an output signal level of the secondary demodulation unit within a predetermined range based on information indicating a spread code length used in the secondary demodulation unit. A third gain control unit for generating the gain control amount of the first gain control unit, a third gain control amount generated by the first gain control unit, and a third gain control amount generated by the third gain control unit. And a second level variable circuit that variably controls an input signal level to the secondary demodulation unit based on the total gain control amount. It is also characterized.

With this configuration, even if the spread code length is changed in accordance with, for example, a change in the transmission rate, and the output level of the secondary demodulation unit is changed accordingly, the third code is used.
By the gain control operation of the gain control unit, the input signal level to the secondary demodulation unit is always kept at an appropriate value. Therefore, also in this case, it is not necessary to provide a circuit having a large dynamic range after the secondary demodulation section, thereby suppressing the required number of bits of the circuit after the secondary demodulation section, thereby reducing the circuit scale and reducing power consumption. Electrification is maintained.

Further, the present invention further includes a third automatic gain control circuit, and the second automatic gain control circuit uses the third automatic gain control circuit to maintain the input signal level to the primary demodulation section within a predetermined range. It is also characterized in that the level of the input signal to the primary demodulation unit is variably controlled based on the level of the primary modulation signal output from.

With this configuration, even if the output signal level of the secondary demodulation unit changes, the input signal level to the primary demodulation unit is always kept at an appropriate value by the third automatic gain control circuit. . For this reason, it is not necessary to provide a large dynamic range to the primary demodulation unit, whereby the required number of bits of the primary demodulation unit is suppressed, and the circuit scale and power consumption can be reduced.

[0034]

(First Embodiment) FIG. 1 is a circuit block diagram showing a first embodiment of a CDMA communication apparatus according to the present invention.

In FIG. 1, a spread spectrum signal received by an antenna 11 is frequency-converted to an intermediate frequency or a baseband frequency by a radio unit 12, an unnecessary wave component is removed by a filter 13, and then an analog / digital ( The signal is sampled by an A / D converter 13 and converted into a digital signal. Then, the received digital signal is input to the correlator 16 after noise components outside the desired frequency band are removed by the digital filter 15. In the correlator 16, the received digital signal is subjected to a despreading process using a spreading code corresponding to a channel to be received by itself. The primary modulation signal obtained by the correlator 16 is primary-demodulated by the data demodulation unit 7, whereby digital data is reproduced. When performing RAKE reception, the correlator 16 is composed of a plurality.

By the way, the CDMA communication apparatus of this embodiment has a first automatic gain control circuit (first AGC circuit) 1
8 and a second automatic gain control circuit (second AGC circuit) 1
9 is provided.

The first AGC circuit 18 includes the A / D converter 1
4 for stabilizing the level of the received signal input to the A / D converter 14 to an appropriate value based on the power level of the received digital signal output from the receiver 4, and is provided between the radio unit 12 and the filter 13. And a variable gain amplifier 18a, an AGC signal generator 18g, and an adder 18f. The AGC signal generator 18g includes a power calculator 18b,
An averaging circuit 18c, a comparison circuit 18c, and a loop filter 18e are provided.

The power calculator 18b calculates the power value of the received digital signal output from the A / D converter 14.
The averaging circuit 18c operates the power calculator 1 every predetermined period.
The average of the power values calculated by 8b is calculated. The comparison circuit 18d compares the average power value calculated by the averaging circuit 18c with a preset threshold value and outputs the difference. The loop filter 18e is connected to the comparison circuit 18
The difference signal output from d is smoothed with a predetermined time constant and output as a gain control signal. The adder 18f adds "1", which is the initial offset value of the variable gain amplifier 18a, to the gain control signal output from the comparison circuit 18d, and supplies the output signal to the variable gain amplifier 18a to variably control the gain. I do.

On the other hand, the second AGC circuit 19 sets the output signal level of the digital filter 15 to an appropriate value and then inputs it to the correlator 16, and is provided between the digital filter 15 and the correlator 16. Multiplier 19a,
It comprises an AGC signal generator 19g and an adder 19f. The AGC signal generator 19g includes a power calculator 19b, an averaging circuit 19c, a comparison circuit 19c, and a loop filter 19e.

The power calculator 19b calculates the power value of the signal output from the digital filter 15. The averaging circuit 19c calculates an average of the power values calculated by the power calculator 19b every predetermined period. Comparison circuit 19d
Compares the average power value calculated by the averaging circuit 19c with a preset threshold value, thereby determining whether the input level to the correlator 16 is appropriate. The loop filter 19e averages the magnitude judgment values output from the comparison circuit 19d, and outputs this as a gain control signal. The adder 19f adds the initial value "1" to the gain control signal output from the comparison circuit 19d, and multiplies the output signal by the multiplier 19a to the output signal of the digital filter 15, thereby obtaining a correlator. The level of the input signal to 16 is varied. Note that, instead of the multiplier 19a, a bit shift circuit capable of controlling the power of 2 may be used.

With such a configuration, the received signal output from the radio section 12 is input to the A / D converter 14 after the signal level is fixed to an appropriate value by the first AGC circuit 18. You. For this reason, even if the received signal level changes due to the characteristic fluctuation of the transmission path state or the like, the A / D converter 1
4 is always kept at an appropriate value. Therefore, the A / D converter 14 always performs optimal quantization without setting a wide dynamic range.

On the other hand, the received digital signal output from the A / D converter 14 is passed through a digital filter 15 to extract only a desired frequency band component. Here, in the CDMA communication device, if the signal strength in the adjacent frequency band is largely dominant as compared with the signal strength in the desired frequency band, the first AGC circuit 18 performs the AGC operation on the signal in the adjacent frequency band. Therefore, the signal level of the desired frequency band output from the A / D converter 14 becomes extremely small. Therefore, from the digital filter 15,
A signal of a desired frequency band with a small level is output.

On the other hand, when the signal strength in the adjacent frequency band is small and the signal in the desired frequency band is dominant,
Since the first AGC circuit 18 performs an AGC operation on the signal in the desired frequency band, the signal level in the desired frequency band output from the A / D converter 14 is a signal of a sufficient magnitude. Therefore, the digital filter 15 outputs a signal in a desired frequency band having a sufficiently large signal level.

That is, the signal level of the desired frequency band output from the digital filter 15 largely changes in accordance with the magnitude of the adjacent frequency band signal. 1
A large dynamic range is required for each circuit after 6.

However, in the device of this embodiment, the signal of the desired frequency band output from the digital filter 15 is input to the correlator 16 after the signal level is fixed to an appropriate value by the second AGC circuit 19. Will be done. Therefore, the correlator 16 and the data demodulation unit 17 do not need to set the dynamic range excessively.
That is, the correlator 16 and the data demodulation unit 17
There is no need to prepare a redundant bit, so that the circuit configuration can be downsized and the power consumption can be reduced accordingly.

(Second Embodiment) FIG. 2 is a circuit block diagram showing a CDMA communication apparatus according to a second embodiment of the present invention. FIG. 3 shows only the configuration of the second AGC circuit according to this embodiment, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

Second AGC circuit 2 according to this embodiment
0 is a multiplier 20a provided between the digital filter 15 and the correlator 16 and the first AGC signal generator 20
b, a second AGC signal generator 20c, and an adder 20d
It is composed of Among them, the first AGC signal generator 2
0b is the AG of the second AGC circuit 19 described with reference to FIG.
It has the same configuration as the C signal generation unit 19g.

The second AGC signal generator 20c generates a second AGC signal for stabilizing the input level to the correlator 16 based on the output signal of the correlator 16. Of the primary modulation signal output from the correlator 16 to obtain an average value of the primary modulation signal at predetermined time intervals, compare the average power value with a threshold value, and output the comparison output to a loop filter. Generated by averaging.

The adder 20d includes a first AGC signal generated by the first AGC signal generator 20b and a second AGC signal.
The second AG generated by the AGC signal generation unit 20c of FIG.
The C signal is added, and "1" which is the initial value of the correlator 16 is further added thereto.

The multiplier 20a includes the digital filter 15
Is multiplied by the gain control value (weight coefficient) obtained by the adder 20d to control the level of the output signal of the digital filter 15,
The output signal of the digital filter 15 whose level is controlled is input to the correlator 16.

Although not shown in FIG. 2, A / D
A first AG for controlling the input signal level to the A / D converter 14 is provided on the input side of the converter 14 in the same manner as in FIG.
A C circuit 18 is provided.

With such a configuration, the signal output from the digital filter 15 is applied to the second AGC circuit 2
0, the gain is controlled by the first and second AGC signals respectively generated based on the output signal power of the digital filter 15 and the output signal power of the correlator 16, whereby the input signal level to the correlator 16 becomes It is fixed to an appropriate value.

With this configuration, the following effects can be obtained. That is, the input signal to the correlator 16 naturally includes noise and interference components, and the output signal level of the correlator 16 is lower when the noise or interference is large than when the noise is small. When noise and interference are small,
Even if the quantization noise is large, good quality can be obtained because the total noise amount is small.

Therefore, when the noise is large, that is, when the correlator 1
Correlator 16 required when output level of signal 6 decreases
Is calculated in advance, and a correlator 16 having a bit number corresponding to the output level is prepared. Then, as described above, the second output power of the correlator 16 is kept constant.
AGC signal generator 20c generates a second AGC signal, and controls the level of the input signal to the correlator 16 by the second AGC signal.
Is reduced, and as a result, the overflow of the arithmetic unit in the correlator 16 is prevented. In this case, the quantization noise is large, but the original noise is small, so the total noise amount is small, and as a result, the quality does not deteriorate.

On the other hand, when the noise level is high, a second AGC signal is generated by the second AGC signal generation section 20c so as to increase the input level to the correlator 16, and a digital filter is generated by the second AGC signal. 15 output signal levels are controlled. Therefore, quantization noise is suppressed, and an increase in the overall noise level is prevented.

As described above, in the second embodiment, the first AGC signal generator 20b and the second AGC signal generator 2b
Ob determines the overall gain control value based on the generated AGC signal, and controls the signal level input from the digital filter 15 to the correlator 16 based on the overall gain control value.

That is, the first AGC signal generator 20b
Although the noise level is not taken into account, a rough input level to the correlator 16 is determined based on the output signal power of the digital filter 15. On the other hand, the second AGC signal generation unit 20c generates a second AGC signal that controls the input level to the correlator 16 more finely in consideration of the noise level.

Therefore, according to the second embodiment, in addition to the average value of the output signal power of the digital filter 15,
By using the average value of the output signal power of the correlator 16 for generating the gain control signal, the number of bits of the correlator 16 can be further reduced, and as a result, the circuit size can be further reduced and the power consumption can be reduced. Electricity can be achieved.

In the CDMA system, multipaths are generally RAKE-combined. In the second embodiment, a second AGC signal generation unit 20c based on the output signal of the correlator 16
Generates the second AGC signal, the same control can be performed by using a RAKE combined output which is a result of in-phase combining output signals of a plurality of correlators. RAK
Since the E-combined output is a signal having higher reliability than the output of one correlator, it is possible to perform control with a smaller error.

In the circuit shown in FIG.
Although the AGC signals generated by the C signal generators 20b and 20c are combined by a simple adder 20d to generate a comprehensive AGC signal, the AGC signals generated by the AGC signal generators 20b and 20c are generated. The signals may be weighted or the like and then combined to generate a comprehensive AGC signal.

(Third Embodiment) A third embodiment according to the present invention
In the second embodiment, in the second AGC circuit, the input signal level to the correlator 16 is variably controlled in consideration of not only the output level of the digital filter 15 but also the output fluctuation of the correlator 16 due to the change of the spread code length. It is something to do.

That is, in the CDMA communication system, when communication is performed at different transmission speeds, the spreading code length is changed. Changing the spreading code length means changing the spreading code length used in the despreading process in the correlator, and as a result, the output signal level of the correlator also changes. When the output signal level of the correlator changes, the data demodulation unit at the subsequent stage requires a corresponding dynamic range, and it is necessary to provide redundant and additional bits.

In the third embodiment, focusing on this point, the second A is set according to the spreading code length used in the correlator 16.
The input signal level to the correlator 16 is made constant by varying the gain control amount of the GC circuit.

FIG. 3 shows a CD according to the third embodiment.
FIG. 3 is a circuit block diagram illustrating a main configuration of the MA device. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

Second control for controlling the input level to the correlator 16
The AGC circuit 21 includes a multiplier 21a provided between the digital filter 15 and the correlator 16, an AGC signal generation unit 21b, a spread gain control signal generation circuit 21d,
And a multiplier 21e. Among them, the AGC signal generation unit 21b is the second AGC circuit 19 described with reference to FIG.
Has the same configuration as that of the AGC signal generation unit 19g.

The spread gain control signal generating circuit 21d uses the correlator 16 to determine the spread code length in accordance with information indicating the spread code length notified from the main control unit 10 which controls the overall operation of the entire apparatus. A control amount (weighting coefficient) for spreading gain for compensating for an output variation generated when used is generated.

The spread gain control amount generated by the spread gain control signal generation circuit 21d is multiplied by the gain control amount generated by the AGC signal generation unit 21b in the multiplier 21e. The gain control amount obtained by the multiplier 21e is multiplied by the output signal of the digital filter 15 in the multiplier 21a.
Input signal level is controlled.

Although not shown in FIG. 3, A / D
A first AG for controlling the input signal level to the A / D converter 14 is provided on the input side of the converter 14 in the same manner as in FIG.
A C circuit 18 is provided.

With such a configuration, when the spread code length of the correlator 16 changes in accordance with the change of the transmission rate, the spread gain control amount according to the spread code length is increased in the spread gain control signal generation circuit 21d. The generated control amount for spreading gain is reflected on the AGC signal generated by the AGC signal generation unit 21b. Therefore, the digital filter 15
In addition to the fluctuation of the output signal level, the fluctuation of the output level of the correlator 16 due to the change of the spreading code length is suppressed.

Therefore, even if the spreading code length is changed,
The input signal level to the data demodulation unit 17 is always kept constant. For this reason, it is not necessary to provide the data demodulation unit 17 with the number of redundant / additional bits. As a result, the circuit scale is reduced and the power consumption is also reduced.

(Fourth Embodiment) In the third embodiment, the case where only one correlator 16 is provided has been described as an example. However, some CDMA communication apparatuses include a plurality of correlators, and perform communication using a plurality of communication channels simultaneously by assigning different spreading codes to these correlators. The AGC method described in the third embodiment is similarly applicable to such an apparatus.

FIG. 4 shows a main configuration of a CDMA communication apparatus according to a fourth embodiment of the present invention, which is provided with two correlators 161 and 162 and data demodulators 171 and 172. Second AGC circuit 2 used in this device
2 corresponds to the two correlators 161 and 162, and A
Two multipliers 22a and 22b for multiplying the GC signal, two adders 22c and 22d for adding the initial value, and two multipliers 22e and 22f for multiplying the control amount for the spreading gain.
, A control signal generation circuit for spread gain 22g, and an AGC signal generation unit 22h.

In the spread gain control signal generation circuit 22g,
The correlator 16 according to the information indicating the spreading code length notified from the main control unit 10 that comprehensively controls the operation of the entire apparatus.
At steps 1 and 162, a spread gain control amount (weight coefficient) corresponding to the spreading code length being generated is generated.

The spread gain control amounts generated by the spread gain control signal generation circuit 22g are multiplied by the gain control amounts generated by the AGC signal generation unit 22h in multipliers 22e and 22f, respectively. The gain control amounts obtained by the multipliers 22e and 22f are respectively multiplied by the output signals of the digital filter 15 in the multipliers 22a and 22b, whereby the input signal levels to the correlators 161 and 162 are respectively adjusted. Controlled.

Although not shown in FIG. 4, A / D
A first AG for controlling the input signal level to the A / D converter 14 is provided on the input side of the converter 14 in the same manner as in FIG.
A C circuit 18 is provided.

With such a configuration, the correlator 16
Even when the despreading process using different spreading code lengths is performed in the correlators 161, 161,
The input signal level to the correlators 161 and 162 is controlled so that the correlation output level becomes constant according to the spread code length for each of the two. Therefore, the data demodulation unit 171,
The level of the input signal to 172 is always kept constant. As a result, it is not necessary to provide additional bits in the data demodulation units 171 and 172, thereby making it possible to reduce the circuit scale and reduce power consumption.

(Fifth Embodiment) The fifth embodiment of the present invention relates to the first and second AGCs described in the first embodiment.
In addition to the circuits 18 and 19, a third AGC circuit 23 for controlling the input signal level to the data demodulation unit 17 to be constant according to the output level of the correlator 16 is provided.

FIG. 5 is a circuit block diagram showing the configuration of the main part. The third AGC circuit 23 includes a multiplier 23a provided between the correlator 16 and the data demodulation unit 17,
It has a signal generator 23b and an adder 23c.

The AGC signal generator 23b outputs the second AGC signal
It has the same configuration as the AGC signal generator 19g of the circuit 19, calculates the output power value of the correlator 16 by a power calculator, obtains the average value by an averaging circuit, and calculates the average power value by a comparison circuit. A third AGC signal is generated by comparing the determination output with a threshold value with a loop filter.
The third AGC signal has an initial value "1" at an adder 23c.
Is given to the multiplier 23a, where the output signal of the correlator 16 is multiplied.

Although not shown in FIG. 5, A / D
A first AG for controlling the input signal level to the A / D converter 14 is provided on the input side of the converter 14 in the same manner as in FIG.
A C circuit 18 is provided.

With this configuration, even if the output level of the correlator 16 fluctuates, the input signal level to the data demodulation unit 17 is always kept at an appropriate value by the third AGC circuit 23. Therefore, it is not necessary to prepare redundant / additional bits in the data demodulation unit 17, and as a result, the circuit scale is reduced and the power consumption is reduced.

The present invention is not limited to the above embodiments. For example, in each of the above embodiments, the first
And each of the second AGC circuits 18 and 19, and
The case where the G circuits 23 are individually configured has been described. Among the circuits configuring the AGC circuits 18, 19, and 23, the processing by the circuits after the comparison circuit having a relatively slow processing speed is performed by one DSP ( (Digital Signal Processor).

In each of the above embodiments, the AGC circuit calculates the signal power and generates the AGC signal based on the average value. However, the AGC circuit detects the signal amplitude value instead of the signal power. The AGC signal may be generated based on the average value.

In addition, the circuit configuration of each AGC circuit, the configuration of the device, the type of the system and the configuration thereof can be variously modified without departing from the gist of the present invention.

[0085]

As described above in detail, according to the present invention, in addition to the first automatic gain control circuit for maintaining the level of the received digital signal output from the analog / digital converter within a predetermined range, the second automatic gain control circuit is provided. An automatic gain control circuit is newly provided, and the second automatic gain control circuit controls the secondary demodulation section based on the output signal level of the digital filter to maintain the input signal level to the secondary demodulation section within a predetermined range. Is variably controlled.

Therefore, according to the present invention, even if the received signal level in the desired frequency band output from the digital filter fluctuates greatly in accordance with the level of the received signal level in the adjacent frequency band, the second automatic gain control circuit makes it possible. , The signal level input to the secondary demodulation unit can always be maintained at an appropriate value. This provides a CDMA communication apparatus and an automatic gain control circuit capable of reducing the required number of bits by limiting the dynamic range of the circuits subsequent to the secondary demodulation section, thereby reducing the circuit scale and reducing power consumption. can do.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of a CDMA communication device according to the present invention.

FIG. 2 is a main part configuration diagram showing a second embodiment of the CDMA communication apparatus according to the present invention.

FIG. 3 is a main part configuration diagram showing a third embodiment of the CDMA communication apparatus according to the present invention;

FIG. 4 is a main part configuration diagram showing a fourth embodiment of the CDMA communication apparatus according to the present invention.

FIG. 5 is a main part configuration diagram showing a fifth embodiment of the CDMA communication apparatus according to the present invention;

FIG. 6 is a circuit block diagram showing a configuration of a conventional CDMA communication device provided with an AGC circuit.

FIG. 7 is a view for explaining an example of a relationship between an input and an output of an A / D converter.

FIG. 8 is a circuit block diagram showing a configuration of another conventional CDMA communication device including an AGC circuit.

FIG. 9 is a circuit block diagram illustrating a general configuration of a wireless unit.

FIG. 10 is a diagram for explaining an example of a frequency allocation and a filtering operation in a cellular mobile communication system employing a TDMA scheme.

FIG. 11 is a diagram for explaining an example of a frequency arrangement and a filtering operation in a cellular mobile communication system employing a CDMA system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Main control circuit 11 ... Antenna 12 ... Wireless part 13 ... Filter 14 ... Analog / digital converter (A / D) 15 ... Digital filter 16,161,162 ... Correlator 17,171,172 ... Data demodulation part 18 ... First automatic gain control circuit (first AGC circuit) 19, 20, 21, 22 ... second automatic gain control circuit (second AGC circuit) 23 ... third automatic gain control circuit (third AGC circuit) Circuit) 18a Variable gain amplifier 19a, 20a, 21a, 21d, 22a, 22b, 2
2e, 22f, 23a Multipliers 18b, 19b Power calculators 18c, 19c Averaging circuits 18d, 19d Loop filters 18f, 19f, 20d, 21c, 22c, 22d, 2
3c Adder 18g, 19g, 20b, 20c, 21b, 22h, 2
3b AGC signal generator 21d, 22g Spread gain control signal generator

Continued on the front page (72) Inventor Hiroshi Asanuma 3-1-1 Asahigaoka, Hino-shi, Tokyo Inside the Toshiba Hino Plant (72) Inventor Hidehiro Takahashi 3-1-1 Asahigaoka, Hino-shi, Tokyo Inside the Toshiba Hino Plant (72) Inventor Hiroshi Ogura 1 Koga Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Research and Development Center Co., Ltd. F-term in Toshiba R & D Center (reference) 5J100 JA01 LA01 LA07 LA08 LA09 LA11 QA01 SA02 5K022 EE01 EE31

Claims (10)

[Claims] 1. A CDMA communication apparatus for use in a mobile communication system having a plurality of frequency bands and transmitting a code-division multiplexed spread spectrum signal using each of the above-mentioned frequency bands. And a radio receiving unit for outputting the received signal; an analog / digital converting unit for converting the received signal output from the wireless receiving unit to a digital signal; and a receiving digital output from the analog / digital converting unit. A digital filter for extracting a signal corresponding to a desired frequency band from the signal, a secondary demodulation unit for despreading the signal extracted by the digital filter and outputting a primary modulation signal, and an output from the secondary demodulation unit A primary demodulation unit for demodulating the primary modulated signal, and an output from the analog / digital conversion unit. And variably controlling the level of the received signal input from the wireless receiver to the analog / digital converter based on the output signal level of the analog / digital converter to maintain the level of the received digital signal within a predetermined range. 1 automatic gain control circuit, and variably controls an input signal level to the secondary demodulation section based on an output signal level of the digital filter so as to maintain an input signal level to the secondary demodulation section within a predetermined range. A CDMA communication device comprising a second automatic gain control circuit. 2. The first automatic gain control circuit according to claim 1, further comprising: a first gain control amount for maintaining an input signal level to said secondary demodulation unit within a predetermined range based on an output signal level of said digital filter. And a second gain for maintaining an input signal level to the secondary demodulation unit within a predetermined range based on a level of the primary modulation signal output from the secondary demodulation unit. A second gain control unit that generates a control amount; a first gain control amount generated by the first gain control unit; and a second gain control amount generated by the second gain control unit. A first level variable circuit for generating a total gain control amount based on the total gain control amount and variably controlling an input signal level to the secondary demodulation unit based on the total gain control amount. The CDMA communication device according to claim 1, wherein: 3. The first automatic gain control circuit includes: a first gain control amount for maintaining an input signal level to the secondary demodulation unit within a predetermined range based on an output signal level of the digital filter. And a first gain control unit that generates a second demodulation unit based on information indicating a spreading code length used in the secondary demodulation unit. A third gain control unit for generating a third gain control amount, a first gain control amount generated by the first gain control unit, and a third gain control generated by the third gain control unit And a second level variable circuit that variably controls an input signal level to the secondary demodulation unit based on the total gain control amount based on the total gain control amount. The CDMA communication device according to claim 1, further comprising: 4. An input signal level to the primary demodulation unit based on a level of a primary modulation signal output from the secondary demodulation unit so as to maintain an input signal level to the primary demodulation unit within a predetermined range. 2. The circuit according to claim 1, further comprising a third automatic gain control circuit for performing variable control.
DMA communication device. 5. A configuration in which a plurality of secondary demodulation sections are provided, and these secondary demodulation sections despread signals output from the digital filters with different spreading codes to output primary modulation signals. The third gain control unit, based on the information indicating the spread code length used in each of the plurality of secondary demodulation units, for each of the secondary demodulation units, its output signal level Generating a third gain control amount for maintaining the first gain control amount in a predetermined range, the second level variable circuit includes a first gain control amount generated by the first gain control unit, and a third gain control amount. A total gain control amount is generated based on the third gain control amount generated for each of the secondary demodulation units by the gain control unit, and the total gain control amount is calculated based on the total gain control amount. Characteristically controls the input signal level to the secondary demodulator CDMA as claimed in claim 3, wherein that
Communication device. 6. A code-division multiplexed spread spectrum signal is received by a radio receiver, and the received signal is converted into a digital signal by an analog / digital converter, and the received digital signal is passed through a digital filter. An automatic gain control circuit used in a CDMA communication device having a configuration in which a signal corresponding to the frequency band of (i) is extracted, and the extracted signal is despread by a secondary demodulation unit and then demodulated by a primary demodulation unit. In order to maintain the level of the received digital signal output from the analog / digital converter within a predetermined range, the reception input from the wireless receiver to the analog / digital converter based on the output signal level of the analog / digital converter. First automatic gain control means for variably controlling the signal level; and input signal level to the secondary demodulation section. Automatic gain control means for variably controlling the level of an input signal to the secondary demodulation section based on the output signal level of the digital filter so as to keep the signal within a predetermined range. Control circuit. 7. The first automatic gain control means for maintaining a level of an input signal to the secondary demodulator within a predetermined range based on an output signal level of the digital filter. And a second gain control means for maintaining an input signal level to the secondary demodulation unit within a predetermined range based on a level of the primary modulation signal output from the secondary demodulation unit. A first gain control amount generated by the first gain control amount generating unit, and a second gain control amount generated by the second gain control amount generating unit. Second
A first level variable which generates a total gain control amount based on the total gain control amount and variably controls an input signal level to the secondary demodulation unit based on the total gain control amount. 7. The automatic gain control circuit according to claim 6, further comprising: 8. A first gain control amount for maintaining an input signal level to the secondary demodulation unit within a predetermined range based on an output signal level of the digital filter. And a first gain control amount generating means for generating, based on information indicating a spread code length used in the secondary demodulation section, for maintaining an output signal level of the secondary demodulation section within a predetermined range. A third gain control amount generating means for generating the third gain control amount, a first gain control amount generated by the first gain control amount generating means, and a third gain control amount generating means. 3rd generated
A second level variable for generating a total gain control amount based on the total gain control amount and variably controlling an input signal level to the secondary demodulation unit based on the total gain control amount. 7. The automatic gain control circuit according to claim 6, further comprising: 9. A level of an input signal to the primary demodulation section based on a level of a primary modulation signal output from the secondary demodulation section so as to maintain an input signal level to the primary demodulation section within a predetermined range. 7. The automatic gain control circuit according to claim 6, further comprising third automatic gain control means for performing variable control. 10. A plurality of secondary demodulation units are provided, and these secondary demodulation units despread signals output from the digital filters with different spreading codes to output primary modulation signals. In the case where the third gain control amount is generated, the third gain control amount generating means outputs the output for each of the secondary demodulation units based on information indicating a spread code length used in each of the plurality of secondary demodulation units. Generating a third gain control amount for maintaining the signal level within a predetermined range, wherein the second level varying means includes a first gain control amount generated by the first gain control amount generation means. And the third gain control amount generating means for each of the secondary demodulators.
Generating a total gain control amount based on the total gain control amount, and variably controlling an input signal level to the secondary demodulation unit based on the total gain control amount. An automatic gain control circuit according to claim 8.