JP2000221246A - Designing system for test point on printed-circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CAD system for designing test-point, by which test-point coordinate data required for the arrangement of a probe pin can be generated automatically when the inspection jig of a multiplayer printed-circuit board is prepared. SOLUTION: This designing system is provided with a test-point processing part 3 in which whether a test point is required or not is judged on the basis of two-dimensional circuit diagram data. The designing system is provided with a net processing part 4 which automatically generates the test point. In addition, the designing system is provided with a test-point arrangement part 5 in which the test point is arranged in coordinates on a printed-circuit board. In addition, the designing system is provided with a test-point coordinate-data output part 7 which outputs test-point coordinate data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system for designing test points of a multilayer printed circuit board using a CAD (Computer Aided Design) system.

[0002]

2. Description of the Related Art A multilayer printed circuit board after component mounting is subjected to quality inspection. For this reason, an inspection jig provided with a large number of probe pins respectively corresponding to the wiring patterns on the printed board is used. The inspection of the printed circuit board is performed by pressing the inspection jig against the printed circuit board and sequentially testing the continuity between the selected pair of probe pins with a tester. In order to bring each probe pin of the inspection jig into contact with a specific wiring pattern on the printed board, a test point pad having a size corresponding to the probe pin is provided in advance on the wiring pattern on the printed board. The inspection jig is manufactured so that the position of each probe pin matches the position of each test point pad on the printed circuit board.

[0003]

Conventionally, a test point on a printed circuit board is set by manually searching for an empty area on the front and back surfaces of a multilayer printed circuit board and adding a test point pad to the empty area. . The inspection jig is manufactured according to the pattern of the test points on the printed circuit board.
The problem with the conventional approach is that it takes time to create the inspection jig. The reason is that an inspection jig having the same pattern as that of the printed board is created, and thus it is not possible to start creating the inspection jig until the manufacture of the printed board is completed.
Another problem with the conventional method is that when a wiring pattern is revised and designed to cope with a logic error on a printed circuit board, the inspection jig must be completely reworked.

An object of the present invention is to provide a test point design system using a CAD system capable of automatically generating test point positions on a multilayer printed circuit board. Another object of the present invention is to automatically generate a test point position related to a changed portion without changing the initially designed test point position when the wiring pattern of the multilayer printed circuit board is designed for revision. It is to provide a test point design system.

[0005]

According to the present invention, there is provided a test point design system, comprising: a test point processing unit for determining whether a test point is required for each net of a wiring pattern on a printed circuit board based on circuit diagram data; A net processing unit for automatically generating test points based on data of the point processing unit, a test point arranging unit for arranging the automatically generated test points at coordinates on a printed circuit board, and outputting the arranged test point coordinate data A test point coordinate data output unit.

According to the test point design system of the present invention, the test point position is automatically generated by the CAD system in consideration of the part shape and the part height, and the test point coordinate data is output. An inspection jig can be created based on this data. Therefore, the inspection jig can be efficiently produced, and the production cost can be reduced.

In a preferred embodiment, the test point design system outputs a net change portion detecting section for detecting a net change portion when a circuit diagram is designed to be revised, and outputs coordinate data of test points of the changed net. A modified test point coordinate data output unit. According to this embodiment, since the data of the changed portion is output, the initially created inspection jig is effectively used, and the initially created inspection jig is modified based on this data, thereby updating the edition. The inspected jig thus manufactured can be easily manufactured. Therefore, it is not necessary to re-create the inspection jig in accordance with the revised design of the circuit diagram, and it is possible to reduce the cost of producing the inspection jig and increase the efficiency.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a test point design system according to the present invention is realized on a personal computer in which a layout CAD is installed, and a two-dimensional print created by a circuit diagram creation CAD. A data storage unit 1 storing board circuit diagram data (data after component placement for adding test points), a CAD component library 2 having external shape information and height information of components mounted on a printed circuit board, A test point processing unit 3 for determining the necessity of a test point, a net processing unit 4 for adding net information of test points automatically generated,
A test point placement unit 5 for placing automatically generated test points, and an automatic routing unit 6 for routing each net
And a test point coordinate data output unit 7 for outputting test point coordinate data used for creating an inspection jig, and a test point change point for outputting test point change point data indicating a part where a test point has been changed or added at the time of revision design. It has a data output unit 8.

The component library 2 includes a component outline information library 21, a component height information library 22, and a component mounting pad information library 23. The test point processing unit 3 includes a test point detection unit 31 and a test point position storage unit 32. The net processing unit 4
A test point net information allocating unit 41 and a net change part extracting unit 42 are provided. Test point placement part 5
A test point pad automatic arrangement unit 51, a test point non-arrangement detection unit 52, an error information output unit 53,
And a test point rearrangement process 54.

The configuration and operation of the test point design system will be described in detail with reference to FIGS.

When the layout CAD system is started, data after component placement is stored in the data storage unit 1 (this is created in advance by a circuit diagram creation two-dimensional CAD).
Is loaded into the test point processing unit 3, and the test point processing unit 3 reconstructs the net list (step A1 in FIG. 2). For example, in a case where two surface mount components are connected to each other as shown in the upper part of FIG. 3 and a net A and a net B having a connection relationship between the surface mount components 1 and 2 exist, By retrieving the net information from the two-dimensional circuit diagram, the net list is reconstructed.

The test point detecting section 31 reads various information of components from the component library 2 and determines whether or not a test point needs to be generated for each net based on the information (step A2 in FIG. 2). . The determination of the necessity of the generation of the test point is performed by checking whether or not one or more through-hole components exist on one net for each net. This is because, when there is a through-hole component, the continuity test is performed by using the through-hole and bringing the probe pin into contact with the conductor of the through-hole, so that it is not particularly necessary to provide a test point pad. Therefore, it is checked whether or not each net has a connection with a through-hole component. If there is a through-hole component in the connection relationship, the connection is classified as a "test pad unnecessary net group" (step A4 in FIG. 2). If there is no hole component, it is classified as "test pad required net group" (step A3 in FIG. 2). In the case of the surface mount component shown in FIG. 3, since each net is connected to each other from the pin pad, it is necessary to generate a test pad, and it is determined whether or not the test pad is necessary (step A2 in FIG. 2).
Then, data is output as a test pad necessary net group.

When a through-hole component exists on one net, it is unnecessary to generate a test point pad. Therefore, a test point pad is not generated in the automatic wiring unit 6 as a "test pad unnecessary net group". The automatic wiring process (Step A11 in FIG. 2) is performed.
If there is no through-hole component on one net, it is necessary to generate a test point pad. Therefore, the test point pad is automatically generated in test point pad generation (step A5 in FIG. 2). The information of each automatically generated test point pad is passed to the test point net information allocating unit 41 of the net processing unit 4, and each piece of net information (the same net name) is allocated to each test point pad (step A6 in FIG. 2). ). In the case of the surface mount component shown in FIG. 3, since a test pad needs to be generated, a test point pad is generated (step A5 in FIG. 2), and a net name corresponding to each net is stored in the test point pad. (Step A in FIG. 2)
6).

When the assignment is completed, the test point pad to which the generated net is assigned is arranged (step A9 in FIG. 2). The test point pad to which the net name is assigned is arranged at an optimum position for wiring design by the test point pad automatic arrangement unit 51, and the information is transferred to the automatic wiring unit 6 to perform automatic wiring processing. That is, the test point pad to which the net information is allocated is passed to the test point placement unit 5, and the test point pad automatic placement unit 51 is easy to wire based on the information of the component library 2 (step A7 in FIG. 2). A test point pad is arranged in a portion where inspection is easy (Step A in FIG. 2)
9). At this time, the layout position is calculated from the component outer size / component height information (Step A7) and the pad layout position parameter (Step A8 in FIG. 2).

The pad arrangement position parameter contains information linked to the height information 22 of each component. For example, a component having a component height of less than 4 mm is a component external size 2
4 mm or more and 10 mm in a place 10 mm or more from 1
Information such as placement of a test point pad in a part less than 15 mm from the component outer size 21 is provided for a part less than the component outer size 21 and in a place 20 mm or more from the component outer size 21 for a component 10 mm or more. By adding this information to the component outer size information 21 (step A7), the test point pad non-placeable region of the # 1 component and the test point pad non-placeable region of the # 2 component (FIG. 3)
See). Further, based on the net connection information, the test point pads are arranged at locations where wiring is easy. The lower part of FIG. 3 shows that test point pads are arranged on each net.

When the test pad arrangement processing (step A9 in FIG. 2) by the test point pad automatic arrangement unit 51 is completed, the test point non-arrangement detection unit 52 checks whether or not all the test point pads are arranged. (Step A10 in FIG. 2).

If there is no unplaced test point pad, the data is passed to the automatic wiring unit 6, and the automatic wiring processing for each net is performed (step A11 in FIG. 2). When an undistributed test point pad is detected, error information is output from the error information output unit 53 (step A12 in FIG. 2), and the test point pad rearrangement processing unit 54 rearranges the test point pads. (Step A13 in FIG. 2). As a method of rearrangement, the already arranged test point pads are moved to secure a space in which the unplaced test point pads can be arranged. The rearranged data is transferred to the automatic routing unit 6, and routing processing for each net is performed (step A in FIG. 2).
11).

FIG. 4 shows a state where the automatic wiring process (A11) is completed. The wiring of the net A is connected by wiring of only the surface layer, and the wiring of the net B is connected by wiring using the front layer and the back layer.

The automatic wiring processing in the automatic wiring section 6 (FIG. 2)
When step A11) is completed, counting of the number of vias (through through holes) for each net generated in the wiring process (step A14 in FIG. 2) and confirmation of the VIA position (step A15 in FIG. 2) are performed. If the number of VIAs is 0 and only the test point pad is used, or if the position of the VIA is below the component, the net name and the coordinate data of the test point pad are passed to the test point coordinate data output unit 7 and the coordinates are output. The data is output (step A17 in FIG. 2). An inspection jig can be created based on the coordinate data.

When the number of VIAs is one or more,
If there is one or more IA positions outside the component, it is checked whether the VIA position matches the pad arrangement position parameter (step A8 in FIG. 2) (step A15 in FIG. 2). If they match, the test point pad is deleted and the net assigned to the test point pad is deleted (step A16 in FIG. 2). In the example shown in FIGS. 3 and 4, since the number of the VIA is 0, the coordinate information of the automatically generated test point pad is output as the inspection jig creation information (step A17 in FIG. 2). This becomes inspection jig creation data. In the net B, the number of VIAs becomes two and the data is passed to the VIA position check (step A15), and it is confirmed whether the position of the VIA generated at the time of automatic wiring is below the component or outside the component. In this case, since the two locations are outside the component, the data is passed to the test pad deletion (step A1 in FIG. 2).
6), as shown in FIG. 5, the automatically generated test point pad of the net B is deleted, and only the penetrating VIA added at the time of automatic wiring is provided.

Then, one VIA outside the part is assigned as a test point pad, and the coordinate data from which the test point pad has been deleted is passed to the test point coordinate data output unit 7 to output the coordinate data ( Step A17 in FIG. 2). An inspection jig is created based on the coordinate data.

Next, a case where one of the components mounted on the multilayer printed circuit board is a through-hole component will be described with reference to FIG. In the example of FIG. 6, nets A and B having a connection relationship between the surface mount component and the through-hole component are shown.
Exists. This net information is stored in the test point processing unit 3
To reconstruct the net list (step A1 in FIG. 2), and determine whether or not a test point pad is required (step A2 in FIG. 2). In the example of FIG. 6, since the respective nets are connected to each other from the through-hole components, the data is passed to the "test pad unnecessary net group" in the determination of the necessity of the test pad (step A2 in FIG. 2) (see FIG. Step A4). Then, the data is transferred to the automatic wiring processing (A11 in FIG. 2), and the automatic wiring processing is performed. If there is a through-hole component on the net, the pin-through hole of the component becomes a test point, and information on the coordinates of this pin-through hole is output to the test point coordinate data output unit 7 (step A17 in FIG. 2). This becomes inspection jig creation data.

Next, the operation and use of the test point design system at the time of designing the revision of the wiring pattern of the printed circuit board will be described. Since the test point pad has already been generated at the time of designing the edition, the test point pad coordinates are stored in the test point position storage unit 32.
Is detected and stored. Then, for a net that requires a new test point, a new test point pad is automatically generated in the test point position storage unit 32.

More specifically, since the test point pads are already arranged at the time of designing the edition, it is necessary to keep the coordinates of the test point pads unchanged for nets whose connection relation is not changed. Therefore, the design data at the time of the revision is transferred to the test point position storage unit 32, and the positions of the test point pads for which the net has not been changed are stored. The stored data is passed to the net change portion detection unit 42, which detects the changed net and deletes its test point pad. For a newly created net or a net changed as shown in FIG. 7, the test point processing unit 3 reconstructs a net list (steps A1 and A in FIG. 2).
2).

The test point detecting unit 31 checks whether a test point is necessary for a newly created net or a changed net. As a confirmation method, check whether there is a connection with a through-hole component in a newly created net or a changed net unit. (Step A4 in FIG. 2), and if there is no through-hole component, it is classified as a “test pad required net group” (Step A3 in FIG. 2).

For a group of nets requiring test pads, test point pads are automatically generated by test pad generation (step A5 in FIG. 2). About the net change part,
The test point pad is peeled off only in the net portion where the connection information is changed by the net change portion extraction unit 42, and the movement prohibition information and the change net name are output so that the arrangement position is not changed in the other unchanged portion. . The outputted movement prohibition information and the changed net name information are passed to the test point net information allocating section 41, where the changed net is allocated, and passed to the test point arranging section 5, where the newly generated test point pad is arranged. I do.

The test point pad automatic arrangement unit 5
If there is a test point pad that cannot be placed in the test point pad 1, it is detected by the test point placement detecting section 52, output to the unplaced error information section 53, passed to the test point pad rearranging section 54, and passed to another test point pad. Eliminate unplaced test point pads while moving.

More specifically, the information of each automatically generated changed test point pad is passed to the test point net information allocating unit 41 of the net processing unit 4, and each net information is allocated to each test point pad (FIG. 2). Step A6). The changed test point pad to which the net information is allocated is passed to the test point placement unit 5,
Based on the information of the component library 2 (step A7 in FIG. 2), the test point pad automatic placement unit 51 (step A9 in FIG. 2) places the test point pads on the portions that are easy to wire and easy to inspect. At this time, the changed test point pads are arranged based on the information stored in the test point position storage unit 32 so as not to move the test point pads. With respect to the test point pad corresponding to the change, the arrangement position is calculated from the pad arrangement position parameter (step A8 in FIG. 2), the component outer size information 21 and the component height information 22 (step A7 in FIG. 2).

There are no unplaced test point pads,
When the arrangement of the test point pads for the change is completed, the data is passed to the automatic wiring unit 6 (step A11 in FIG. 2),
Performs automatic routing of the changed part of the net. The data for which the respective wiring processes have been completed are passed to the test point coordinate data output unit 7 to generate inspection jig creation data. Further, at the time of the edition design, data is passed to the test point change point data output unit 8 to indicate a part where the test point has been changed or added, and test point coordinate information of the changed part is generated.

More specifically, when the wiring processing is completed, the number of VIAs for each changed net generated in the wiring processing is counted (step A14 in FIG. 2) and the VIA position is confirmed (step A15 in FIG. 2). That is, when the number of VIAs is 0 and only the test point pad is used, or when the position of the VIA is at the lower part of the component, the changed net name and the coordinate data of the test point pad are output to the test point changed point data output unit 8. The data is passed, the changed coordinate data is output, and used for creating the inspection jig. Also, VI
If the number of A is one or more and the position of the VIA is one or more outside the component, it is checked whether the VIA position matches the pad arrangement position parameter (step A15 in FIG. 2). ). If they match, the test point pad is deleted and the net assigned to the test point pad is deleted. Then, one part of the VIA outside the part is used as a test point pad,
The coordinate data is assigned and sent to the test point change point data output unit 8, where the coordinate data is output and used for creating an inspection jig.

[0031]

A first effect of the present invention is that an inspection jig can be easily prepared. This is because the test point position on the multilayer printed circuit board is automatically generated by the CAD system and the coordinate data is output. Another advantage of the present invention is that an existing inspection jig can be easily changed when a wiring pattern of a multilayer printed circuit board is designed for revision. The reason is that the test point pad position of the net that has not been changed is not changed, and the information of the test point pad of the changed net is automatically generated and output.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of the system of the present invention.

FIG. 2 is a flowchart showing the operation of the system shown in FIG. 1;

FIG. 3 is a schematic diagram showing the operation of the system shown in FIG. 1;

FIG. 4 is a schematic diagram showing the operation of the system shown in FIG.

FIG. 5 is a schematic diagram showing the operation of the system shown in FIG. 1;

FIG. 6 is a schematic diagram showing the operation of the system shown in FIG. 1;

FIG. 7 is a schematic diagram showing the operation of the system shown in FIG. 1;

[Explanation of symbols]

 2: Component library 3: Test point processing unit 4: Net processing unit 5: Test point placement unit 6: Automatic wiring unit 7: Test point coordinate data output unit 8: Changed test point coordinate data output unit 42: Net change part detection unit

Claims (2)

[Claims] 1. A test point processing unit for determining whether a test point is required for each net of a wiring pattern on a printed circuit board based on circuit diagram data, and a test point is automatically generated based on data of the test point processing unit. A net processing unit to perform, a test point placement unit to place the automatically generated test points at coordinates on the printed circuit board,
A test point coordinate data output unit that outputs the arranged test point coordinate data. 2. The apparatus according to claim 1, further comprising: a net change portion detecting section for detecting a net change portion when the circuit diagram is designed for revision, and a change test point coordinate data output section for outputting coordinate data of test points of the changed net. 2. A test point design system according to claim 1, wherein: