JP4160656B2 - Printed circuit board test method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board (hereinafter abbreviated as PCB) test method, and more particularly to an improved PCB test method suitable for testing a high-density PCB.
[0002]
[Prior art]
As for the technique related to the PCB test method, a method for determining a probe pin of an in-circuit tester is discussed, for example, as described in JP-A-62-206468.
[0003]
[Problems to be solved by the invention]
Although the above-described conventional technology has been discussed with respect to the processing unique to the tester, the technology for facilitating the test in the PCB design process and the test process is not discussed.
[0004]
The above-described prior art relates to an in-circuit tester that performs a test using a dedicated test jig corresponding to the circuit configuration of the PCB, and has a probe point on which a probe pin can be set on a printed pattern on the PCB. Is assumed, and no treatment is considered when there is no probe point.
[0005]
Further, in the conventional test method, a single PCB is tested by an in-circuit tester having a dedicated jig corresponding to the circuit, and a method for dealing with a circuit that cannot be tested is not discussed. .
[0006]
This in-circuit tester is suitable for testing mass-produced products because the same test jig can be used for PCBs in the same circuit. As a matter of course, if the circuits are different, the arrangement of the probe pins is also different, and a dedicated test jig having probe pins implanted corresponding to the circuits is required.
[0007]
However, in recent PCBs with high density, there are many cases where probe points cannot be provided on a printed pattern, and dealing with these points has become a challenge for testing high-density PCBs. That is, as the circuit density increases, there are parts that can no longer be handled by an in-circuit tester using a test jig, and it becomes impossible to test the entire PCB.
[0008]
On the other hand, a flying probe tester is known as a tester that uses this type of probe pin and does not use a dedicated test jig. In this case, since the test probe can be set at an arbitrary position, it is possible to test a circuit area that cannot be tested with a dedicated test jig. However, this flying probe tester has the advantage of being able to test the circuit freely to some extent, but has the disadvantage that the time required for the test is longer than that of the in-circuit tester.
[0009]
Accordingly, an object of the present invention is to eliminate the above-mentioned problems of the prior art, and the maximum test effect can be obtained in the shortest time by sharing the high-density PCB test with the in-circuit tester and the flying probe tester. It is to provide an improved PCB testing method.
[0010]
[Means for Solving the Problems]
  In order to achieve the above object, the PCB test method of the present invention incorporates a device for testing in accordance with the work contents in each process from the stage of circuit design and mounting design process, and tests the circuit on the high-density PCB. The above circuit is separated into a circuit that can be tested using a tool and a circuit that cannot be tested with an in-circuit tester using a test jig, and the latter circuit is tested with a flying probe tester that does not use a test jig. A test program for each tester is created to optimize the PCB test.
  More specifically, in the printed circuit board test method of the present invention, a predetermined test pattern is provided on the printed circuit board mounting component and the printed circuit board from a probe pin standing on the printed circuit board composed of the electronic circuit component and the printed wiring board. An in-circuit tester and a test jig that use a test jig to monitor the output signal from a printed pattern or electronic component that is supplied to at least one of the circuit board mounted component pins and connects the printed circuit board mounted component pins. A method for testing a printed circuit board by a processing apparatus having an unnecessary flying probe tester and CPU, internal memory, external memory, and input / output means,
In accordance with the circuit configuration of the printed circuit board stored in the external memory or the internal memory connected to the processing device, the connection relationship between the circuit symbol of the circuit diagram information stored in the external memory or the internal memory and the mounting component pin number is represented. From the net table and the print pattern table representing the connection relationship between the mounted component and the component pin number, the test is made to correspond to the print pattern of the net number registered in the print pattern table corresponding to the first net number on the net table. Search for points that can be contacted with the probe pin of the in-circuit tester using a jig in order from the top of the print pattern table, and if there are such points, register the net number, point type, and XY coordinate information in the probe candidate point table. In-circuit tester contact point Means for determining,
Means for determining the test point of the flying probe tester by registering the net number in the undetected net table when the contact point of the in-circuit tester is not found from the print pattern table;
The means for determining the contact point of the in-circuit tester and the means for determining the test point of the flying probe tester are sequentially repeated for all the nets stored in the net table, and the in-circuit tester The in-circuit tester method is used for the contact points of the above, and the flying probe method is separately used for the test points of the flying probe tester.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the invention will be described with reference to the drawings.
FIG. 1A is a flowchart showing an outline of a test method of the present invention, and FIG. 2 is a block diagram showing an arrangement relationship between an electronic computer and tester equipment when carrying out the present invention.
[0012]
1A of the present invention shown in FIG. 1A, circuit input 101 considering the test, pattern design 102, probe point selection 103, in-circuit test TP (abbreviation of test program) 104, test jig information creation 105, The TP (abbreviation of test program) generation 106 for the flying probe tester 106 and the TP transfer 107 to the tester are software that operates on the CPU 200 as shown in FIG. 2, are stored on the hard disk 202, and are VDT (video In response to an instruction from the terminal 203, necessary software is loaded into the memory 201 and operates on the CPU 200. The TP created on this computer system is transferred to the in-circuit tester 204 and the flying probe tester 205 via the communication line 210.
[0013]
FIG. 1A shows an outline of a process until a circuit designer inputs a circuit and completes the test. A process 101 is a PCB circuit input process. At this time, the circuit input considering the test is shown in FIG. The DVT 203 is used.
[0014]
The circuit input in consideration of the test means that when an oscillation circuit is included in the circuit, as shown in FIG. 7A, in the oscillation circuit 700, when the oscillation circuit 700 inputs a high level signal, the oscillation output signal When the enable pin 701 for suppressing the above is provided, the pull-down resistor 701B is automatically generated so that this can be controlled.
[0015]
Further, as shown in FIG. 7B, when the oscillation circuit 700A does not have an enable pin, a dividing circuit 705 and a pull-up resistor 704B are automatically provided between the oscillation circuit output signal 702 and the logic circuit. Generate. The dividing circuit 705 uses a 2-input NAND element, and one of the input signals is connected to the output signal pin 702 of the oscillation circuit 700A, and the other is connected to the power supply via the pull-up resistor 704B. In order to realize this, a test control component table 810 shown in FIG. 8B is used. In the test control component table 810, component names, component types of components that affect in-circuit tests such as oscillation circuits and LSIs, enable pin numbers, and enable signals are registered. It is determined from the test control component table 810 whether the component is a component that needs to be automatically generated based on the component name in the circuit.
[0016]
Similarly, if an LSI is present in the circuit, it is necessary to control the output signal of the LSI to high impedance in the in-circuit test. Therefore, if an LSI is detected in the circuit, the LSI can be controlled by the enable pin. A control circuit is automatically generated as shown in FIG. In FIG. 8A, the LSI 3 is a corresponding component, the pin number 204 is a control pin, and the enable signal is H: high level. Therefore, a pull-up resistor 801 is automatically generated for this pin.
[0017]
When a BS circuit (abbreviation of Boundary Scan circuit) exists in the circuit and BS connection is not performed, the BS circuit connection is automatically performed. This will be described with reference to the drawings. In the circuit diagram of FIG. 9A, LSI1 and LSI4 are LSIs that employ a BS circuit, and component A is a component that does not employ a BS circuit. This connection (circuit diagram information) is described in the circuit file 151 of FIG. 1A.
[0018]
This is illustrated in FIG. 9C. In processing 9301, the component name is read from the processing circuit file 151 for each circuit symbol representing the component mounting unit, and it is determined whether or not it is a BS component in the test control component table 810 of FIG. 8B, and only the BS component is extracted. It is set in the BS part table 9110 of FIG. 9B (c).
[0019]
Next, in process 9302, control pin information of the BS component is extracted for each circuit symbol registered in the BS component table 9110.
[0020]
In process 9303, TDO (tester data output) and TDI (tester data input) are connected on the circuit diagram in the order of the circuit symbols registered in the BS part table 9110 of FIG. 9B (c). In this embodiment, signal names are generated as TD1 and TD2 in order, and are connected in the order of circuit symbols L10, L20, and L40 as shown in FIG. 9B (a).
[0021]
After processing 9303 is completed, connection of TMS (test mode select) is performed in processing 9304. This extracts the circuit symbol and the TMS pin number (135 for LSI1 / 23 for LSI4) from the BS component table 9110 of FIG. 9B (c), and all TMS pins on this table as shown in FIG. 9B (a). Are connected with the same signal name TMS0. A pull-down resistor is connected to this TMS.
[0022]
In process 9305, connection of TCK (test clock) is performed. For connection of TCK, the TCK pin number (15 for LSI1 / 70 for LSI4) on the BS component table 9110 is extracted for each circuit symbol, and all are given the same signal name (TCK0 in this example). As a result, the BS scan connection shown in FIG. 9B (a) is completed.
[0023]
Another embodiment is shown in FIG. 9D. In this method, when a correct BS scan connection is not made, an error message is output and correction is instructed. First, in process 9401, all BS parts are extracted from the circuit file 151 in FIG. 1A and registered in the BS part table 9110 in FIG. 9B (c).
[0024]
The control pin information of the BS component is extracted for each circuit symbol registered in the BS component table 9110 in processing 9402, and the TDI and TDO between the BS components registered in the BS component table 9110 are connected in processing 9403. Check that. If TDI and TDO are not connected, the process proceeds to processing 9404 and an error message is output to the connection error location on the circuit diagram.
[0025]
Next, the processing proceeds to processing 9405 to output an inquiry message as to whether or not to perform default connection processing. If there is a default instruction, the signal name is corrected in processing 9405A so that the same pin types are connected. The default is a standard test.
[0026]
Next, the process proceeds to process 9406. In process 9406, it is checked whether the TCK and TMS signals are connected to the same type of pins. If different pin types are connected to each other, the process proceeds to processing 9407 and an error message is output to the connection error location on the circuit diagram.
[0027]
Next, in step 9408, an inquiry message is output as to whether or not to perform default connection processing. If there is a default instruction, the same signal name is assigned to pins with different signal names so that the same pin type is connected. To do. This makes it possible to pick out an incorrect connection and automatically correct it to the correct connection. By performing these processes, it is possible to perform circuit input considering the test of the process 101 shown in FIG. 1A.
[0028]
After the circuit input considering the test of the process 101 in FIG. 1A is completed, the circuit pattern is designed in the process 102. In this process, normal pattern design is performed and a pattern design file 152 is created. A method of reading the pattern design file 152 and determining the probe pin position is shown in FIG.
[0029]
In the process 311, first, the logical design information is extracted from the pattern design file 152 shown in FIG. 1A, the net table 151A shown in FIG. 1B (a) is created, and the print pattern information is similarly extracted from the pattern design file 152. The print pattern table 152B shown in FIG. 1B (d) is created.
[0030]
Next, in step 312, the first pin of the net table 151A is focused. At this time, the process 313 checks whether there is information in the net table 151A. If there is no information, the process proceeds to process 318 and all the probe pin candidate points registered in the probe candidate point table 152A shown in FIG. A proximity check is performed to determine whether the distance between all component pins and vias on the target PCB satisfies the constraint value, and only the probe candidate points satisfying the limit distance are registered in the probe candidate point table 152A, and the end process 319 is performed. Do.
[0031]
If information exists in the net table 151A shown in FIG. 1B (a), the process proceeds to process 314, and the probe position of the target net is traced using the print pattern table 152B shown in FIG. 1B (d). The trace process is a process of checking pattern data on the print pattern table 152B having the same number as the target net in order from the top.
[0032]
Whether or not a probe point has been found in process 315 is checked. If not found, the process proceeds to process 316B, a net number is registered in the undetected net table 151B shown in FIG. 1B (c), and the process proceeds to process 317. If it is found that it was found in the process 315, the process proceeds to the process 316A, and this probe position is set in the probe candidate point table 152A.
[0033]
Next, the processing proceeds to processing 317, paying attention to the next net, and returns to processing 313. As a result, the probe pin position candidate point for each net is registered in the probe candidate point table 152A shown in FIG. 1B (b), and the probe pin can be set up in the undetected net table 151B shown in FIG. 1B (c). The net number that did not exist is registered.
[0034]
In the process 103 (probe point determination) displayed in FIG. 1A, the net table 151A, the undetected net table 151B, the probe candidate point table 152A, the component mounting position table 151C, and the test control component table 810 created in the process 102 (pattern design). The probe pin position determination considering the BS for the circuit to be tested, the probe point creation of the part of the circuit that can be tested by the in-circuit tester, and the probe point information for the flying probe test of the part that cannot be tested by the in-circuit tester are created. Thereby, information for testing the test target PCB can be output.
[0035]
A probe pin position determination method considering the BS circuit in the process 103 will be described with reference to the flowchart of FIG. In the process 651, paying attention to the first net of the net table 151A displayed in FIG. 1B (a), it is checked whether or not there is data in the net focused in the process 652. The process ends.
[0036]
If there is data, the process proceeds to process 653 to extract all the parts connected on the target net, and it is checked in process 654 whether all the parts are BS parts. As a result, if all of the parts are BS parts, the process proceeds to step 655, and it is checked whether or not there is an instruction to suppress pinning when all of the parts are BS parts with parameters designated by the user from the outside. If there is an inhibition instruction, the process proceeds to process 656, and it is checked whether or not there is a currently focused net number in the probe candidate point table 152A displayed in FIG. 1B (b). If there is the same net number, a deletion mark is assigned to the probe candidate point of the net number, and the process proceeds to process 657. If there is no inhibition instruction in the determination of the process 655, the process proceeds to the process 657 without performing the process 656.
[0037]
If it is determined in process 654 that parts other than the BS part are included in the net, the process proceeds to process 658 to check whether all parts are parts other than the BS part. If all parts are not BS parts, process 657 is performed. Proceed to When the BS component is included in the process 658, the process proceeds to the process 659, and it is checked in the BS component table 9110 displayed in FIG. 9B (c) whether or not the signal output source is the BS component.
[0038]
As a result, when the signal output source is the BS part, the process proceeds to process 660 and it is checked whether there is an instruction to suppress pinning other than the BS part. If there is an inhibition instruction, the process proceeds to process 656 and a deletion mark is assigned to the probe pin of the target net. If it is not the signal output source in the process 659, the process proceeds to the process 657. In process 657, attention is paid to the next net in the net table 151A displayed in FIG. 1B (a), and the process returns to process 652. This process is repeated, and when all the nets have been processed, the probe pins that have become unnecessary can be deleted from the probe point candidate points by performing a boundary scan.
[0039]
FIG. 5A shows an example in which the probe pin is suppressed as a result of performing these processes. In the figure, the probe pins of the in-circuit tester are symbols 621, 622, 623, 631, and 632, and the probe pins that suppress pinning are symbols 633 and 634, respectively. Moreover, FIG. 5B shows an example of pin standing when no pin standing restraining instruction is given.
[0040]
Next, a method for determining a probe point for a flying probe test will be described with reference to FIG. In the process 400, the net table 151A displayed in FIG. 1B1 (a) is sorted by the circuit symbol and the pin number which are the component mounting position symbols, and the process proceeds to the process 401 and attention is paid to the component of the first circuit symbol.
[0041]
  Next, the process proceeds to process 401, where it is checked whether or not all the mounted parts have been processed. Process if all processing is complete406The process for determining the probe point for the flying probe test is terminated.
[0042]
If the component of the target circuit symbol is an unprocessed component, the process proceeds to step 403, and all the component pins of the target circuit symbol are stored in the undetected net table 151B displayed in FIG. 1B1 (c). Check if there is a connected net number, and if there is a net number, it is a component pin without a probe pin, so the component pin is checked to see if it is in contact with the adjacent component pins on both sides, so pay attention The net number of the component pin adjacent to the component pin is registered in the flying probe test table 430 shown in FIG. 4C. At this time, if the distance between the component pins is equal to or greater than the proximity distance given by the user. Not to be tested and not registered in the flying probe test table 430.
[0043]
Also, even when the same combination of net numbers has already been registered in the flying probe test table 430, it is not registered. When this processing is completed for all the component pins of the component of the circuit symbol of interest, the processing proceeds to processing 405 and returns to processing 402 while focusing on the component of the next circuit symbol.
[0044]
Next, a proximity check between the net registered in the undetected net table 151B displayed in FIG. 1B1 (c) and another net is performed based on the distance between the print patterns. The distance is a value designated by the user from the outside. The nets determined to be close here are registered in the flying probe test table 430. At this time, if the net number of the same combination is already registered in the flying probe test table 430, it is not registered.
[0045]
Next, a method for checking whether or not the net registered in the flying probe test table 430 shown in FIG. 4C cannot be tested by the flying probe tester will be described with reference to FIG.
[0046]
When there is a part 1010 having a height h around the part 1000 to be tested and a probe pin 1021 of a flying probe tester having an inclination angle θ is used, the distance d between the part 1010 and the part to be tested pin, the height h of the part, Further, a probe pin prohibited area where the probe pin 1021 cannot be contacted is determined by the width w of the component 1010. The forbidden area is an area that satisfies the calculation formula h + (w / 2) × cot θ <d × tan θ.
[0047]
The test points registered in the flying probe table 430 displayed in FIG. 4 (c) are checked whether or not this condition is satisfied, and the points in the prohibited area include the corresponding data on the flying probe table 430. Add a delete mark.
[0048]
Next, the process proceeds to process 104 (TP generation for in-circuit tester) in FIG. 1A, and the test program TP1 for the in-circuit tester is stored in the net table 151A displayed in FIG. 1B (a) and the probe candidates displayed in FIG. 1B (b). In accordance with the point table 152A, it is output to a file, and in step 105, test jig information is output from the probe candidate point table 152A to a file. The test jig inputs this file, and is processed and manufactured by an NC processing machine.
[0049]
Next, in processing 106 (TP generation for flying probe tester), a flying probe tester test program TP2 is created and output according to the flying probe table 430 shown in FIG. 4C.
[0050]
In the process 107, the in-circuit test program TP1 created in the file 155 and the flying probe tester test program TP2 created in the file 156 are transferred to each tester connected to the network. The file 160 stores the in-circuit tester TP, and the file 162 stores the flying probe tester TP. At this time, the test combination of the test target PCB is entered in the test process instruction sheet 161 displayed in FIG. 1B (e), and sent to the test site via the network.
[0051]
The process 108 and subsequent steps are the work of the test workplace. In the process 108, the contents of the process instruction 161 are checked. If there is an in-circuit test instruction, the in-circuit test is performed in the process 109 and the process proceeds to the process 110. Is checked whether there is a flying probe tester instruction, and if there is an instruction, the process proceeds to step 111 to perform a flying probe test.
[0052]
  In-circuit testing and processing of processing 109111Locations that are not detected in the flying probe test are output to the undetected file 158 and confirmed in the final confirmation step 112.
[0053]
FIG. 11 shows an embodiment in which the resist in the via hole portion is deleted when contacting the via hole of the PCB to be tested as a probe point for the in-circuit test. When the via hole 1103 is selected as a probe point at the time of performing the in-circuit test, the via hole 1103 is instructed to remove the resist 1101, and the probe of the in-circuit tester is applied to the via hole 1103 where the resist 1101 is not present. Electrical contact is obtained by bringing the pins 1102 into contact, and a test pattern can be injected or observed.
[0054]
FIG. 12 shows an example in which the probe point mark 1201 is given by silk printing to the via hole 1103 in contact with the probe pin 1102 on the PCB. When a design change occurs in the PCB to be tested, the jumper and cut information generated by the design change is recorded in the jumper cut file 159, the jumper and cut information is taken from here, the probe point of the flying probe tester is taken out, and the flying Design change information can be confirmed by a probe tester.
[0055]
FIG. 13 shows an example of the jumper cut information file 159.
When the flying probe tester moves the probe pin, the height of the component mounted on the PCB to be tested becomes an obstacle, and the probe pin may not be moved. This countermeasure is shown in FIG. The parts mounted on the PCB to be tested, which are higher than the height limit of the probe pin of the flying probe tester, are positioned on a grid in which the PCB to be tested shown in FIG. The failure mark R is put in and expressed. Accordingly, when the flying probe pin moves from the point S1401 to the point E, the probe pin can be moved while avoiding the obstacle by determining the moving position while avoiding the prohibition mark R on the lattice.
[0056]
【The invention's effect】
As described in detail above, the intended object can be achieved by the present invention. That is, according to the present invention, means for facilitating the test can be taken in each PCB design process, so that the test debugging of the PCB can be facilitated and the test debugging time can be shortened. In addition, a test program for testing by combining a plurality of testers having different functions according to the mounting conditions of the test target PCB can be created at the same time, and test jig creation information can be created at the same time, thereby improving the test detection rate. .
[Brief description of the drawings]
FIG. 1A is a flowchart showing an embodiment of the present invention.
FIG. 1B is a table showing an embodiment of the present invention.
FIG. 2 is a block diagram of a PCB test hardware system showing an embodiment of the present invention.
FIG. 3 is a flowchart showing an embodiment of a test probe pinning rule.
FIG. 4 is a flowchart showing an embodiment of a pinning method for a flying probe tester, a schematic PCB mounting diagram, and a structure example of a probe pin table for a flying tester.
FIG. 5A is an embodiment in the case of suppressing boundary scan pin standing.
FIG. 5B shows an embodiment in the case of a boundary scan pin stand.
FIG. 6 is a flowchart of an embodiment showing a probe pinning method in consideration of a boundary scan.
FIG. 7 shows an implementation example of an oscillation circuit for ease of testing.
FIG. 8 shows an embodiment of an LSI operation control facilitating circuit for facilitating a test.
FIG. 9A is an example of a circuit before boundary scan connection;
FIG. 9B shows an embodiment after automatic generation of boundary scan connection.
FIG. 9C is a flowchart showing an embodiment in which boundary scan connection is automatically performed at the time of circuit input.
FIG. 9D is a flowchart showing an embodiment for correcting an error in boundary scan connection at the time of circuit input.
FIG. 10 shows an embodiment for obtaining a prohibited area of probe points in a flying probe tester.
FIG. 11 shows an embodiment in which the probe point resist in the in-circuit tester is removed.
FIG. 12 shows an embodiment in which a probe point mark is printed when a via is selected as a probe point by an in-circuit tester.
FIG. 13 shows an example of a jumper cut file.
FIG. 14 shows an example of a forbidden region of a high-height part that hinders probe pin movement in a flying probe tester.
[Explanation of symbols]
200 ... CPU,
201 ... memory,
202 ... a hard disk,
203 ... a hard disk,
204: In-circuit tester,
205 ... Flying probe tester,
210: Communication line.

Claims (11)

A predetermined test pattern is supplied to at least one of the printed circuit board mounting component pin and the printed circuit board mounting component pin from a probe pin standing on the printed circuit board configured by the electronic circuit component and the printed wiring board, and mounted on the printed circuit board. An in-circuit tester that observes output signals from printed patterns or electronic components that connect between component pins using a test jig and a flying probe tester that does not require a test jig, CPU, internal memory, external memory, input / output means A method for testing a printed circuit board by a processing apparatus having:
In accordance with the circuit configuration of the printed circuit board stored in the external memory or the internal memory connected to the processing device, the connection relationship between the circuit symbol of the circuit diagram information stored in the external memory or the internal memory and the mounting component pin number is represented. From the net table and the print pattern table representing the connection relationship between the mounted component and the component pin number, the test is made to correspond to the print pattern of the net number registered in the print pattern table corresponding to the first net number on the net table. Search for points that can be contacted with the probe pin of the in-circuit tester using a jig in order from the top of the print pattern table, and if there are such points, register the net number, point type, and XY coordinate information in the probe candidate point table. In-circuit tester contact point Means for determining,
Means for determining the test point of the flying probe tester by registering the net number in the undetected net table when the contact point of the in-circuit tester is not found from the print pattern table;
The means for determining the contact point of the in-circuit tester and the means for determining the test point of the flying probe tester are sequentially repeated for all the nets stored in the net table, and the in-circuit tester A test method for a printed circuit board, in which an in-circuit tester method is used for the contact point of the test and a flying probe method is used for the test point of the flying probe tester . A circuit composed of components that can test the mounted components on the printed circuit board by using a test jig from the circuit of the printed circuit board developed in the internal memory and the external memory of the processing apparatus, and other components. classified into the configured circuit generates an in-circuit test pattern for the circuit composed of components that can be tested in the test fixture, unnecessary test fixture for the circuit composed of parts that can not be tested 2. The printed circuit according to claim 1 , wherein a test pattern for a flying probe tester is generated, and each test pattern is supplied to a corresponding tester to test the entire printed circuit board. Board testing method. And the circuit composed of components that can be tested by using the test fixture, when classifying into a configured circuit in the other parts, between component pins and the component pins on the printed circuit board connected at the same potential If no portion where the probe pins for testing by the test fixture on a printed pattern that are to contact, claims, characterized in that to select the components and the pattern to be connected to the pattern as a circuit which can not be tested in-circuit testers 3. A method for testing a printed circuit board according to 2 . 2. The printed circuit according to claim 1, wherein for a circuit that cannot be tested by the in-circuit test, a test pattern is created in which a probe pin of a flying probe tester is brought into contact with a start point and an end point of the print pattern included in the circuit. Board testing method. For circuits that cannot be tested by the in-circuit test, make sure that there is no contact between the component pins that cannot be used for the probe pin setting by the test jig of the components included in the circuit and the pins of other nets of the component adjacent to the component pins. 2. The printed circuit board test method according to claim 1, wherein a test pattern is created in which a probe pin of a flying probe tester is brought into contact with a pin of another net of the component adjacent to the component pin . From the external memory of the processing apparatus, the circuit information of the printed circuit board developed on the internal memory, and select all the electrically independent printed patterns and via holes on the printed circuit board that are close to each other. 2. The method for testing a printed circuit board according to claim 1 , wherein a test pattern for a flying probe tester is created. When the via hole on the printed circuit board developed on the external memory or the internal memory of the processing apparatus is determined on the processing apparatus as the probe pin position of the in-circuit tester, a resist is applied to the via hole. 2. The method for testing a printed circuit board according to claim 1 , further comprising the step of issuing a non-instruction. When the via hole on the printed pattern of the printed circuit board developed on the external memory and the internal memory of the processing device is determined on the processing device as the probe pin position of the in-circuit tester, a probe pin mark is placed on the via hole. The method for testing a printed circuit board according to claim 1 , further comprising the step of: According to the external memory of the processing apparatus, the design information of the printed circuit board developed on the internal memory and the change information of the printed circuit board, or the change information of the printed circuit board input from the outside of the processing apparatus using an input unit, 2. The method for testing a printed circuit board according to claim 1 , further comprising a step of generating an in-circuit test pattern for outputting a difference only for the changed portion and replacing the test pattern created before the change with the corresponding portion. According to the design information of the external circuit of the processing device, the printed circuit board developed on the internal memory, when generating the test pattern of the flying probe tester, the height of the parts on the printed circuit board is taken into consideration 2. The method for testing a printed circuit board according to claim 1 , further comprising the step of generating control information that moves while avoiding a position where the component height becomes an obstacle when the probe moves. When the test pattern of the flying probe tester is generated according to the design information of the external circuit of the processing apparatus and the printed circuit board developed on the internal memory, the part adjacent to the test target part on the printed circuit board is the test target. 2. The method for testing a printed circuit board according to claim 1 , further comprising a step of removing a component pin from a test pattern of a flying probe tester as a test object when it becomes an obstacle when contacting the component pin.

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