JPH0636008B2 - Printed circuit board test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a method of testing a pattern for each net on a printed circuit board, when testing a printed circuit board having a non-uniform grid,
In order to solve the problem of wasteful labor and a lot of time, test data for each net is selected from among all net pattern data of the printed circuit board, for example,
The proximity pattern data that may cause a short circuit is extracted, and only the extracted net is tested by, for example, a two-point test method.

[Industrial application field]

 The present invention relates to a printed circuit board test method.

Generally, the test of the printed circuit board is to check whether or not the pattern printed and wired on the printed circuit board is properly wired and whether or not there is a short circuit between the patterns.

However, with the recent diversification of electronic components, the dimensional standards of terminals have also diversified, and components with various sizes are often mounted, and the grid grid tends to be uneven. It is in.

In addition, with the recent trend toward large-scale computer systems and high-density packaging, holes other than uniform grid grids are being generated.

Therefore, if the test of the printed circuit board of the non-uniform grid grid is manually performed, it takes a lot of time and labor,
A printed circuit board test method that can be performed in a short time is required.

In addition, it is possible to create a printed circuit board tester that can hit two grid terminals even if they are uneven.
In order to perform the above-mentioned short circuit check completely with the tester, it is necessary to combine all the nets, which requires a huge amount of time. Therefore, for a printed circuit board having a non-uniform grid grid, A test method capable of effectively performing a short circuit test has come to be awaited.

[Problems to be solved by conventional technology and invention]

FIG. 4 is a diagram for explaining a conventional printed circuit board test method, (a) shows a case of a printed circuit board having a uniform grid grid, and (b) shows a case of a printed circuit board having a non-uniform grid grid. ing.

First, as shown in Figure (a), if the grid grid has a uniform grid such as a 100 mil square grid, for example, with a uniform probing terminal such as'Kenzan ', all grids Lattice (e.g.
) Was being probed and tested at the same time.

However, a printed circuit board having a non-uniform grid as shown in Fig. (B) cannot be tested with a uniform probing terminal, so that it was manually tested, for example.

Therefore, in the case of (a), it is necessary to create a “fixture” (uniform test terminal board) that can be probed at the same time for each size of the printed circuit board, which is very costly and time consuming. was there.

For this reason, for example, a tester that probing every two points is known, but in order to inspect the above-mentioned net short-circuit (short circuit), all the net combinations as shown in FIG. There was a problem that it needed to be tested and was very time consuming.

In view of the above-mentioned conventional drawbacks, the present invention has an object to provide an efficient test method in a printed circuit board test method that can shorten the test time.

[Means for solving problems]

FIG. 1 is a flow chart of processing showing the configuration of the printed circuit board testing method of the present invention.

In the present invention, a method for testing a pattern for each net on a printed circuit board, in which net pattern data adjacent to the test data for each net is extracted from all net pattern data for the printed circuit board Means 32, 33 are provided, and only the net pattern extracted by the means 32, 33 is tested.

[Action]

That is, according to the present invention, in a method of testing a pattern for each net on a printed circuit board, in order to solve the problem that it takes a lot of time and labor when testing a printed circuit board having a non-uniform grid. , Out of all the net pattern data on the printed circuit board, for example, proximity pattern data that may cause a short circuit is extracted from the test data for each net, and only the extracted nets, for example, 2 Since the point test method is used, there is no need to test with'vias', 'patterns', etc. that are far from the test data, and the time required to check the printed circuit board is shortened. This has the effect of eliminating the need to create a'fixture 'for checking each printed circuit board.

〔Example〕

 Embodiments of the present invention will be described in detail below with reference to the drawings.

The aforementioned FIG. 1 is a flow chart showing the configuration of the printed circuit board test method of the present invention, FIG. 2 is a diagram showing a configuration example of the printed circuit board test system, and FIG. 3 is the printed circuit board test method of the present invention. Is a diagram showing a concrete example of the above, and steps 32 and 33 in FIG. 1 are means necessary for carrying out the present invention. The same reference numerals indicate the same objects throughout the drawings.

The printed circuit board testing method of the present invention will be described below with reference to FIGS.

First, in FIG. 2, the central processing unit (CPU) 1 executes the “printed circuit board test system” 21 loaded on the main memory device (MS) 2 to obtain a file memory.
From the database (DB) built in (FM) 3, the wiring pattern data of the printed circuit board to be tested is stored in the main memory (M
S) The data is expanded as a printed circuit board data in a specific area (printed circuit board data area) 22 on 2 and the data to be tested is extracted into the check data area 23 by steps 32 and 33 in FIG. Based on the above, the two-point tester 4 is activated to test the printed circuit board of the present invention.

The check data extracting method of the present invention will be described below with reference to FIG.

Step 30: From the printed circuit board database (DB) described above, patterns and vias (holes) that make up one net.
Collect data.

Here, the'net 'refers to a group of patterns and hole data that are always connected to each other and have the same potential.

Step 31: Create check data for checking the net connection collected in step 30.

Step 32: Collect the pattern of the above net, or the pattern of another net adjacent to the hole, and hole data.

Normally, the pattern and hole data are stored in the main memory (MS).
In the printed circuit board data area 22 (see FIG. 2) on 2,
Since, for example, end point coordinate data and a line width data group are stored in an ordered area for each net,
By selecting the net data stored in the area close to the data of a certain net and calculating the mutual distance with respect to the selected data, the close net can be extracted.

Step 33: For the net extracted in Step 32, check data for checking adjacent shorts is created and stored in the check data area 23 of FIG.

Step 34: It is checked whether or not the above steps 32 and 33 have been performed for all the patterns and holes forming the net, and if there are remaining patterns or holes, the process returns to step 32. , If all are completed, move to next step 35.

Step 35: Check whether all the nets existing on the printed circuit board have been processed, and when not finished,
Return to step 30, but if completed, proceed to the next step.

Step 36: With respect to the check data stored in the above-mentioned check data area 23, one of the duplicate check data is deleted to create lean check data.

The printed circuit board test of the present invention is performed on the check data generated in steps 30 to 36 by the above-described two-point tester 4.

A specific example of the check data extracted in steps 32 and 33 will be described with reference to FIG.

In the figure, for one net connecting holes ,, the adjacent nets belonging to the hole are extracted in the above steps 32 and 33, and the nets belonging to the hole are not extracted.

When testing this check data with a two-point testing machine 4, first, to test that the net connecting the holes ,, is normally connected ,,,, and
Check the space by probing.

Next, a probing terminal (for example,-,-) near a point at which there is a risk of short-circuiting is selected from the nets selected for checking the short-circuiting, and the short-circuiting is checked.

Conventionally, as shown in Fig. 4 (b), short checks were performed on all nets, so the number of checks was enormous.

As described above, the present invention extracts only the nets that are close to the net to be tested from the design data of the printed circuit board to generate the check data for the two-point test,
For example, it is characterized in that it is tested by the above-mentioned two-point tester.

〔The invention's effect〕

As described in detail above, the printed circuit board check method of the present invention is a method of testing a pattern for each net on the printed circuit board, and when testing a printed circuit board having a non-uniform grid, a wasteful labor and a lot of time are required. In order to solve the problem of requiring, for all the test pattern data of the printed circuit board, for each test data of each net, for example, the proximity pattern data that may cause a short circuit is extracted, Since only the extracted nets are tested by, for example, the 2-point test method, it is not necessary to test with'vias', 'patterns', etc. that are far away from the test data, and the printed circuit board can be checked. This has the effect of shortening the time required for doing so and eliminating the need to create a "fixture" for checking each printed circuit board.

[Brief description of drawings]

FIG. 1 is a flow chart of processing showing a configuration of a printed circuit board test method of the present invention, FIG. 2 is a diagram showing a configuration example of a printed circuit board test system, and FIG. 3 is a specific example of the printed circuit board test method of the present invention. Fig. 4 and Fig. 4 are diagrams for explaining the conventional printed circuit board test method. In the drawing, 1 is a central processing unit (CPU), 2 is a main memory (MS), 21 is a printed circuit board test system, 22 is a printed circuit board data area, 23 is a check data area, 3 is a file memory (FM), 4 Indicates a 2-point tester, 30 to 36 indicate processing steps, and indicates a hall.

Claims (1)

[Claims] 1. A method for testing a pattern for each net on a printed circuit board, wherein adjacent net pattern data is extracted from all the net pattern data on the printed circuit board for the test data for each net. A printed circuit board test method, characterized in that the means (32, 33) for performing is provided, and only the net pattern extracted by the means (32, 33) is tested.