JPS63201575A - Method for testing circuit mounted on printed circuit board - Google Patents

Abstract

PURPOSE:To test a circuit which a probe pin can not be stood without providing a land for testing and a test point by dividing and extracting the circuit where the probe pin can not be stood and supplying a test pattern to the whole circuit. CONSTITUTION:A CPU 1 read and stores package design information on all components mounted on a printed circuit board and logic design information on a printed board in a memory 4. Then the CPU 1 reads information on one net and judges and registers whether or not a pin can be stood on the read net in the table in the memory 4. Then all pieces of net information are read and then an advance to a step 108 is made; when there is a net where a probe pin can not be stood, logic design information on one net in a pin stand disable net table to form division circuits. This process is repeated to generate a test pattern for all probe pin standing disable sequence on the printed circuit board.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an in-circuit tester for testing the operation of a printed circuit board, and in particular, it relates to an in-circuit tester for testing the operation of a printed circuit board, and in particular, for testing probe pins when electronic components are directly connected to each other on the printed circuit board. The present invention relates to a printed circuit board mounted circuit testing method suitable for in-circuit testing of circuits that cannot be contacted.

[Conventional method]

FIG. 3 is a schematic diagram of an in-circuit tester and a printed circuit board to be tested. In FIG. 3, the tester CPU 9 outputs a test signal to the test pin 11 on the table 10 according to the test pattern information read from the floppy disk 8, and processes the data returned from the circuit mounted on the printed circuit board 14 to be tested. do.

The probe pin 14 of the test jig 13 whose position is set based on the test jig manufacturing numerical control information and the test tube 1
1 means cable 12 based on automatic wiring numerical control information.
Wired connection is made by On the front side of the printed circuit board 15,
Electronic components 16, 17, etc. that make up the circuit are mounted.

The printed circuit board 15 usually has holes for inserting component pins formed at equal intervals at grid point positions. The pins of the electronic components are connected on the back side of the printed circuit board 15 to form a circuit.

In recent years, as electronic components have become smaller, some IC pins and the like (hereinafter referred to as lattice-missing components) have appeared whose pin spacing is narrower than the hole spacing of a printed circuit board. Additionally, the scale of the circuits mounted on printed circuit boards has become larger, and for this reason electronic components are often directly connected to the front surface of the printed circuit board (such components are referred to as surface-mounted components).

In this case, since the test probe pins 14 are brought into contact with the back side of the board as shown in FIG. 3, it is not possible to test the quality of individual electronic components.

For this reason, conventionally, for example, electronic packaging technology (ElectronicPack
aging Technology) 1986.2. V
ol, 2. As described in No. 2, "Trends in inspection systems for high-density, high-multilayer technology, etc.," when designing printed circuit board mounting, surface mount components are provided with dedicated lands for contacting probe pins, and parts that miss the grating are I am trying to prepare test points for this.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into account the contact method of the probe pin when the surface mount components and the grid off-grid components are mounted very close to each other and are directly connected. If the components are mounted and connected, there is a problem that it is not possible to create dedicated lands or grid extraction contact points, making it impossible to test such components.

When using surface mount components or grating off-grid components, it is necessary to consider the test method of the printed circuit board from the mounting design stage. Since the purpose is to implement efficiently without creating any problems, creating test lands and grid drawer test points is an obstacle to implementation design.

An object of the present invention is to provide a printed circuit board mounting circuit testing method that allows testing of printed circuit boards mounted with surface mount components and grid off-grid components using an in-circuit tester without affecting the mounting design as described above. It is in.

(Means for solving the problem) The above purpose is to divide the circuit of the printed circuit board under test into circuits that can be pinned with probe pins and circuits that cannot be pinned with probes, and the circuits that can be pinned with probes are connected to logical connection networks. Test the operation of the component by touching one probe pin to each net, and extract circuits that include the circuit where probe pins cannot be set, and make probe bins that can surround the area where probe pins cannot be set. A probe pin is brought into contact with the component, a test pattern is generated for the circuit surrounded by this probe pin, and this test pattern is supplied from the probe pin that was previously set up in the area where the probe pin can be set up to check the output value. This is achieved by doing so.

[Effect]

For circuits that cannot be probe pinned, divide and extract them.
A test pattern is supplied to the entire circuit, and the quality of the circuit and its components is determined based on the output value. This makes it possible to test circuits that cannot be probe pinned without providing test lands or test points, which simplifies mounting design and allows larger circuits to be mounted on printed circuit boards. Become.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a configuration diagram of an apparatus for carrying out a printed circuit board mounting circuit testing method according to an embodiment of the present invention.

In FIG. 2, a central processing unit (CPtl) 1 extracts and processes data from each peripheral device according to a predetermined program, and controls the operation of each peripheral device. 2 is a video terminal for inputting batch jobs to the CPU 1 and checking job run results. A magnetic disk device 3 stores logical design information and packaging design information of the printed circuit board to be inspected, as well as intermediate results of processing by the CPU i. 4 is memory, CPU
Contains the program that operates 1. 5 is a tape output device that outputs the pin position of the probe pin determined by the processing in the CPU 1 to the test jig manufacturing numerical control paper chip of the in-circuit tester, and also outputs the pin position of the probe pin determined by the processing in the CPU 1 to the test jig manufacturing numerical control paper chip of the in-circuit tester. Outputs the wiring connection with the tool onto automatic wiring numerical control paper tape.

A floppy disk output device 6 stores test pattern information used in the in-circuit tester on a floppy disk. 7 is a line printer device, CPU 1
Outputs the job processing results in .

FIG. 1 is a flowchart showing an example of a printed circuit board testing method. First, from video terminal 2 to C in Figure 2
PU 1 is instructed to start work, and processing in CPU 1 starts (step 100).

The CPU 1 reads the mounting design information of all the components mounted on the printed circuit board from the magnetic disk device i3, and stores it in the memory 4 (step 101). As shown in Fig. 4(a), the mounting design information consists of "component information" which is the mounting information of one component repeated as many times as the number of components on the printed circuit board, and each "component information" is ``Component type'' that indicates the physical ``mounting position name'' of the component mounted on the board, surface mount component, or grid off-grid component. The mounting information consists of "direction,""pinnumber," which represents the mounting information of the pins of the component, and "pin coordinates." still,
The "pin number" and "pin coordinates" are repeated for the number of pins of the component.

After reading such mounting design information, CPU 1
The logical design information of the printed circuit board in the magnetic disk device 3 is read in one equivalent connection (hereinafter referred to as "net") and stored in the memory 4 (102). Here, the logical design information of the printed circuit board is data indicating the logical connection relationship between electronic components on the board and the printed circuit board, and a specific example thereof is shown in FIG. 4(b). Figure 4(b) represents the logical design information for one net, including the "mounting position pointer" pointing to the mounting design information of one component, the "pin number" of the component pin connected to the net, and the ""Netnumber" is stored for the number of pins in the net.

After reading this one net information, the CPU 1 determines whether the logic design information is complete (step 103), and if so, proceeds to logic circuit division processing 10B.

If the logical design information is not complete, the process advances to step 104, and it is determined whether it is possible to place a pin on the read net. This judgment is made based on whether all the pins of the components connected to one net are surface-mounted components mounted on the front surface of the printed circuit board, components that are off-grid components, or regular components mounted on the back surface of the printed circuit board. As a result of this judgment (step 104), if any one of the component pins on one net can be pinned, the process advances to step 106.
Perform probe pin assignment processing. If there is no place to set a probe pin on one net, this net is registered as a net where probe pins cannot be set in the net table where pins cannot be set as shown in Figure 4(d) provided in Memo+74, and the next net is The process returns to the reading process 102. In step 106, where the probe pin stand position is determined, the probe pin assignment is performed so that one probe pin stands on the (1) net without fail.

The probe pin number determined in this way is set and registered at the corresponding position of the net information read in step 102 in the pin setting table shown in FIG. 4(C) provided in the memory 4.

Once all the net information in the magnetic disk drive 4 has been read and the nets that cannot be probe bin erected and the nets that can be erected probe pins have been classified, the process proceeds to step 108, where circuit division processing is performed.

In step 108, it is determined whether or not there is a net that cannot be used to set the probe pin. If there is no such net, the process proceeds to step 114, and normal electronic component processing is performed. As a result of the determination in step 108, if there is a net that cannot be pinned, the logic design information for one net on the net table that cannot be pinned is rewritten. That is, the component pins on the net are rearranged in ascending or descending order of the mounting position pointer, and pins of components located at the same mounting position are collected (step 109). For example, if the circuit shown in Figure 5 is mounted on a printed circuit board (the parts with diagonal lines in the diagram are parts that cannot be mounted on a probe bottle, the capital letters are the mounting position pointer numbers, and the one-digit Arabic numerals are the pins). (The numbers in the 700s are net numbers.) The contents of the net table that cannot be pinned before the process of step 109 is as shown in Figure 6(a), but the process of step 109 is When executed, the contents shown in FIG. 6(b) will be obtained. Here, specify the net number (70
(numbers in the 0 range), classify the net numbers connected to the same mounting position, and create a series in which the probe pin cannot be set. In the case of FIG. 5, as shown in step 801 of FIG.
Net number 701-702-703-704 and 70
It can be seen that 5 is a series in which the probe bottle cannot be set. In this way, in step 110 of FIG. 1, an impossible net series is created for all the probe pin stands on the printed circuit board. Next, a process of adding a net for determining the probe pin position for providing an input test pattern (TP) and the probe pin position for observing the output value to the net series where the probe pin cannot be set created here (step 112) The net series completed here becomes the target divided circuit. The processing procedure is first step 1.
In step 11, it is checked whether or not there are any sequences in which probe pinning is not possible. If there is a series where probe pin-setting is not possible, extract all nets that connect to components at the mounting position included in the probe-pin-setting impossible series from the probe pin-setting possible net table, and combine them with the probe pin-setting impossible nets. form a divided circuit.

In the case of FIG. 5, the processing procedure is steps 802 and 803 in FIG. 7, and the division circuit 1. It is completed. Next, a test pattern is generated for this divided circuit, and the result is temporarily output to the magnetic disk device 3 (step 113).
. By repeating the processes from steps lit to 113, test patterns for all probe pin-setting impossible series on the printed circuit board can be generated.

Next, the process advances to step 114 to generate a pattern for normal electronic components, and this test pattern is also temporarily output to the magnetic disk 3. In step 115, the test pattern for the divided circuit created in step 113 and the test pattern created in step 114 are generated. The pattern is read from the magnetic disk device 3, edited as a test pattern for the in-circuit tester, and outputted to the floppy disk device 6.

Finally, output the test jig manufacturing numerical control paper tape and the automatic wiring numerical control paper tape according to the probe pin erecting net table and mounting design information to complete all processes (step 116).

As explained above, according to this embodiment, the division is not performed according to the circuit logic of the circuit mounted on the printed circuit board, but is performed according to the arbitrary region where the probe bin cannot be set up due to the shape of the mounted components, the mounting condition, etc. Since this is a method, it is possible to easily cope with increasing the scale of circuits mounted on printed circuit boards.

〔Effect of the invention〕

According to the present invention, when there is a net on a printed circuit board that connects components that cannot be brought into contact with probe pins, a divided circuit is created that is composed of the components and the components that can be contacted by the probe pins surrounding the components. Since test patterns can be generated, operation tests can be performed using an in-circuit tester even on printed circuit boards for which probe pins cannot be directly installed.

[Brief explanation of the drawing]

Fig. 1 is a flowchart showing one embodiment of the processing procedure of the present invention, Fig. 2 is a diagram of the equipment configuration of a computer implementing the present invention, Fig. 3 is a conceptual diagram of an in-circuit tester and a printed circuit board, and Fig. 4 (a), Φ), (C). (d) is an explanatory diagram of mounting design information, logical connection information, a pin-up possible table, and a pin-up impossible table, respectively; FIG. 5 is a circuit diagram showing a general example of the present invention; and FIG. 6 (a). (b) is an explanatory diagram of the table rewriting operation in the computer memory according to the present invention, and FIG. 7 is a flowchart showing the procedure for creating a divided circuit. 1...Central processing unit (CPU), 2...Video terminal, 3...Magnetic disk device, 4...Memory,
5... Paper tape output device, 6... Floppy disk output device, 7... Line printer device, 8... Floppy disk input device, 9... Tester CPU. Agent Patent Attorney Tadashi Akimoto Figure 1 Figure 2 Figure 3 Figure 1 Day Figure 4 Figure 5 Figure 6 (a) (b) Arrangement of procedure (voluntarily) March 10, 1988

Claims (1)

[Claims] 1. In an in-circuit tester that supplies test patterns to circuit components mounted on the board from probe pins set up on the printed circuit board and observes output signals from the electronic components, a logic design that shows the logical connection relationships of electronic components on the printed circuit board. information and mounting design information indicating the connection state of the printed circuit board's printed circuit board and the mounting state of electronic components on the printed circuit board, and process the logic design information and mounting design information to make it impossible to set up probe pins. Separates logical connection information where electronic components are directly connected to each other from other logical connection information, and generates a test pattern for each logic circuit where electronic components that cannot be probe pinned are connected to each other. A method for testing a circuit mounted on a printed circuit board, characterized in that a probe pin is set up at a test point connected to the logic circuit where it is impossible to set a probe pin, and the logic circuit is tested using the test pattern.