JP2000216200A - Semiconductor device and its manufacture, and tape carrier, circuit board, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To see that the end face of wiring is not exposed to the flank of a semiconductor device. SOLUTION: This method includes a first step of preparing a tape carrier 40 where a plurality of through holes 28 are made and a plurality of electrically independent wirings 22 passing, on one side, above the through holes 28 are made, a second step of applying electroless plating to the wiring 22, a third step of mounting a semiconductor chip 10 to the tape carrier 40, with its face down, and covering the surface, side, and head face of the wiring 22, and a fourth step of striking the tape carrier 40 in the position excluding the wiring 22 outside the semiconductor chip 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, a tape carrier, a circuit board, and electronic equipment.

[0002]

BACKGROUND OF THE INVENTION Among CSP (Chip Scale / Size Package) type semiconductor devices, a structure in which a semiconductor chip is mounted face down (flip chip connection) on a substrate is known as one form. Using tape as a substrate, forming a plurality of wiring patterns corresponding to a plurality of semiconductor devices on the substrate, and punching out a tape according to each semiconductor device after mounting a semiconductor chip can improve productivity. it can. The respective wiring patterns are electrically connected to each other to perform electrolytic plating, and the wiring patterns are cut when the tape is punched.

Therefore, the cut surface of the wiring pattern is exposed on the end surface of the substrate of the completed semiconductor device. And
Corrosion may progress from the exposed cut surface toward the electrode of the semiconductor chip. In addition, due to the narrow pitch between the individual wirings constituting the wiring pattern, a short circuit may occur due to, for example, a conductive foreign substance intervening in the exposed cut surface, and the function may be impaired.

[0004] In particular, as the miniaturization of a CSP-type semiconductor device progresses, the necessity for taking measures to solve these problems increases.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of exposing an end face of a wiring on a side surface of the semiconductor device, a method of manufacturing the same, a tape carrier, and a circuit board. Another object of the present invention is to provide an electronic device.

[0006]

(1) In a method of manufacturing a semiconductor device according to the present invention, a plurality of through holes are formed,
A first step of preparing a substrate on one side of which is formed a wiring electrically connected to each of the through holes;
A second step of applying electroless plating to the wiring, and a third step of mounting at least one semiconductor chip face down on the substrate and covering the entire non-contact surface of the wiring with the substrate with a resin, A fourth step of punching the substrate at a position outside the semiconductor chip and avoiding the wiring.

According to the present invention, the wiring can be plated by applying electroless plating. Further, since the substrate is punched at a position where the wiring is avoided in the fourth step, the wiring is not cut and the cut surface is not exposed. The wiring is covered with a resin in the third step. Thus, according to the obtained semiconductor device, since the end face of the wiring is not exposed, it is possible to cut off the moisture entry path. In addition, since there is no plating lead required when performing electrolytic plating, wiring design efficiency is improved, and a multi-pin (multi-grid) semiconductor device (particularly, a CSP) can be easily designed. Further, since there is no plated lead, a signal is not transmitted to an unnecessary lead, and transmission characteristics are improved.

(2) In this manufacturing method, in the third step, the semiconductor chip is face-down mounted via an anisotropic conductive material in which conductive particles are contained in the adhesive as the resin, and the wiring is formed. The wiring may be covered by providing the anisotropic conductive material so as to cover the entire non-contact surface with the substrate.

According to this, the semiconductor chip can be easily mounted, and the wiring can be covered simultaneously with the mounting.

(3) In this manufacturing method, the method may further include a step of providing a plurality of external terminals electrically connected to the wiring via a conductive member in the through hole.

(4) In this manufacturing method, one end of each of the wirings is joined to one of the electrodes of the semiconductor chip, and the other end is connected to any one of the electrodes via a conductive member in the through hole. May be bonded to the external terminal.

In this way, the electrodes of the semiconductor chip and the external terminals are joined to both ends of the wiring, so that the wiring is formed only on the path that requires signal transmission, and the transmission characteristics are improved. .

(5) In this manufacturing method, a plurality of semiconductor chips may be face-down mounted on the substrate in the third step, and the substrate may be punched for each semiconductor chip in the fourth step.

This improves the productivity of the semiconductor device.

(6) In this manufacturing method, the substrate may be a tape carrier.

(7) The semiconductor device according to the present invention is manufactured by the above method.

(8) In the semiconductor device according to the present invention, a plurality of through holes are formed, and one surface of each of the wirings is electrically connected to each of the through holes and subjected to electroless plating. A formed substrate, an adhesive containing conductive particles, an anisotropic conductive material covering the entire non-contact surface of the wiring with the substrate, and a face on the substrate via the anisotropic conductive material. The semiconductor device includes a down-mounted semiconductor chip, and a plurality of external terminals electrically connected to the wiring via a conductive member in the through hole.

According to the present invention, since the end face of the wiring is not exposed, it is possible to cut off the path of moisture. Further, since there is no plating lead which is necessary when performing electrolytic plating, wiring design efficiency is improved, and multi-pin (multi-grid) can be realized. Further, since there is no plated lead, a signal is not transmitted to an unnecessary lead, and transmission characteristics are improved.

(9) In this semiconductor device, one end of each of the wirings is joined to one of the electrodes of the semiconductor chip, and the other end is connected to any one of the electrodes via a conductive member in the through hole. May be bonded to the external terminal.

By doing so, the electrodes of the semiconductor chip and the external terminals are joined to both ends of the wiring, so that the wiring is formed only on the path that requires signal transmission, and the transmission characteristics are improved. .

(10) The tape carrier according to the present invention comprises:
A tape-shaped substrate on which a plurality of through holes are formed, and a plurality of wirings which are electrically independent and electrolessly plated through the through holes on one surface of the substrate, The wiring forms a plurality of wiring patterns for a plurality of semiconductor devices.

According to the present invention, a plurality of wirings are plated by applying electroless plating although they are electrically independent.

(11) The above semiconductor device is mounted on a circuit board according to the present invention.

(12) An electronic apparatus according to the present invention includes the above semiconductor device.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. The semiconductor device 1 includes a semiconductor chip 10 and a substrate 20. When the planar shape of the semiconductor chip 10 is rectangular (square or rectangular), a plurality of semiconductor chips 10 are arranged on one surface (active surface) of the semiconductor chip 10 along at least one side (including two opposing sides or all sides). Electrodes 12 are formed. The bumps 1 are formed on the electrodes 12 by solder balls, gold wire balls, gold plating, or the like.
4 are provided. The electrode 12 itself may be in the form of a bump. Nickel, chromium, titanium, or the like may be added between the electrode 12 and the bump 14 as a diffusion preventing layer for the bump metal.

The overall shape of the substrate 20 is not particularly limited, and may be a rectangle, a polygon, or a combination of a plurality of rectangles, but may be similar to the planar shape of the semiconductor chip 10. . The thickness of the substrate 20 is often determined by its material, but is not limited thereto.
The substrate 20 may be formed of any of an organic or inorganic material, and may be formed of a composite structure thereof, but is preferably punched out. The substrate 20 can be formed by punching out a tape-shaped flexible substrate formed from an organic material. For example, a plurality of substrates 20 are obtained by punching out the carrier tape 40 shown in FIG.

FIG. 2 is a plan view of the substrate of the semiconductor device shown in FIG. As shown in FIGS. 1 and 2, a plurality of wirings (leads) 22 are formed on one surface of the substrate 20.
The wiring pattern 42 is formed. At least one or all of the plurality of wirings 22 are not electrically connected to the other wirings 22 and are electrically independent. Or,
Among the plurality of wirings 22, lands may be connected to a common wiring connected to a power supply, a ground, or the like of the semiconductor chip 10. Land portions 24 and 26 are formed at both ends of each wiring 22. Land part 2
4 and 26 are often formed to have a greater width than the part connecting them. One land portion 24 is formed on the substrate 20 at a position near the end of the semiconductor device as a final product, and the other land portion 26 is formed on the substrate 2.
It may be formed at a position near the center of 0.

The substrate 20 has a plurality of through holes 28 formed therein. One of the wirings 22 passes through each through hole 28. The end of the wiring 22 may be located on the through hole 28. When the land 26 is formed at the end of the wiring 22, the land 26 is located on the through hole 28.

A plating layer 30 is formed on the wiring 22. The wiring 22 can be formed of copper, and the plating layer 30 can be formed of nickel, gold, solder, or tin. By forming the plating layer 30, conductivity is ensured. Specifically, good soldering with external terminals is possible,
The oxidation of the surface of the wiring 22 is prevented, and the electrical connection resistance with the bump is reduced.

Since each wiring 22 is electrically independent, the plating layer 30 can be formed by electroless plating. The plating layer 30 is formed on the surface of the wiring 22 opposite to the surface to be bonded to the substrate 20.
The plating layer 30 is also formed on an area of the wiring 22 that is bonded to the substrate 20 and inside the through hole 28.
This region can also be a part of the land portion 26. further,
The plating layer 30 is also formed on the side surface and the tip surface of the wiring 22.

The semiconductor chip 10 is mounted face down on the substrate 20. Bump 1 of semiconductor chip 10
4 and the wiring 22 formed on the substrate 20 are electrically connected. Since the plating layer 30 is formed on the wiring 22, good electrical connection is obtained. When the lands 24 and 26 are formed on the wiring 22, one of the lands 2
4 and the bump 14 are electrically connected. As an electrical connection means, an anisotropic conductive material 32 in which conductive particles are contained in an adhesive made of resin may be used. In that case, the conductive particles are interposed between the wiring 22 and the bumps 14 to achieve electrical conduction. The anisotropic conductive material 32 may be an anisotropic conductive film or an anisotropic conductive adhesive.

When the anisotropic conductive material 32 is used, the surface, the side surface, and the tip surface of the wiring 22 on the side opposite to the bonding surface with the substrate 20 are covered. When the anisotropic conductive material 32 is not used, the surface, the side surface, and the tip surface of the wiring 22 on the side opposite to the bonding surface with the substrate 20 are covered with a resin such as an underfill material. The material covering the wiring 22 may cover the entire surface of one surface of the substrate 20.

An external terminal 34 is electrically connected to the wiring 22. The external terminal 34 is often a solder ball, but may be a conductive protrusion such as plating or conductive resin. The external terminal 34 can be electrically connected to the wiring 22 via a conductive member in the through hole 28. The through holes 28 may be filled with a conductive member such as solder, and the external terminals 34 may be provided directly on the wiring 22. In particular, if the electrode 12 of the semiconductor chip is connected to one end of the wiring 22 and the external terminal 34 is connected to the other end of the wiring 22, the wiring 22 is formed only on the electrical path between them. That is, the signal transmission characteristics are improved. In other words, extra wiring patterns other than the electrical path in design,
For example, since no plating lead is required, signal reflection and the like are reduced. The wiring 22 has a through hole 28
Because the plating layer 30 is formed also on the exposed portion, good electrical connection between the external terminal 34 and the wiring 22 can be obtained. Alternatively, a second wiring that is electrically connected to the wiring 22 through the through hole 28 may be formed on the other surface of the substrate 20, and an external terminal may be provided on the second wiring. In this case, the substrate 20 is a double-sided substrate since wiring is formed on both surfaces. Further, as the substrate 20,
A multilayer substrate or a build-up type substrate may be used, and the wiring (lead) on the surface is located within the outer shape of the semiconductor device as a final product and is entirely covered with the resin covering the wiring and is subjected to electroless plating. It should just be. When using a build-up type substrate or multilayer substrate, if a wiring pattern is formed on a beta land layer that spreads out in a plane, a microstrip structure with no extra wiring pattern will be obtained, so that signal transmission characteristics will be further improved. Can be.

In the above description, the face-down type junction using the anisotropic conductive material has been described. However, the present invention is not limited to the face-down type junction of this type, and the semiconductor chip with solder bumps is heated (necessary). Pressurizing according to the temperature) or heating and heating a semiconductor chip with gold bumps.
The present invention can also be applied to a method of applying pressure (ultrasonic bonding if necessary) or a method of face-down bonding using a curing shrinkage force of a resin.

In the above-described embodiment, all the portions on the wiring 22 are electrolessly plated. However, if necessary, only the portions related to the connection are electrolessly plated, and the other portions are electrolessly plated. It may be covered with a resin such as a resist without electrolytic plating.

FIG. 1 shows a FAN-IN type semiconductor device in which the wiring 22 is formed only in the mounting area of the semiconductor chip 10 and the external terminals 34 are provided only in the mounting area of the semiconductor chip 10. But not limited to this. For example, the FAN-OUT type semiconductor device in which the wiring 22 is drawn out of the semiconductor chip 10 and the external terminal 34 is provided only outside the mounting area of the semiconductor chip 10 or the FAN-IN type in which the FAN-IN type is combined with the FAN-OUT type semiconductor device. IN
The present invention can be applied to a / OUT type semiconductor device. In any case, the wiring 22 may be subjected to electroless plating and covered with a resin, and the outside may be punched out so as to become the outer shape of the semiconductor device. In addition, FA
In an N-OUT type or FAN-IN / OUT type semiconductor device, a stiffener may be attached to the outside of the semiconductor chip with a resin that covers the wiring.

In addition to the above-described embodiment, before mounting the semiconductor chip, one or more holes (for example, long holes) are preferably partially or preferably not less than half of the outer position of the semiconductor device.
May be formed, and after mounting the semiconductor chip, the remaining portion (for example, a portion between a plurality of holes) of the outer shape position may be punched.

The present embodiment is configured as described above, and its manufacturing method will be described below.

(First Step) The above-mentioned substrate 20 can be formed by punching a substrate (base material) larger than that. In the present embodiment, the tape carrier 4 shown in FIG.
Prepare 0. A plurality of substrates 20 can be obtained from the tape carrier 40 by punching. That is, the tape carrier 40 includes a plurality of wirings 2 forming a plurality of wiring patterns 42 corresponding to the plurality of substrates 20.
2 are formed. The tape carrier 40 includes the wiring 22
Except that the plating layer 30 is not formed on the substrate 20 (see FIGS. 1 and 2).

(Second Step) Next, the wiring 22 formed on the tape carrier 40 is subjected to electroless plating to form a plating layer 30 as shown in FIG.

(Third Step) The semiconductor chip 10 is provided on each wiring pattern 42 formed on the tape carrier 40.
Is mounted face down. For example, as shown in FIG. 1, an anisotropic conductive material 32 can be used. The anisotropic conductive material 32 is used for the electrode 12 in the semiconductor chip 10.
May be provided in advance on the surface where the wiring 22 is formed, or may be provided in advance on the surface of the tape carrier 40 where the wiring 22 is formed. The anisotropic conductive material 32 may be provided so as to cover each wiring pattern 42, or the anisotropic conductive material 32 may be provided so as to cover a plurality of wiring patterns 42.

Then, the surfaces, side surfaces, and front end surfaces of all the wirings 22 are covered. When the anisotropic conductive material 32 is used, the anisotropic conductive material 32 may be provided to cover the anisotropic conductive material 32 at the same time. Alternatively, it may be covered with another material.

Further, an external terminal 34 shown in FIG. 1 is provided.
The details of the external terminal 34 are as described in the present embodiment.

In this way, as shown in FIG. 4, a plurality of semiconductor chips 10 are mounted on the tape carrier 40 to obtain a semiconductor device assembly in which the plurality of semiconductor devices 1 are integrated.

(Fourth Step) As shown in FIG. 4, the tape carrier 40 is punched at a position outside the respective semiconductor chips 10 and away from the wirings 22. The punched shape is not particularly limited, but may be similar to the planar shape of the semiconductor chip 10. For the punching, cutting jigs 44 and 46 can be used. Thus, the semiconductor device 1 can be manufactured continuously.

According to this embodiment, since the plurality of wirings 22 are formed in an electrically independent state in advance, the plating layer 30 can be formed on the wirings 22 by applying electroless plating. Further, since the tape carrier 40 is punched at a position avoiding the wiring 22 in the fourth step, the wiring 22 is not cut and the cut surface is not exposed. According to the semiconductor device 1 thus obtained, since the end surface of the wiring 22 is not exposed, it is possible to cut off the ingress path of moisture, and to provide a resin or the like on the side surface of the semiconductor device to cover the cut surface. It is not necessary. Further, since there is no plating lead which is necessary when performing electrolytic plating, wiring 2
2 improves the design efficiency, and can easily design a multi-pin (multi-grid) semiconductor device (especially a CSP). Further, since there is no plated lead, a signal is not transmitted to an unnecessary lead, and transmission characteristics are improved.

FIG. 5 shows a circuit board 50 on which the semiconductor device 1 according to the present embodiment is mounted. Circuit board 5
For 0, an organic substrate such as a glass epoxy substrate is generally used. A wiring pattern 52 made of, for example, copper is formed on the circuit board 50 so as to form a desired circuit, and the electrical connection between the wiring pattern and the external terminal 34 of the semiconductor device 1 is made by mechanical connection. Conduct continuity.

FIG. 6 shows a notebook personal computer as an electronic apparatus 60 having the semiconductor device 1 to which the present invention is applied.

It is to be noted that the constituent element "semiconductor chip" of the present invention is replaced with "electronic element", and an electronic element (whether active element or passive element) is mounted on a substrate in the same manner as a semiconductor chip. Parts can also be manufactured. Electronic components manufactured using such electronic elements include, for example, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, or fuses.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a substrate of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a diagram showing a tape carrier used in the embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a diagram showing a circuit board according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating an electronic apparatus including a semiconductor device manufactured by applying the method according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor chip 20 Substrate 22 Wiring 28 Through hole 30 Plating layer 32 Anisotropic conductive material 34 External terminal 40 Carrier tape 42 Wiring pattern 50 Circuit board 60 Electronic device

Claims (12)

[Claims] A first step of preparing a substrate on which a plurality of through holes are formed and a wiring formed on one surface and electrically connected to each of the through holes; A second step of performing electroless plating, a third step of mounting at least one semiconductor chip face-down on the substrate, and covering the entire non-contact surface of the wiring with the substrate with a resin, A fourth step of punching the substrate at a position outside and avoiding the wiring. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the third step, the semiconductor chip is faced via an anisotropic conductive material in which conductive particles are contained in an adhesive as the resin. A method of manufacturing a semiconductor device, wherein the semiconductor device is mounted down and covers the wiring by providing the anisotropic conductive material over the entire non-contact surface of the wiring with the substrate. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of providing a plurality of external terminals that are electrically connected to the wiring via a conductive member in the through hole. Device manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein one end of each of said wirings is joined to one of electrodes of said semiconductor chip, and the other end is a conductive material in said through hole. A method for manufacturing a semiconductor device to be joined to any one of the external terminals via a member. 5. The method for manufacturing a semiconductor device according to claim 1, wherein a plurality of semiconductor chips are mounted face-down on said substrate in said third step, and each of said plurality of semiconductor chips is mounted in said fourth step. A method of manufacturing a semiconductor device, wherein the substrate is punched for each semiconductor chip. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the substrate is a tape carrier. 7. A semiconductor device manufactured by the method according to claim 1. 8. A substrate having a plurality of through-holes formed therein and a wiring formed on one surface thereof and electrically connected to each of the through-holes and subjected to electroless plating. An anisotropic conductive material that contains conductive particles and covers the entire non-contact surface of the wiring with the substrate, a semiconductor chip face-down mounted on the substrate via the anisotropic conductive material, And a plurality of external terminals electrically connected to the wiring via a conductive member in the through hole. 9. The semiconductor device according to claim 8, wherein one end of each of said wirings is joined to one of electrodes of said semiconductor chip, and the other end is connected to a conductive member in said through hole. A semiconductor device joined to any one of the external terminals. 10. A tape-shaped substrate having a plurality of through-holes formed thereon, and a plurality of wirings which are electrically independent and are subjected to electroless plating on one surface of the substrate by passing over the through-holes. Wherein the wiring comprises a plurality of wiring patterns for a plurality of semiconductor devices. 11. A circuit board on which the semiconductor device according to claim 7 is mounted. 12. An electronic apparatus comprising the semiconductor device according to claim 7.