JP2000208733A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a capacity element which is structured so that a plate electrode layer functions not only as a plate electrode but also has other purposes. SOLUTION: The capacity element of a semiconductor device is provided with a storage electrode 103 connected with a source/drain region of an Si substrate 101 under a first interlayer insulation film 102 via a contact penetrating the first interlayer insulation film 102, a capacity insulation film 104 formed on the storage electrode 103, a capacity insulation film 104 formed on the storage electrode 103, a plate electrode 105 facing the storage electrode 103 with the capacity insulation film 104 inbetween, and a second interlayer insulation film 106 formed on the plate electrode 105. The plate electrode 105 is made of an n-type semiconductor and is composed of a lower layer 105a functioning as a plate electrode and an upper layer 105b made of a p-type semiconductor. If a Vcc is supplied to the n-type semiconductor lower layer 105a, a pn joint normal current does not run in the p-type semiconductor upper layer 105b, even when the potential is made to vary from the ground potential to Vcc, the structure can be made to function as a signal wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitance element and a method of manufacturing the same, and more particularly, to a miniaturized semiconductor device having a plate electrode and a semiconductor layer having functions other than the plate electrode. And a method of manufacturing the same.

[0002]

2. Description of the Related Art A typical semiconductor device having a capacitance element is a DRAM. By the way, with the miniaturization of computers, electronic devices, and the like, semiconductor devices having a capacitance element such as a DRAM are increasingly required to be highly integrated and miniaturized. Therefore, a capacitor having a stacked capacitor structure, which can reduce the required area, is being widely used.

[0003] Here, referring to FIG.
The configuration of a DRAM having a capacitor structure will be described. Figure
4 is a main part of the conventional DRAM, that is, a stacked capacitor.
FIG. 3 is a cross-sectional view of a substrate showing a configuration of a capacitive element having a structure. In FIG.
Describes only the capacitor structure which is the main part related to the present invention.
And cell transistors and bit lines are omitted. capacity
The element has a contact penetrating the first interlayer insulating film 402.
Of the Si substrate 401 under the first interlayer insulating film 402
Area, for example, the storage current connected to the source / drain
Pole (n⁺) 403 and the volume formed on the storage electrode 403
Storage electrode via the capacitive insulating film 404 and the capacitive insulating film 404
403 and a plate electrode (n ⁺) 405 and pre
A second interlayer insulating film 406 formed on the gate electrode 405 and
It has. The plate electrode 405 is a second interlayer insulating film
And upper wiring 407 through a contact penetrating through 406
Connected.

[0004]

By the way, in the conventional capacitive element, as shown in FIG.
A capacitor insulating film 404 and a plate electrode 405 are formed thereon. Generally, the plate electrode 405 is often made of phosphorus-doped polycrystalline silicon, and has a structure in which the entire memory cell region is covered with n-type polycrystalline silicon. Only functioned as. That is, conventionally, a plate electrode functioning only as a plate electrode of a memory cell occupies a large area of a semiconductor device, particularly, a capacitor. In this case, it has been difficult to miniaturize the capacitive element, that is, a semiconductor device having the capacitive element, for example, a DRAM.

It is an object of the present invention to provide a semiconductor device having a capacitor and a method of manufacturing the same, wherein the plate electrode layer occupying this large area of the capacitor serves not only as a plate electrode but also performs other functions. It is to provide.

[0006]

In order to achieve the above object, a semiconductor device according to the present invention (hereinafter referred to as a first invention) comprises a storage electrode connected to a substrate via a contact,
In a semiconductor device including a plate element facing a storage electrode and a capacitive element having a capacitive insulating film interposed between the storage electrode and the plate electrode, the plate electrode may include a first electrode.
And a plate electrode layer formed on the side of the capacitor insulating film as the semiconductor layer of the second conductivity type, and a layer formed on the side opposite to the capacitor insulating film as the second semiconductor layer of the second conductivity type. It is characterized by:

According to the present invention, a plate electrode layer formed on the capacitor insulating film side as a first conductive type semiconductor layer of the plate electrode, and a second conductive type semiconductor layer formed on the side opposite to the capacitor insulating film. These layers function as electrically independent and separate layers based on the principle of pn junction separation. For example, a semiconductor layer of the first conductivity type is a plate electrode,
The semiconductor layer of the second conductivity type can function as a signal wiring.

In a preferred embodiment of the present invention, a predetermined region of the semiconductor layer of the second conductivity type of the plate electrode is converted into the first semiconductor layer and connected to the upper wiring via a contact.

Another semiconductor device according to the present invention (hereinafter referred to as a second
A semiconductor device comprising: a storage electrode connected to a substrate via a contact; a plate electrode facing the storage electrode; and a capacitor having a capacitor insulating film interposed between the storage electrode and the plate electrode. In the device, a plate electrode is formed as a first conductive type semiconductor layer on the side of the capacitor insulating film, and a plurality of second conductive type semiconductor layers electrically independent from each other are provided as capacitive insulating layers. It is characterized by comprising a film and a layer formed on the opposite side.

In the second invention, in addition to the function of the constituent elements of the first invention, a second conductive type semiconductor layer of the plate electrode is further separated into a layer formed on the side opposite to the capacitor insulating film. Function. For example, one can function as a power wiring and the other can function as a signal wiring.

Still another semiconductor device according to the present invention (hereinafter, referred to as a semiconductor device)
A third aspect of the present invention includes a capacitor having a storage electrode connected to a substrate via a contact, a plate electrode facing the storage electrode, and a capacitor insulating film interposed between the storage electrode and the plate electrode. In the semiconductor device, the plate electrode is provided in the plate electrode layer formed as the first conductivity type semiconductor layer on the capacitor insulating film side, in the second conductivity type well, and in the second conductivity type well. And a layer formed on the side opposite to the capacitor insulating film as a semiconductor layer having at least one of the active element and the wiring.

According to a third aspect of the present invention, in addition to the function of the components of the first aspect, a semiconductor layer of the second conductivity type of the plate electrode is formed on a layer formed on the side opposite to the capacitor insulating film. It is configured as a substrate, on which another active element is formed.

In the first to third inventions, the semiconductor layer of the first conductivity type is a layer formed as an n-type semiconductor layer,
The semiconductor layer of the second conductivity type may be a layer formed as a p-type semiconductor layer. In the present example, the p-type semiconductor layer can function as a wiring because a relationship in which a forward current of the pn junction does not flow from the n-type semiconductor lower layer to the p-type semiconductor upper layer is satisfied. Also, contrary to the above example, the first
The semiconductor layer of the second conductivity type may be a layer formed as a p-type semiconductor layer, and the semiconductor layer of the second conductivity type may be a layer formed as an n-type semiconductor layer.

A method of manufacturing a semiconductor device having a capacitor according to the present invention includes the steps of forming a storage electrode when forming a capacitor, forming a capacitor insulating film on the storage electrode, The method is characterized by comprising a step of forming a silicon film, a step of implanting boron only in the vicinity of the surface of the phosphorus-doped polysilicon film, and a step of performing heat treatment to activate ions.

In the step of forming the storage electrode, when forming and patterning the storage electrode, the storage electrode is patterned so that a gap in one direction and a gap in a direction intersecting in one direction are different from each other. To form a plurality of storage electrodes. Preferably, in the step of forming the phosphorus-doped polysilicon film, phosphorus (P)
A concentration gradient is set so that the concentration becomes low.

A semiconductor device according to the present invention (hereinafter, referred to as a fourth invention) is characterized in that the wiring layer is constituted by a semiconductor wiring layer including a p-type semiconductor layer and an n-type semiconductor layer. In the above-described first to third inventions, the present invention is directed to a plate electrode layer of a DRAM having a stacked capacitor structure. However, the fourth invention is not limited to this, and other semiconductors having a semiconductor wiring layer may be used. The present invention is also applicable to an apparatus. The wiring layer is composed of a semiconductor wiring layer including a p-type semiconductor layer and an n-type semiconductor layer, and the p-type semiconductor layer and the n-type semiconductor layer of the semiconductor wiring layer are electrically connected by the principle of pn junction separation. They function as independent and separate layers. For example, the p-type semiconductor layer can function as a power wiring and the n-type semiconductor layer can function as a signal wiring.

[0017]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 This embodiment is an example of an embodiment of a semiconductor device according to the first invention, and FIG. 1 is a cross-sectional view showing a main part of the semiconductor device of this embodiment, that is, a configuration of a capacitor. It is. As shown in FIG. 1, the capacitance element of the semiconductor device according to the present embodiment is
Via a contact penetrating the first interlayer insulating film 102,
Storage electrode 1 connected to a predetermined region of Si substrate 101 under first interlayer insulating film 102, for example, a source / drain region
03 and the capacitance insulating film 10 formed on the storage electrode 103
4, a plate electrode 105 facing the storage electrode 103 via the capacitor insulating film 104, and a second interlayer insulating film 106 formed on the plate electrode 105. The plate electrode 105 is made of an n-type semiconductor, and includes a lower layer 105a functioning as a plate electrode and an upper layer 105b made of a p-type semiconductor.

At present, the potential of the plate electrode is generally set to 1/2 Vcc. Also in this embodiment, when 1/2 Vcc is supplied to the n-type semiconductor lower layer 105a, the p-type semiconductor upper layer 105b thereon can function as, for example, a ground wiring. That is, in the present embodiment, the relationship that no forward current flows through the pn junction from the n-type semiconductor lower layer 105a to the p-type semiconductor upper layer 105b is satisfied.
Can function as wiring.

For example, when Vcc is supplied to the n-type semiconductor lower layer 105a functioning as a plate electrode,
Even if the potential is changed from the ground potential to Vcc, the pn junction forward current does not flow, so that the type semiconductor upper layer 105b can also function as a signal wiring. The plate electrode 105 in the predetermined region is formed as an n-type semiconductor layer in both the upper layer and the lower layer, and is connected to the upper wiring 107 via a contact penetrating the second interlayer insulating film 106. On the other hand, the p-type semiconductor upper layer 10 of the plate electrode 105
5b is connected to the signal wiring 108 via a contact.

Next, a method of manufacturing the capacitive element according to the first embodiment will be described with reference to FIG. After a MOS transistor or the like is formed (not shown) on the silicon substrate 101 according to a normal manufacturing method of a memory cell,
A first interlayer insulating film 102 is formed on a Si substrate 101.
Next, a contact penetrating the first interlayer insulating film 102 is formed, a storage electrode 103 is formed on the contact, and a capacitor insulating film 104 is formed on the storage electrode 103.

Next, a phosphorus-doped polysilicon film is formed as the plate electrode layer 105. At this time, it is desirable to provide a concentration gradient so that the phosphorus concentration becomes lower toward the surface. Next, boron is introduced only in the vicinity of the surface of the plate electrode layer 105 by an ion implantation method. Thereafter, a heat treatment is performed to activate the ions, thereby lowering the lower layer of the plate electrode layer 105 to the n-type semiconductor layer 10.
5a, and the upper layer can be formed as the p-type semiconductor layer 105b.

Next, the process proceeds to the step of forming the upper wiring 107 electrically connected to the plate electrode 105. First, a contact hole that penetrates through the second interlayer insulating film 106 and exposes the plate electrode 105 is opened at a desired place, and a p-type or n-type impurity is selectively formed at a desired contact bottom by using a lithography technique. And introduce p-type or n
Form a mold region. Next, the upper wiring 107 electrically connected to the plate electrode 105 can be formed by filling the contact hole with a wiring metal.

Embodiment 2 This embodiment is an example of an embodiment of a semiconductor device according to the second invention, and FIG. 2A is a plan view of a capacitive element provided in the semiconductor device of this embodiment. FIG. 2B is a cross-sectional view taken along the line AA in FIG. 2, and FIG.
It is sectional drawing of B cross section. As shown in FIGS. 2A to 2C, the capacitive element provided in the semiconductor device of the present embodiment is provided with the first element through a contact penetrating the first interlayer insulating film 202.
A storage electrode 203 connected to a predetermined region of the Si substrate 201 under the interlayer insulating film 202, for example, a source / drain region
And a capacitor insulating film 204 formed on the storage electrode 203
And a plate electrode 205 facing the storage electrode 203 via the capacitive insulating film 204, and a second interlayer insulating film 206 filling a groove space formed between the plate electrodes 205.

The plate electrode 205 is composed of a lower layer 205a made of an n-type semiconductor functioning as a plate electrode and an upper layer 205b made of a p-type semiconductor and existing as a plurality of electrically isolated regions. It is configured. Thus, the p-type upper semiconductor layers 205b that are electrically independent from each other can function as a plurality of independent power supply wirings or signal wirings.

Next, with reference to FIG. 2, a method of manufacturing the capacitive element of the second embodiment will be described. After a MOS transistor or the like is formed on the silicon substrate 201 (not shown) according to a normal manufacturing method of the memory cell,
A first interlayer insulating film 202 is formed on an i-substrate 201. Next, a contact penetrating the first interlayer insulating film 202 is formed, and subsequently, a storage electrode 203 is formed on the contact. Here, as shown in FIGS. 2A to 2C, BB
From the distance b between the individual storage electrodes 203 on the side visible in the cross section,
The distance a between the individual storage electrodes 203 on the side visible in the AA section
Is formed to be large. For example, if the interval a is 0.
5 μm and the interval b are set to 0.25 μm.

Next, the capacitor insulating film 2 is formed on the storage electrode 203.
04 is formed. Subsequently, a phosphorus-doped polysilicon film is formed as the plate electrode layer 205. At this time, so that the phosphorus concentration becomes thinner as it goes to the surface,
It is desirable to provide a concentration gradient. Next, boron is introduced only in the vicinity of the surface of the plate electrode layer 205 by an ion implantation method. After that, heat treatment is performed to activate the ions, whereby the lower layer of the plate electrode layer 205 can be formed as the n-type semiconductor layer 205a and the upper layer can be formed as the p-type semiconductor layer 205b.

In the formation of the plate electrode 205, the thickness of the phosphorus-doped polysilicon is set to, for example, 0.18 μm, and the distance a between the storage electrodes 203 does not become buried with the phosphorus-doped polysilicon film but follows the shape of the storage electrode 203. Thus, a groove of the phosphorus-doped polysilicon film is formed. On the other hand, the interval b between the storage electrodes 203 is buried with a phosphorus-doped polysilicon film. Thereafter, the phosphorus-doped polysilicon film is patterned to form a plate electrode layer 205 having upper layers independent of each other.
In order to form a plurality of independent p-type semiconductor regions, it is easy to selectively introduce p-type impurities by lithography. In the present embodiment, a method of forming without adding a lithography step is employed.

Next, by forming a thick second interlayer insulating film 206 and performing a flattening process such as CMP, the grooves formed at the interval a are buried in the second interlayer insulating film 206 and
The surface of the plate electrode layer 205 on the storage electrode 203 is exposed.

Next, boron is introduced only in the vicinity of the exposed surface of the plate electrode layer 205 by ion implantation. afterwards,
By performing heat treatment to activate the ions, the lower layer of the plate electrode layer 205 is formed as the n-type semiconductor layer 205a, and the exposed layer near the surface is formed as the p-type semiconductor layer 205b. Thereby, as shown in FIG. 2A, a plurality of p-type semiconductor regions parallel to the line BB are formed.

The method of this embodiment has the effect that a plurality of semiconductor regions can be formed in one semiconductor wiring layer without adding a lithography step, and the manufacturing cost can be reduced. Have.

In the above, a plurality of p parallel to the line BB
Although the formation of the p-type semiconductor region has been described, the present invention is not limited to this, and it is possible to form a p-type semiconductor region that becomes a bent wiring by arbitrarily selecting the intervals a and b between the storage electrodes. it can. Also, individual production methods such as the above-described boron introduction method are not limited thereto,
The main point of the manufacturing method according to the present embodiment is to define the relationship between the interval between the storage electrodes 203 and the film thickness of the plate electrode layer 205, so that when the second interlayer insulating film 206 is planarized, the plate electrode That is, only a desired portion of the layer 205 is exposed.

Embodiment 3 This embodiment is an example of an embodiment of the semiconductor device according to the third invention, and FIG. 3 is a cross-sectional view of a capacitor provided in the semiconductor device of this embodiment. . The present embodiment is an example in which the first and second embodiments are further developed. The capacitor provided in the semiconductor device of the present embodiment includes a first interlayer insulating film as shown in FIG. Si substrate 3 under first interlayer insulating film 302 through a contact penetrating film 302
01, for example, a storage electrode 303 connected to a source / drain region, a capacitor insulating film 304 formed on the storage electrode 303, and a plate electrode 305 facing the storage electrode 303 via the capacitor insulating film 304. , A second interlayer insulating film 306 formed on the plate electrode 305.

The plate electrode 305 is formed to have a large thickness by using, for example, an epitaxial growth technique, is made of an n-type semiconductor layer, and has a lower layer 305 a functioning as a plate electrode, and a capacitance insulating film of the plate electrode 305. P formed of a p-type semiconductor layer provided on the side opposite to 304
A well 308 is provided. And the p-well 308
On the upper surface, active elements such as an n ⁺ diffusion layer 309 and a MOSTr are formed. A gate electrode 310 is formed in the second interlayer insulating film 306.

In this embodiment, in the conventional capacitance element,
By forming a new device in a region that only functions as a plate electrode in this way, the chip area as a product can be reduced. In the example of FIG. 3, the potential of the plate electrode is set to 1/2 Vcc, the potential of the p well is set to GND, and the potential of the source / drain region of the n-MOSTr is set to the range of GND to Vcc.

Fourth Embodiment In the first to third embodiments, a plate electrode layer of a DRAM having a stacked capacitor structure is described as an example. However, the present invention is not limited to this. The present invention is also applicable to other semiconductor devices having In this case, the wiring layer is formed of a semiconductor wiring layer including a p-type semiconductor layer and an n-type semiconductor layer, and one semiconductor layer can function as a power supply wiring and the other semiconductor layer can function as a signal wiring. .

[0036]

According to the structure of the present invention, a plurality of semiconductor regions separated by a pn junction are formed in one semiconductor wiring layer. This has an effect that it can function as an element. Further, one wiring semiconductor layer can function as a plurality of wirings. As a result, the degree of element integration of the semiconductor device is improved, and there is an effect that the chip area as a product is reduced and the yield is improved. The method of the present invention realizes a preferable method of manufacturing a semiconductor device according to the present invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a capacitor provided in a semiconductor device according to a first embodiment.

FIG. 2A is a plan view of a capacitive element provided in a semiconductor device according to a second embodiment of the present invention, and FIG.
FIG. 2C is a cross-sectional view of a cross section taken along line BB of FIG. 2.

FIG. 3 is a sectional view of a capacitor provided in a semiconductor device according to a third embodiment;

FIG. 4 is a cross-sectional view of a capacitor provided in a conventional semiconductor device.

[Explanation of symbols]

101, 201, 301, 401 Si substrate 102, 202, 302, 402 First interlayer insulating film 103, 203, 303, 403 Storage electrode 104, 204, 304, 404 Capacitive insulating film 105, 205, 305, 405 Plate electrode 105a , 205a, 305a n-type semiconductor lower layer 105b, 205b, 305b p-type semiconductor lower layer 106, 206, 306, 406 second interlayer insulating film 107, 207, 307, 407 upper wiring 308 p-well 309 n ⁺ diffusion layer 310 gate electrode

Claims (10)

[Claims] 1. A semiconductor device comprising: a storage electrode connected to a substrate via a contact; a plate electrode facing the storage electrode; and a capacitance element having a capacitance insulating film interposed between the storage electrode and the plate electrode. A plate electrode having a first conductive type semiconductor layer formed on the capacitor insulating film side and a second conductive type semiconductor layer formed on the side opposite to the capacitor insulating film; A semiconductor device comprising two layers. 2. The semiconductor device according to claim 1, wherein a predetermined region of the semiconductor layer of the second conductivity type of the plate electrode is converted into the first semiconductor layer and connected to the upper wiring via a contact. 13. The semiconductor device according to claim 1. 3. A semiconductor device comprising: a storage electrode connected to a substrate via a contact; a plate electrode facing the storage electrode; and a capacitance element having a capacitance insulating film interposed between the storage electrode and the plate electrode. A plate electrode layer formed on the side of the capacitor insulating film as a semiconductor layer of the first conductivity type; and a capacitor insulating film as a plurality of second conductive type semiconductor layers electrically independent from each other. And a layer formed on the opposite side. 4. A semiconductor device comprising: a storage electrode connected to a substrate via a contact; a plate electrode facing the storage electrode; and a capacitance element having a capacitance insulating film interposed between the storage electrode and the plate electrode. A plate electrode layer formed on the capacitor insulating film side as a semiconductor layer of the first conductivity type, a well of the second conductivity type, and an active element provided in the well of the second conductivity type And a semiconductor layer having at least one of a wiring and a layer formed on the side opposite to the capacitor insulating film. 5. The semiconductor device according to claim 1, wherein the semiconductor layer of the first conductivity type is a layer formed as an n-type semiconductor layer, and the semiconductor layer of the second conductivity type is a layer formed as a p-type semiconductor layer. The semiconductor device according to claim 1, wherein: 6. The semiconductor device according to claim 1, wherein the semiconductor layer of the first conductivity type is a layer formed as a p-type semiconductor layer, and the semiconductor layer of the second conductivity type is a layer formed as an n-type semiconductor layer. The semiconductor device according to claim 1, wherein: 7. A method for manufacturing a semiconductor device provided with a capacitor, comprising: forming a storage electrode when forming the capacitor; forming a capacitor insulating film on the storage electrode; A method for manufacturing a semiconductor device, comprising: a step of forming a silicon film; a step of implanting boron ions only in the vicinity of the surface of a phosphorus-doped polysilicon film; and a step of performing heat treatment to activate ions. . 8. In the step of forming a storage electrode, when forming the storage electrode and patterning the storage electrode, the storage electrode is formed such that a gap in one direction and a gap in a direction intersecting in one direction are different from each other. 8. The method according to claim 7, wherein a plurality of storage electrodes are formed by patterning. 9. A step of forming a phosphorus-doped polysilicon film, wherein the distance from the capacitive insulating film increases as the distance from the capacitive insulating film increases.
9. The method of manufacturing a semiconductor device according to claim 7, wherein a concentration gradient is provided so that the concentration is reduced. 10. A semiconductor device, wherein the wiring layer comprises a semiconductor wiring layer including a p-type semiconductor layer and an n-type semiconductor layer.