JP2720815B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a resistance element.

[0002]

2. Description of the Related Art A dynamic RAM is an example of a semiconductor device having a resistance element. Recent Dynamic RA
Although a self-refresh circuit has come to be built in M, a resistance element using a polycrystalline silicon film is used for a timer of the self-refresh circuit. Hereinafter, a method for manufacturing such a dynamic RAM will be described.

First, as shown in FIG. 3A, a plurality of first active regions are formed by selectively forming a field oxide film 2 having a thickness of 400 mm on the surface of a p-type silicon substrate 1. 101 and a plurality of second active regions 102
Are provided in the memory cell formation region I and the peripheral circuit formation region II, respectively.

Next, after a gate oxide film 3 is formed on the surface of the first and second active regions, the gate electrodes 5M (also serving as word lines), 5P and n-type impurity diffusion layers 4M1, which are source / drain regions, are formed. 4M2 and 4P are formed. Next, after depositing a BPSG film having a thickness of 400 nm and performing a reflow process to form an interlayer insulating film 6, as shown in FIG. 3B, the n-type impurity diffusion layer 4M of the memory cell transistor is formed.
After a contact hole 7 reaching 1 is formed, a 200-nm-thick tungsten silicide film constituting the digit line 8 is deposited and patterned. Next, a 400 nm thick B
After depositing a PSG film and performing a reflow treatment to form an interlayer insulating film 9, as shown in FIG. 4A, a contact hole 11 reaching the n-type impurity diffusion layer 4M2 is formed. After depositing the silicon film, phosphorus is diffused to make it conductive. Next, the lower electrode 12 of the stacked capacitor is formed by using a known lithography technique. Next, a 10-nm-thick silicon nitride film is deposited to form a capacitor insulating film 13. Next, a thickness of 200 nm
After the polysilicon film is deposited, a heat treatment is performed at 850 ° C. for 20 minutes in a POCl ₃ atmosphere to diffuse phosphorus to have conductivity. Next, a cell plate electrode 14-1 (upper electrode) is formed on the memory cell formation region and a film resistor 14-2 is formed on the peripheral circuit formation region, respectively, using a known lithography technique. Next, a BPSG film having a thickness of 400 nm is deposited, a reflow process is performed, an interlayer insulating film 15 is formed as shown in FIG. 4B, and a through hole 16 is provided around the cell plate electrode 14-1 to provide a fixed potential. (Eg Vc
The wiring 17 for supplying c / 2) is formed.

[0005]

In the prior art described above, the film resistor is formed in the same layer as the cell plate electrode. The layer resistance of the film resistor is preferably as high as possible since the mask pattern area required to obtain a predetermined resistance value is small, and the lower limit is at least 100 Ω / μm ² or more. However, the layer resistance of the cell plate electrode in the same layer needs to be 600 Ω / μm ² or less for circuit operation. Also,
The variation of the layer resistance needs to be within ± 20% for the circuit operation. The variation at a layer resistance of 200 Ω / μm ² is ± 20%, and the variation at a layer resistance of 400 Ω / μm ² is ± 50%. The higher the layer resistance, the larger the variation. From the above, the layer resistance of the film resistor is 200
２５０250 Ω / μm ² .

If a non-doped polycrystalline silicon film is used, the variation in the layer resistance is suppressed to within ± 10%,
Although a high resistance of about GΩ / μm ² can be realized, the above-mentioned conventional example cannot be used because the cell plate electrodes of the same layer have a high resistance.

As described above, in the semiconductor device according to the prior art, in order to satisfy the requirements of lowering the resistance of electrodes or wirings such as cell plate electrodes in the same layer and reducing variations in layer resistance, 200 to 250 Ω / μm ^2. Therefore, there is a problem that the area occupied by the film resistor increases.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which can be realized by a film resistor having a high layer resistance, an electrode or wiring having a low layer resistance, and a polycrystalline silicon film.

[0009]

According to a first method of manufacturing a semiconductor device of the present invention, a first surface having a first height from a surface of a semiconductor substrate, and a first surface adjacent to the first surface are formed. A first polycrystalline silicon pattern covering the first surface by depositing and patterning a non-doped polycrystalline silicon film on a base substrate having a second surface having a low second height; and the second surface Coating the second
Forming a film resistor composed of a polycrystalline silicon pattern, and performing an ion implantation after performing a planarization process after depositing an insulating film to utilize a step between the first surface and the second surface. And forming an electrode or a wiring by introducing an impurity only into the first polycrystalline silicon pattern and the second polycrystalline silicon pattern.

In a second method of manufacturing a semiconductor device according to the present invention, a plurality of first active regions and a plurality of second active regions partitioned by selectively forming element isolation regions on a surface portion of a semiconductor substrate are provided. Providing an active region in each of a memory cell forming region and a peripheral circuit forming region; and forming a first transistor and a second transistor having impurity diffusion layers formed in the first active region and the second active region, respectively. Forming an interlayer insulating film having a step between the memory cell forming region and the peripheral circuit forming region after forming;
After forming a contact hole reaching one of the impurity diffusion layers constituting the first transistor in the interlayer insulating film, a conductive film is deposited and patterned to be connected to the first transistor through the contact hole. Forming a lower electrode of the stacked capacitor to form a capacitor insulating film, and depositing and patterning a non-doped polycrystalline silicon film to cover the lower electrode of the capacitor via the capacitor insulating film. Forming a film resistor made of a second polycrystalline silicon pattern for selectively covering the interlayer insulating film on the silicon pattern and the peripheral circuit formation region; and performing a planarization process after depositing the insulating film. Ion implantation is performed from the step using the step of the interlayer insulating film and the height difference due to the presence or absence of the lower electrode. Is that a step of forming the first polycrystalline silicon pattern and the upper electrode of the stacked capacitor by introducing impurities only the former of the second polysilicon pattern.

The planarization is preferably performed by a CMP method.

Further, a silicon oxide film can be deposited as an insulating film, and phosphorus can be ion-implanted as an impurity.

[0013]

A first polycrystalline silicon pattern and a second polycrystalline silicon pattern are provided on an undersubstrate having a step, and an insulating film is deposited and planarized before ion implantation. It acts as a mask for ion implantation for the silicon film pattern.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A, 1B, 2A, and 2B are longitudinal sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a plurality of first active regions are formed by selectively forming a field oxide film 2 having a thickness of 400 nm on the surface of a p-type silicon substrate 1. 101 and a plurality of second active regions 102
Are provided in the memory cell formation region I and the peripheral circuit formation region II, respectively. Next, after the gate oxide film 3 is formed on the surfaces of the first and second active regions, the gate electrodes 5M (also serving as word lines), 5P and the n-type impurity diffusion layers 4M1, 4M2, 4P serving as source / drain regions. To form Next, a BPSG film having a thickness of 400 nm is deposited and subjected to a reflow process to form an interlayer insulating film 6, and then, as shown in FIG. 1B, the n-type impurity diffusion layer 4 of the memory cell transistor is formed.
After the contact hole 7 reaching M1 is provided, a 200 nm thick tungsten silicide film constituting the digit line 8 is deposited and patterned. At this time, necessary wiring may be formed of a tungsten silicide film also in the peripheral circuit formation region. Next, a BPSG film having a thickness of 400 nm is deposited and subjected to a reflow process to form an interlayer insulating film 9.
Alternatively, it is more preferable to reduce the thickness by depositing a BPSG film more thickly and performing a reflow treatment and then performing etching to reduce the thickness of the interlayer insulating film 9 with less surface irregularities. Next, as shown in FIG. 2A, after forming a contact hole 11 reaching the n-type impurity diffusion layer 4M2, a 400 nm-thick crystalline silicon film is deposited, and then phosphorus is diffused to have conductivity. Let Next, the lower electrode 12 of the stacked capacitor is formed by patterning using a known lithography technique. Next, a 10-nm-thick silicon nitride film is deposited to form a capacitor insulating film 13. Next, after depositing a non-doped polycrystalline film having a thickness of 200 nm, the first polycrystalline silicon pattern 14-1A and the second polycrystalline silicon for forming a cell plate electrode by patterning using a well-known lithography technique. A film resistor composed of the pattern 14-2A is formed. At this time, the first polycrystalline silicon pattern 14
-1A and the height difference h between the film resistor (14-2A) are 800
nm. Note that this step is due to the fact that the lower electrode exists only in the memory cell formation region, and the underlying wiring pattern such as the gate electrode and the tungsten silicide film is denser in the memory cell formation region than in the peripheral circuit formation region. It is caused by things.

Next, for example, 1 to 1
After depositing a silicon oxide film 15A having a thickness of 2 μm,
The thickness is 30 on the first polycrystalline silicon pattern 14-1A by the MP method (chemical mechanical polishing method).
Etchback is performed so as to have a thickness of 0 nm, and an interlayer insulating film 15Aa is formed as shown in FIG. At this time, since the interlayer insulating film 15Aa is almost completely flattened, it is about 800 nm thicker on the film resistor (14-2A) than on the first polycrystalline silicon pattern 14-1A.

Next, phosphorus is applied at 360 keV and 1 × 10 ¹⁴ cm.
Ion implantation with ^-2 . At this time, the range of phosphorus = 0.3
Since 74 μm and range dispersion = 0.084 μm, phosphorus is introduced only into the first polycrystalline silicon film pattern 14-1A, and is not introduced into the film resistor 12-2A. Then 850
A heat treatment at 20 ° C. for 20 minutes is performed to activate phosphorus, thereby completing the formation of the cell plate electrode 14-1Aa (lower electrode). Next, a through-hole is provided around the cell plate electrode 14-1Aa to provide a fixed potential (for example, Vcc /
The wiring 17 for supplying 2) is formed. At this time,
A wiring connecting the film resistor 14-2A to a transistor or the like can be formed at the same time.

The spacing between the lower electrodes 12 is set to about 350 nm in this embodiment so as to be almost completely filled with the non-doped polycrystalline silicon film. Can be advantageously formed.

Since the interlayer insulating film is thicker on the peripheral circuit formation region by the thickness of the silicon oxide film corresponding to the step of the underlying substrate on which the non-doped polycrystalline silicon film is deposited, the first polysilicon film on the memory cell formation region Ions can be implanted only into the crystalline silicon pattern. This difference in thickness may be larger than the range dispersion of the ion implantation.

In this embodiment, the CMP method is used as the flattening process. However, it is needless to say that other methods such as SOG may be used.

[0021]

As described above, according to the present invention, the difference in surface height between a memory cell formation region and a peripheral circuit formation region in a dynamic RAM is reduced, as in the case of an interlayer insulating film in which a capacitor lower electrode is formed. A non-doped polycrystalline silicon film is deposited on a certain base substrate and patterned to form a first surface on a first surface such as the above-mentioned memory cell forming region having a large surface height and a second surface on a peripheral circuit forming region or the like. After forming the second polycrystalline silicon pattern, depositing an insulating film, performing a planarization process, and then performing ion implantation, impurities can be introduced only into the first polycrystalline silicon pattern. An electrode such as a cell plate electrode or a wiring can be formed with good conductivity, and a film resistor made of a non-doped polycrystalline silicon film can be formed. Therefore, a high-resistance film resistor of about 1 GΩ / μm ² can be realized with a small layer resistance variation within ± 10%, and the occupied area can be reduced. At this time, an electrode or a wiring made of a polycrystalline silicon film deposited in the same step can have a low resistance without increasing the number of alignments.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams for explaining an embodiment of the present invention.
It is a process order sectional view divided and shown to (b).

FIG. 2 is a cross-sectional view in the order of steps, which is separated from (a) and (b) following FIG. 1;

FIGS. 3A and 3B are cross-sectional views in the order of steps, which are separately illustrated in FIGS.

FIG. 4 is a cross-sectional view in the order of steps, which is separated from (a) and (b) shown after FIG. 3;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type silicon substrate 2 field oxide film (element isolation region) 3 gate oxide film 4M1, 4M2, 4P n-type impurity diffusion layer 5M gate electrode (of memory cell transistor also serving as word line) 5P gate electrode (for peripheral circuit) 6 Interlayer insulating film 7 Contact hole 8 Digit line 9 Interlayer insulating film 10 Interlayer insulating film 11 Contact hole 12 Lower electrode 13 Capacitor insulating film 14-1, 14-1Aa Cell plate electrode 14-1A First polycrystalline Silicon pattern 14-2 Film resistor 14-2A Second polycrystalline silicon pattern 15, 15Aa Interlayer insulating film 15A Silicon oxide film 16 Through hole 17 Wiring 101 First active region 102 Second active region I Memory cell formation region II Peripheral circuit formation area

Claims (4)

(57) [Claims] 1. An undersubstrate having a first surface having a first height from a surface of a semiconductor substrate and a second surface adjacent to the first surface and having a second height lower than the first surface. Depositing and patterning a non-doped polycrystalline silicon film to form a film resistor comprising a first polycrystalline silicon pattern covering the first surface and a second polycrystalline silicon pattern covering the second surface Performing a planarization process after depositing an insulating film, performing ion implantation, and utilizing the step between the first surface and the second surface to form the first polysilicon pattern and the second polysilicon pattern. Forming an electrode or a wiring by introducing an impurity into only the former of the two polycrystalline silicon patterns. 2. A plurality of first active regions and a plurality of second active regions partitioned by selectively forming element isolation regions on a surface portion of a semiconductor substrate to form a memory cell formation region and a peripheral circuit formation, respectively. Forming a first transistor and a second transistor having an impurity diffusion layer respectively formed in the first active region and the second active region, and forming the first transistor and the second transistor on the memory cell forming region and the peripheral circuit. Forming an interlayer insulating film having a step between itself and a formation region, forming a contact hole reaching one of the impurity diffusion layers constituting the first transistor in the interlayer insulating film, and then depositing a conductive film. Forming a lower electrode of a stacked capacitor connected to the first transistor through the contact hole by patterning; forming a capacitor insulating film; Forming a first polycrystalline silicon pattern for covering the capacitor lower electrode via the capacitor insulating film by depositing and patterning a non-doped polycrystalline silicon film and the interlayer insulating film on the peripheral circuit formation region. Second to selectively coat the membrane
A step of forming a film resistor made of a polycrystalline silicon pattern, and performing an ion implantation after performing a planarization process after depositing an insulating film, and utilizing a step of the interlayer insulating film and a height difference due to the presence or absence of a lower electrode. Forming an upper electrode of a stacked capacitor by introducing impurities only into the first polycrystalline silicon pattern and the second polycrystalline silicon pattern. . 3. The method for manufacturing a semiconductor device according to claim 1, wherein the planarization process is a CMP method. 4. A silicon oxide film is deposited as an insulating film,
4. The ion implantation of phosphorus as an impurity.
The manufacturing method of the semiconductor device described in the above.