JP2000208435A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with good high-frequency operational characteristics and power characteristics, by reducing contact resistance of an ohmic electrode on a gallium nitride-based semiconductor. SOLUTION: A metallic layer 5 containing aluminum is formed on an active layer 4 made of gallium nitride-based semiconductor. Then, the metallic layer 5 is treated in a rapid heating and cooling unit with a carbon-graphite heater and annealed under hydrogen atmosphere for a minute at 600 deg.C to make the metallic layer 5 and the active layer 4 in an affinity state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an ohmic electrode on a gallium nitride based semiconductor.

[0002]

2. Description of the Related Art GaN, AlGaN, InGaN, InGaN
Gallium nitride-based semiconductors such as AlGaN have direct transitions and can have a band gap from 1.95 eV to 6 eV, and thus are promising as materials for light-emitting devices such as laser diodes.

[0003] Further, GaN has high dielectric breakdown field strength, thermal conductivity, and electron saturation speed, and is therefore promising as a power device material for high frequencies. In particular, AlGaN / Ga
Since the N heterojunction structure has an electric field intensity of 1 × 10 ⁵ V / cm, which is twice or more the electron velocity of GaAs, high frequency operation can be expected by miniaturization of power devices.

[0004] These gallium nitride based semiconductor materials are made of Si.
Doping with an n-type dopant such as GaN or Ge exhibits n-type characteristics, and a field-effect transistor (hereinafter referred to as “FE
T ”). In a FET, a gate electrode and a source electrode which is an ohmic electrode are formed on a gallium nitride based semiconductor layer. Here, since the parasitic resistance between the source and the gate greatly affects the high-frequency characteristics of the FET, how to reduce the source resistance is a major issue. In order to reduce the source resistance, it is particularly important to reduce the contact resistance of the ohmic electrode provided on the gallium nitride based semiconductor.

[0005]

However, gallium nitride-based semiconductors have poor processability and are thermally stable, so that the fabrication process is difficult. For this reason, various ohmic electrode materials have been studied, but in reality, the contact resistance of the ohmic electrode has not been sufficiently reduced. This is considered to be due to the oxidation of Al during annealing.

An object of the present invention is to provide a semiconductor device having excellent high-frequency operation characteristics and power characteristics by reducing the contact resistance of an ohmic electrode provided on a gallium nitride-based semiconductor.

[0007]

According to a method of manufacturing a semiconductor device of the present invention, a metal layer containing aluminum is formed on a gallium nitride-based semiconductor layer, and the metal layer is annealed in a gas containing hydrogen. .

In the present invention, the material of the metal layer formed on the gallium nitride based semiconductor layer is aluminum or an alloy containing aluminum. For example, an alloy of Al and one metal selected from Cr or Ni or Ti or In can be used, and in particular, Ti-Al, Ni-A
One alloy is desirable. After forming a metal layer containing aluminum over the gallium nitride-based semiconductor layer, the metal layer is annealed in a gas containing hydrogen. Thereby, the gallium nitride based semiconductor layer and the metal layer fit together, and the metal layer can be brought into ohmic contact with the gallium nitride based semiconductor layer,
Further, since hydrogen in the gas suppresses oxidation of aluminum, ohmic contact with lower resistance can be achieved.

The temperature for annealing the metal layer is 500
It is desirable that the temperature is not less than ° C.

The gas used for annealing the metal layer contains an inert gas such as argon or nitrogen in addition to hydrogen, and its content is preferably 70% or less.

[0011]

(Embodiment 1) Next, a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings.

FIGS. 1A to 1E are cross-sectional views showing the steps of the FET according to the first embodiment of the present invention.

First, as shown in FIG.
20 nm thick Ga on the sapphire substrate 1 using the D method.
Buffer layer 2 made of N, non-doped GaN layer 3 having a thickness of 2 μm, and Si-doped carrier concentration of 7 × 10
An active layer 4 having a thickness of 0.1 μm and made of n-type GaN, which is a gallium nitride based semiconductor layer of ¹⁷ cm ⁻³ , is sequentially formed.

Next, as shown in FIG. 1B, the active layer 4 is removed by mesa etching except for the portion where the FET is to be formed.

Next, as shown in FIG. 1C, two metal layers 5 are formed on the remaining active layer 4 by a lift-off method. This metal layer 5 is composed of a Ti film 5a having a thickness of 20 nm and an Al film 5b having a thickness of 200 nm.

Thereafter, as shown in FIG. 1 (d), the metal layer 5 is activated by annealing at 600 ° C. for 1 minute in a hydrogen atmosphere in a rapid thermal quenching annealing apparatus using a carbon graphite heater. Adapt to layer 4. As a result, the metal layer 5 is in ohmic contact with the active layer 4 with a very low resistance.

Finally, a 50 nm thick Pt layer (not shown), a 50 nm thick Ti layer (not shown), and a 200 nm thick
A gate electrode 6 formed by sequentially laminating an Au layer (not shown) with a thickness of nm is formed as shown in FIG. 1E by a lift-off method to complete the FET.

FIG. 2 shows a current-voltage characteristic between two metal layers 5 in ohmic contact with the active layer 4. As is clear from FIG. 2, the current-voltage characteristics show a straight line, and it is understood that good ohmic characteristics are obtained. Also, T
The contact resistivity determined by the LM method is 3 × 10 ⁻⁶ Ωc
m ^2, which is one digit lower than the contact resistance value of 3 × 10 ⁻⁵ Ωcm ² in the conventional semiconductor device.

It is considered that the reason why such low contact resistance can be realized is that aluminum in the metal layer 5 is hardly oxidized by annealing the metal layer 5 in a hydrogen atmosphere.

FIG. 3 shows the relationship between the content of argon contained in the gas used for annealing the metal layer 5 and the contact resistivity. As is clear from FIG. 3, the contact resistivity increases as the argon content increases. In particular, it rapidly increases at 70% or more, and it is understood that the argon content must be 70% or less in order to obtain a good ohmic contact.

FIG. 4 shows the relationship between the annealing temperature and the contact resistivity. Annealing temperature is 600
The lowest contact low efficiency was obtained at ℃. At 450 ° C., the current-voltage characteristics were not linear and no ohmic contact was obtained. When the annealing temperature exceeds 800 ° C., although ohmic contact is obtained, the reaction between the active layer 4 and the metal layer 5 is large, and the surface of the metal layer 5 becomes uneven. Annealing temperature 500 ℃
In the range of from 800 ° C. to 800 ° C., the contact resistivity was lower than that of the conventional semiconductor device.

Second Embodiment Next, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 5A to 5E are process sectional views of an AlGaN / GaN heterojunction field effect transistor (hereinafter, referred to as "HFET") according to the second embodiment of the present invention.

First, as shown in FIG.
20 nm thick Ga on the sapphire substrate 1 using the D method.
Buffer layer 2 made of N, a non-doped GaN layer 3 having a thickness of 2 μm, and a Si-doped carrier concentration of 8 × 10
^A gallium nitride based semiconductor layer of ¹⁷ cm ^-3 having a thickness of 50 nm
And an active layer 4 made of n-type Al _0.15 Ga _0.85 N.

Next, as shown in FIG.
The active layer 4 is removed by mesa etching except for the portion where the pattern is formed.

Next, as shown in FIG. 5C, metal layers 5 are formed at two places on the remaining active layer 4 by a lift-off method. This metal layer 5 is composed of a Ti film 5a having a thickness of 20 nm and an Al film 5b having a thickness of 200 nm.

Then, as shown in FIG. 5D, the metal layer 5 is activated by annealing at 800 ° C. for 1 minute in a hydrogen atmosphere in a rapid thermal quenching annealing apparatus using a carbon graphite heater. Adapt to layer 4. As a result, the metal layer 5 is in ohmic contact with the active layer 4 with a very low resistance.

Finally, a 50 nm thick Pt layer (not shown), a 50 nm thick Ti layer (not shown) and a 200 nm thick
The gate electrode 6 is formed by sequentially laminating an Au layer (not shown) of nm in thickness as shown in FIG. 5E by a lift-off method to complete the HFET.

FIG. 6 shows a current-voltage characteristic between two metal layers 5 in ohmic contact with the active layer 4. As is clear from FIG. 6, the current-voltage characteristics show a straight line, and it is understood that good ohmic characteristics are obtained. Also, T
The contact resistivity determined by the LM method is 3 × 10 ⁻⁶ Ωc
m ^2, which is one digit lower than the contact resistance value of 3 × 10 ⁻⁵ Ωcm ² in the conventional semiconductor device.

It is considered that the reason why such low contact resistance can be realized is that aluminum in the metal layer 5 is hardly oxidized by annealing the metal layer 5 in a hydrogen atmosphere.

FIG. 7 shows the relationship between the annealing temperature and the contact resistivity. Annealing temperature 800
The lowest contact efficiency at ℃ was obtained. When the temperature is lower than 500 ° C., the current-voltage characteristics are not linear and an ohmic contact was not obtained. When the annealing temperature is 900
When the temperature exceeds ° C, ohmic contact is obtained, but the reaction between the active layer 4 and the metal layer 5 is large, and the surface of the metal layer 5 becomes uneven. Annealing temperature 500 ℃
In the range from to 900 ° C., the contact resistivity was lower than that of the conventional semiconductor device.

As described above, although the optimum annealing temperature varies depending on the mixing ratio of the n-type gallium nitride based semiconductor material forming the active layer 4, if the temperature is 500 ° C. or more,
It can be seen that good ohmic contact resistance can be realized by annealing in a hydrogen atmosphere. In addition, as an annealing atmosphere, even if an inert gas such as argon is mixed in addition to hydrogen alone, a contact resistance with no problem in device characteristics can be realized as long as the content of argon is 70% or less.

In the embodiment of the present invention, the active layer 4
Has been described as GaN or AlGaN,
The present invention can be similarly implemented by using nGaN or InAlGaN.

Although the doping concentration of the n-type impurity in the active layer 4 has been described as 7 × 10 ¹⁷ cm ⁻³ to 8 × 10 ¹⁷ cm ⁻³ , if the doping concentration is higher, a lower contact resistance can be realized. . For example, n-type GaN
Doping concentration of the active layer composed of 1.8 × 10 ¹⁸
When a sample of cm ^-3 was used, the other conditions were the same as in Embodiment 1, and a lower contact resistivity of 1.2 × 10 ^-6 Ωcm ² was obtained.

Although the case where a rapid quenching annealing apparatus using a carbon graphite heater is used as the apparatus used for annealing has been described, the present invention can be similarly applied to a lamp annealing apparatus or an electric furnace annealing apparatus.

In the embodiments of the present invention, the steps of fabricating the FET and the HFET have been described. However, the present invention has the same effect even when an n-type ohmic electrode of a laser diode or a light emitting diode is formed.

[0037]

As described above, a metal layer containing aluminum is formed on a gallium nitride-based semiconductor layer, and this metal layer is annealed in a gas containing hydrogen to form a metal layer on the gallium nitride-based semiconductor layer. Ohmic resistance of the substrate is reduced. As a result, the source parasitic resistance is reduced, and the high frequency characteristics and power characteristics of the gallium nitride based semiconductor device are improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing current-voltage characteristics of the semiconductor device.

FIG. 3 is a view showing a relationship between an argon content and a contact resistivity in the method for manufacturing the semiconductor device.

FIG. 4 is a view showing a relationship between an annealing temperature and a contact resistivity in the method for manufacturing the semiconductor device.

FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing current-voltage characteristics of the semiconductor device.

FIG. 7 is a view showing a relationship between an annealing temperature and a contact resistivity in the method for manufacturing the semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 Buffer layer 3 Non-doped GaN layer 4 Active layer 5 Metal layer 6 Gate electrode

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Hiroyuki Masato, Inventor 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation (72) Inventor Kaoru Inoue 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics F-term (reference) in Industrial Co., Ltd. 4M104 AA04 BB05 BB06 BB14 CC01 CC05 DD79 DD80 GG04 GG12 HH15 5F041 AA21 CA34 CA40 CA73 CA83 CA92 CA98 5F102 FA03 GB01 GC01 GD01 GJ10 GK04 GL04 GT03 HC21

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: forming a metal layer containing aluminum on a gallium nitride-based semiconductor layer; and annealing the metal layer in a gas containing hydrogen. 2. The method according to claim 1, wherein said metal layer has a titanium layer and an aluminum layer. 3. The method according to claim 1, wherein the gallium nitride based semiconductor layer is formed of n-type Ga.
3. The method according to claim 1, wherein the metal layer is made of N, and the metal layer is annealed at 500 ° C. or more and 800 ° C. or less. 4. 4. The method according to claim 1, wherein the gallium nitride based semiconductor layer is formed of n-type Al.
GaN, and the metal layer is at least 500 ° C. and 900 ° C.
3. The method for manufacturing a semiconductor device according to claim 1, wherein annealing is performed below. 5. The gas containing hydrogen is 70% of the total gas.
% Or less of inert gas.
A method of manufacturing a semiconductor device according to claim 4.