JP2000207291A - Method for diagnosing memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for diagnosing the fault of a memory element by referring to a memory address where single-bit error occurrence is recorded and deciding that a control circuit in a memory element has gone out of order, when the memory addresses for single-bit errors generated in a prescribed time are more than a prescribed number. SOLUTION: When the type of the latest error in an error log file is '01', a memory error file is referred to (30). The memory address of the last error log in the memory error file is compared with the memory address of the latest error (40), and when the addresses do not match each other, the current number of memory addresses is compared with a previously set prescribed value (60). When prescribed value is exceeded, it is decided that the control circuit of the memory element is out of order (70) on condition that the generation time difference between the oldest error log and the latest error log in the memory error file is within the previously set prescribed time, thereby outputting an alarm (80). Then all the error logs in the memory error file are erased (90).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a main memory and an ECC.
The present invention relates to a computer having a correction mechanism and a method of diagnosing a memory.

[0002]

2. Description of the Related Art Conventionally, highly reliable industrial computers have been used in industrial fields such as electric power, transportation, and the public. Such computers must be devised so that no failure occurs, and even if a failure occurs, if the failure is minor, it must have a function to continue processing and perform preventive maintenance before a severe failure occurs. is there. In order to respond to such a request, for example, in the case of a memory single-bit error, conventionally, data read by an ECC correction mechanism is corrected, and the corrected data is written to a memory. It had a diagnostic means for determining a failure.

[0003] However, an additional mechanism for writing the corrected data is required, and the write operation causes a reduction in performance.

In recent years, industrial computers have been required to have high performance in addition to reliability. In many cases, general-purpose high-performance processors are used. These processors have a standard memory interface. However, in many cases, the above-mentioned additional mechanism is not provided, and the conventional diagnostic method cannot be adopted because performance is emphasized.

Further, Japanese Patent Application Laid-Open Nos. Hei 6-161796 and
As described in JP-A-133899, there is known a method of counting the number of occurrences of a memory ECC error by a diagnostic program without a special additional mechanism and monitoring a threshold value. Has not been reached.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide an EC
It is an object of the present invention to provide a method for diagnosing a memory element failure in a general-purpose computer having no special mechanism such as an additional mechanism for writing C-corrected data.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is to store a single bit error occurrence in a time-series manner, a storage means which does not volatilize even when the power is restored, and a time-series in which the occurrence of a power recovery is performed. Means for temporarily storing data, means for monitoring the occurrence of single-bit errors and power recovery, addresses at which single-bit errors have occurred, memory addresses for errors that have occurred in the past, and single-bit errors in memory depending on whether power recovery has occurred. A general-purpose computer having means for judging whether it is due to an external factor such as α-rays or the like, and having no special mechanism such as an additional mechanism for writing ECC-corrected data by the method according to claim 1. This makes it possible to diagnose a memory element failure.

[0008]

FIG. 1 shows a computer to which the present invention is applied. The computer includes a processor 10, a system controller 20 for controlling access from the processor, a main memory 30, and an input / output controller 4 for controlling input / output devices.
0, a processor bus 50, a memory bus 60, and a system bus 70 for connecting the system controller 20 to the processor 10, the main memory 30, and the input / output controller 40, respectively. Access to the main memory 30 and the input / output controller 40 from the processor 10 is performed via the system controller 20.

FIG. 2 shows the configuration of the system controller 20 and the main memory 30.

The system controller 20 and the main memory 30
Are connected by a memory bus 60, which comprises a column address valid signal 61, a row address valid signal 62, a read / write signal 63, a row and column address signal 64, and a data signal 65.

The system controller 20 includes a control circuit 21 for generating a column address valid signal 61, a row address valid signal 62, and a read / write signal 63 from an address signal 51 of the processor bus, an address buffer 22, and an ECC from a data signal 52 of the processor bus. Generate code E
CC encoding circuit 24, write data buffer 23,
E for detecting a single bit error by ECC when reading data from the data signal 65 of the memory bus
It comprises a CC error detecting circuit 25, an ECC decoding circuit 26 for decoding an ECC code when a single bit error occurs and correcting data, and a read data buffer 27.

The main memory 30 comprises a memory element such as a dynamic RAM.

Next, the operation of the system controller 20 and the main memory 30 will be described. Figure 1
Is performed by outputting the write destination memory address and data to the processor bus address signal 51 and data signal 52. The address is converted by the control circuit 21 into a column address valid signal 61 and a row address valid signal 62 for specifying a memory element, and the read / write signal 63 goes to L level representing write.
The data is added with an ECC code by the ECC encoding circuit 24, temporarily stored in the write data buffer 23, and stored in the main memory 30 in accordance with the determination of the column address valid signal 61, the row address valid signal 62, and the read / write signal 63. Written.

At the time of reading, a read / write signal 6
3 is at the H level indicating read, and the data output to the data signal 65 of the memory bus is checked by the ECC error detection circuit 25. If there is no error, the data is read as it is. If there is an error, the data is output by the ECC decode circuit 26. The data is corrected, held in the data buffer 27, and read by the processor 10.

As described above, when a memory single-bit error occurs, the system controller 20 corrects only read data by the ECC correction mechanism, and does not correct data in the main memory.

FIG. 3 shows the structure of programs and data operating on the computer shown in FIG. The error occurrence monitoring program monitors the occurrence of a single-bit error in the memory and the restoration of power, and when such an event occurs, records auxiliary information such as an occurrence time, an error type, and a memory address in the error log file 300. The error log file 300 is configured in a nonvolatile storage device, and in the case of the present embodiment, is a fixed magnetic disk device.

The memory diagnostic program 200 refers to the error log file 300, and if there is a single-bit error log, temporarily records it in the memory error file 400. The memory error file 400 is similarly configured in a nonvolatile storage device, and in the case of the present embodiment, is a fixed magnetic disk device.

FIG. 4 shows the recording format of the error log file 300. The error information per case is composed of an error occurrence time, an error number assigned in the order of the error occurrence time, an error type, and auxiliary information on the error.
Here, the error type '01' indicates a memory single bit error, and '02' indicates a power recovery log.

FIG. 5 shows a recording format of the memory error file 400. The error information for one case is the error occurrence time, the error number assigned in the order of the error occurrence time,
The memory is configured by a memory address at which a single bit error has occurred. Here, the memory address is a physical address.

FIG. 6 shows a flowchart of the memory diagnosis program. The memory monitoring program is always started while the computer is running, and refers to the error log file (step 1).
0), the occurrence of a single bit error is identified by the error type (step 20). In step 20, the error type of the latest error in the error log file is "0".
If it is not "1", the process returns to Step 10, and if it is "01", the memory error file is referred to (Step 30).

Next, the process proceeds to step 40, where the memory address of the previous error log of the memory error file is compared with the memory address of the latest error. If the addresses do not match, the process proceeds to step 60. In step 60, the current number of memory addresses is compared with a preset specified value.

If the value is less than the specified value, step 120 is executed.
If the difference exceeds the specified value, if the time difference between the oldest error log in the memory error file and the latest error log in the memory error file is within a predetermined time set in step 70,
It is determined that the control circuit of the memory element constituting the main memory has failed, and an alarm is output in step 80. Thereafter, in step 90, all error logs in the memory error file are deleted. If the occurrence time difference exceeds the specified time in step 70, the process proceeds to step 120, and the latest error log is added to the memory error file.

If the memory address of the last error log matches the memory address of the latest error at step 40, the process proceeds to step 100, where the error log file is referred to again and there is no power recovery log before the latest memory error log. Is confirmed (step 110). If the error type "02" is confirmed in step 110, it is determined that the memory cell specified by the memory address of the memory element constituting the main memory has failed, and the process proceeds to step 80 to output an alarm. If the power recovery log cannot be confirmed in step 110, the process proceeds to step 120.

FIG. 7 shows an embodiment in which the prescribed value in step 60 of FIG. 6 is set to three times and the prescribed time in step 70 is set to 5 seconds. The flow in each case will be described with reference to FIG.

1) Cases of FIGS. 4 and 5 In FIG. 4, the processing from the time when the error log of No. 1 is recorded first refers to the error log file in step 10 of FIG. Step 30 because the error type of the error log of .1 is '01'
Proceed to. Here, the memory error file (FIG. 5) is referred to and compared with the previous log No. 2 (step 4).
0). As a result, since the addresses do not match, the routine proceeds to step 60, where the address is compared with the specified value. In step 70, the error log N
The occurrence time from o.1 to No.3 is compared with the specified time of 5 seconds, and since it exceeds this, it is not determined that the memory cell has failed, and the process proceeds to step 90 to erase the memory error file. .

2) Cases of FIGS. 4A and 5A When No. 1 in FIG. 5A is recorded, step 60 in FIG.
And the occurrence time from error log No. 1 to No. 3 is within 5 seconds of the specified time, it is determined that the memory cell has failed. Output.

2) Cases of FIGS. 4B and 5B At the time when No. 1 in FIG. 5B is recorded, step 40 in FIG.
Since the address matches the address of No. 2 in the previous log, the process proceeds to step 100. In step 100, the error log is referred to, and since there is a power recovery log in No. 2 in FIG. 4B, it is determined that the memory cell has failed, and the process proceeds from step 110 to step 80 to output an alarm.

[0028]

According to the present invention, storage means for storing the occurrence of a single bit error in a time series and not volatilizing even after power recovery, means for storing the occurrence of a power recovery in a time series, a single bit error and Means for monitoring the occurrence of power recovery, the address where a single-bit error occurred, the memory address of an error that occurred in the past, and whether a single-bit error in the memory was caused by an element failure depending on whether or not power recovery occurred. ECC has a means to determine whether
A general-purpose computer having no special mechanism such as an additional mechanism for writing corrected data can diagnose a memory element failure.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a computer according to the present invention.

FIG. 2 is a diagram showing a configuration of a system controller and a main memory.

FIG. 3 is a diagram showing a configuration of a program and data.

FIG. 4 is a diagram showing a format of an error log file.

FIG. 5 is a view showing a format of a memory error file.

FIG. 6 is a diagram showing a flow of a diagnostic program.

FIG. 7 is a diagram showing a flow of a diagnostic program.

[Explanation of symbols]

10: Processor, 20: System controller, 30
... main memory, 40 ... input / output controller, 100 ... error occurrence monitoring program, 200 ... memory diagnostic program.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B018 GA03 GA05 GA07 HA14 HA25 HA31 JA22 KA01 MA01 NA02 QA13 RA01 RA03 RA04 RA11 5B025 AD13 AE09 5B042 GA33 JJ17 JJ31 MA08

Claims (2)

[Claims] A processor, a system controller, an input / output controller, a main memory, and a processor bus, a memory bus, and a system bus for connecting the main memory to each other, wherein a single-bit error occurs when reading data from the main memory. ECC (Error Checking and Corr
ecting feature) A computer that corrects only the read data by the correction mechanism and does not correct the data in the main memory, stores the occurrence of single-bit errors in chronological order, and a storage means that does not volatilize even after power recovery. It has means for storing in chronological order, means for monitoring the occurrence of a single-bit error, and means for diagnosing memory. The means for diagnosing memory refers to the memory address recorded by the storage means for single-bit error occurrence. If the memory address of the single-bit error that occurred within the specified time is equal to or greater than the specified number, it is determined that the control circuit in the memory element has failed, a replacement request is made, and the memory of the single-bit error that occurred within the specified time is If the number of addresses is less than the specified number, it is judged that it is due to external factors such as α rays, and no exchange request is made. Diagnostic method of the memory device to be. 2. A computer according to claim 1, wherein a storage means for storing the occurrence of a single-bit error in time series and which does not volatilize even after power recovery, a means for storing the occurrence of power recovery in time series, It has means for monitoring the occurrence of bit errors and power recovery, and means for diagnosing the memory. The means for diagnosing the memory refers to the memory address recorded by the storage means for single bit error occurrence, and
If there is a power recovery between the single bit errors and the memory addresses match, if the memory address of the single bit error that occurred within the specified time is more than the specified number, the specific memory in the memory element A method for diagnosing a memory device, comprising determining that a cell failure has occurred, making a replacement request, and if there is no power recovery, determining that an external factor such as α-rays has occurred, and not making a replacement request.