JP2000194326A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device by which the optimum sampling timing is obtained for an arbitrary specific portion of a specified display area or an entire area. SOLUTION: A dot clock reproducing circuit 102 generates dot clock signals Φsynchronized with horizontal synchronizing signals Hsy of inputted picture signals Sv and having the frequency that is an integer multiple of the signal Hsy. A control circuit 104 counts the signals Φ and controls the amount of the delay of the signals Φ in accordance with vertical and horizontal position values outputted from vertical and horizontal counters and a liquid crystal display module 105 displays a picture by the outputted signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a phase adjusting means for performing dynamic phase adjustment.

[0002]

[Prior art]

As shown in FIG. 4, a conventional liquid crystal display device has an RGB video signal Sv and a horizontal and vertical synchronization signal Hs.
An information processing device 401 for outputting y and Vsy, and horizontal and vertical synchronizing signals Hsy and Vsy are supplied, and a dot clock signal φ that is synchronized with the horizontal synchronizing signal Hsy and has a frequency that is an integral multiple of the horizontal synchronizing signal Hsy is generated and output. And a control circuit 4 for outputting one selected switch control data Ds of the dot clock signal φ.
04 and a delay switching circuit 403 that delays the dot clock signal φ by the delay amount selected by the switching control data Ds and outputs it as a delayed dot clock signal φd.

As shown in FIG. 5, a delay switching circuit 403 is supplied with a dot clock signal φ from a dot clock reproduction circuit 402, and delays the dot clock signal φ to output a delayed clock signal 501 in parallel. ,
The switching control data Ds is supplied, and a delay clock switching circuit 502 selectively outputs one of a plurality of delay dot clock signals as a delay dot clock signal φd.

As shown in FIGS. 4 and 5, the operation of the conventional liquid crystal display device is such that the horizontal synchronizing signal Hsy output from the information processing device 401 is an integral multiple so that one pixel of the video signal has one cycle. An integer multiple value generated and set by the dot clock reproducing circuit 402 uses a preset value determined from the input horizontal synchronization frequency and vertical synchronization frequency or adjusts and selects the value by the user. The set value is set by the control circuit 404, but the output is performed in a state where the phases of the video signal and the dot clock are shifted due to differences in AC power supply voltage, environmental temperature, etc., even when the type of the information processing device or the like is different. Because the phase of the video signal and the dot clock are shifted even at the power supply voltage of the liquid crystal display device or the environmental temperature, the video signal is displayed on the liquid crystal display module screen. The no longer be correctly sampled, if the horizontal image stabilizer in dot level (distortion) occurs, the control circuit 404 the delay time which is preset in advance, or the delay time selected by the user,
By setting the delay switching circuit 403, an optimal display image can be obtained.

[0006]

However, the conventional liquid crystal display device reproduces an integer multiple of the dot clock signal from the horizontal synchronizing signal using the PLL circuit. Indicates that the PLL circuit is in a free-run state during the synchronization period. At this time, during the free-run period, when the dot clock oscillation frequency of the PLL circuit gradually increases or decreases due to the characteristics inherent to the PLL circuit, the reproduced signal is reproduced. When a video signal is displayed by using a dot clock signal, the phase of the video signal and the sampling dot clock are shifted in the first half, the second half, or the middle of the horizontal scanning period, and as a result, the displayed video is different within the horizontal display period. There were challenges.

Further, in the conventional liquid crystal display device, a dot clock signal is reproduced from a horizontal synchronizing signal by using a PLL circuit. Therefore, a horizontal synchronizing signal serving as a reference for reproducing the dot clock signal is like a composite signal. If the horizontal synchronization signal is not supplied during the vertical synchronization period, the horizontal synchronization signal pulse is lost during the vertical synchronization period of the composite signal.
This means that the reference frequency itself to be compared with the oscillation frequency of the PLL circuit is not input, and when the PLL circuit free-runs, the dot clock oscillation frequency of the PLL circuit gradually increases or decreases due to the characteristics inherent in the PLL circuit. When the video signal is displayed using the reproduced dot clock signal, the display phase of the video signal is shifted at the upper end position of the screen corresponding to the scanning position immediately after the vertical synchronization period, and as a result, the displayed video However, there is a problem that the image is distorted at the upper end position on the screen.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device for setting a predetermined portion or the whole of a designated display area on a liquid crystal display screen so as to have an optimum sampling timing.

[0009]

In order to solve the above-mentioned problems, a liquid crystal display device according to the present invention synchronizes with a horizontal synchronizing signal of an input image signal and outputs a dot having a frequency which is an integral multiple of the horizontal synchronizing signal. A dot clock regeneration circuit for generating a clock signal; a horizontal counter for counting the dot clock signal generated by the dot clock regeneration circuit and outputting a horizontal position value of the image signal on a display screen; And outputs a vertical position value of the image signal on the display screen, and controls a delay amount of the dot clock signal according to the vertical position value output from the vertical counter and the horizontal position value. And a liquid crystal display module for displaying an image by an output signal from the control circuit.

In order to solve the above-mentioned problem, a liquid crystal display device according to the present invention stores the delay amount corresponding to a position on the display screen determined by the horizontal position value and the vertical position value. It is characterized by comprising a control circuit.

Further, in order to solve the above-mentioned problem, the liquid crystal display device of the present invention stores the delay amounts respectively corresponding to predetermined areas on the display screen determined by the horizontal position values and the vertical position values. It is characterized by comprising the above control circuit.

[0012]

Next, a liquid crystal display according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a liquid crystal display according to an embodiment of the present invention.

FIG. 2 is a block diagram of a delay switching circuit of a liquid crystal display according to an embodiment of the present invention.

FIG. 3 is a selection state diagram of a delay amount of the liquid crystal display device according to one embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an embodiment of the present invention is an information processing apparatus 1 for outputting an RGB video signal Sv and horizontal and vertical synchronization signals Hsy and Vsy.
01 and the horizontal and vertical synchronizing signals Hsy and Vsy are supplied, synchronized with the horizontal synchronizing signal Hsy, and
A dot clock reproduction circuit 102 for generating and outputting a dot clock signal φ having a frequency that is an integral multiple of y, and horizontal and vertical synchronization signals Hsy, Vsy and a dot clock signal φ are supplied, and the position of the dot clock signal φ on the display screen A control circuit 104 that outputs switching control data Ds according to
Delay switching in which the horizontal and vertical synchronizing signals Hsy and Vsy, the dot clock signal φ, and the switching control data Ds are supplied, and the dot clock signal φ is delayed by a delay amount according to the switching control data Ds and output as a delayed dot clock signal φd. And a circuit 103.

As shown in FIG. 2, the delay switching circuit 103 is supplied with a dot clock signal φ from the dot clock regeneration circuit 102, and delays the dot clock signal φ to output different delay amounts in parallel. The circuit 201 and the dot clock signal φ are connected to the clock terminal,
The horizontal synchronizing signal Hsy is supplied to the reset terminal, a horizontal counter 202 for outputting horizontal count value data Dh indicating the horizontal position of the dot clock signal φ on the display screen, the horizontal synchronizing signal Hsy to the clock terminal, the vertical synchronizing signal Vs
y is supplied to the reset terminal, and the vertical count value data Dv representing the vertical position of the dot clock signal φ on the display screen.
, The horizontal count value data Dh, the vertical count value data Dv, and the switching control data D.
s is supplied and a switching signal Ss is generated and output from the switching control data Ds in accordance with the position of the dot clock signal φ on the display screen determined by the horizontal count value data Dh and the vertical count value data Dv. Selection circuit 204
And a plurality of delayed dot clock signals from the delayed clock generating circuit 201 are input in parallel, and one of the plurality of delayed dot clock signals is selectively output as a delayed dot clock signal φd in accordance with the switching signal Ss. And a circuit 205.

Next, the operation of the liquid crystal display device according to one embodiment of the present invention will be described with reference to the drawings.

The operation of the liquid crystal display device according to the first embodiment of the present invention will be described first with reference to FIGS.
The horizontal synchronizing signal output from the information processing apparatus 101 is generated by the dot clock reproducing circuit 102 by multiplying one pixel of the video signal by an integer so as to have one cycle. As the value of the set integer multiple, a preset value determined from the input horizontal synchronization wave number and vertical synchronization frequency is used, or a value adjusted and selected by the user is set by the control circuit 104. . Next, the horizontal counter 202 outputs a horizontal synchronization signal Hsy input from the information processing apparatus 101.
And the dot clock φ required to specify the horizontal position on the display screen from the dot clock φ input from the dot clock reproduction circuit 102, and generates horizontal count value data Dh.
3 is a vertical synchronization signal V input from the information processing apparatus 101
sy and the horizontal synchronization signal Hs necessary for specifying the vertical position on the display screen from the horizontal synchronization signal Hsy.
y is counted to create vertical count value data Dv.
Next, a specific display position or display area and a delay time amount of the selected dot clock φ are designated to the control circuit 104 by an external instruction (not shown) by a user's operation or the like from a state displayed on the screen. The control circuit 1
Reference numeral 04 creates switching control data Ds including the display position or display area and the selected delay time. The delay signal selection circuit 204 monitors the horizontal count data Dh and the vertical count data Dv, always compares the input count data with the switching control data Ds indicating the display position or display area, and compares the input count data with the display data. As soon as it is determined that the positions match or the display area is included, the switching signal Ss indicating the designated delay time is output. Delay C
The LK switching circuit 205 selects one of the specified delay amounts based on the input switching signal Ss from the dot clocks having a plurality of delay amounts input from the delay CLK generation circuit 201, and immediately delays the delay dot. The clock φd is output. Therefore, the liquid crystal display module 105 samples each pixel of the input video signal using the dot clock φd having a different phase within one display screen.

In one display example of the liquid crystal display device according to the embodiment of the present invention, as shown in FIG. 3, the control circuit 104 includes a, b indicating the change point of the delay amount in the horizontal direction, and the delay amount in the vertical direction. Control data D having c, d, and e indicating the change points of, and delay amounts n, n + 1, and n + 2 used after the respective change points.
By creating s and instructing the delay signal selection circuit 204, a dot clock φd having the delay amount shown in FIG. 3 can be created. The above display example is an example of the creation of the switching control data Ds specifying the image display position. In the present invention, the display screen is specified as an area divided into blocks, and the delay amount is assigned to each block. By generating the switching control data Ds having the selected delay amount, dynamic delay amount control in which a region is specified can be performed.

As described above, even if the video signal Sv and the dot clock to be sampled have different phases within one display screen, the video signal can always be sampled at the optimum phase, and the optimum display can be obtained. it can.

[0022]

As described above, according to the liquid crystal display device of the present invention, the dot clock signal reproduced by the dot clock reproducing circuit includes the first half of the horizontal scanning period,
Even if a phase shift occurs in the latter half or the middle part, the phase shift is eliminated during the horizontal scanning period by adjusting the delay amount of the dot clock signal in accordance with the position on the display screen. Therefore, there is an effect that a display image with high accuracy can be obtained without distortion of the display image.

Further, according to the liquid crystal display device of the present invention, even if a signal such as a composite signal to which the horizontal synchronizing signal is not supplied during the vertical synchronizing period is supplied and a phase shift occurs, the position on the display screen is maintained. The phase shift is eliminated during the vertical scanning period by adjusting the delay amount of the dot clock signal in accordance with the condition (1), so that the display image is not distorted even at the upper end on the display screen. There is an effect that an accurate display image can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a delay switching circuit of the liquid crystal display device according to one embodiment of the present invention.

FIG. 3 is a selection state diagram of a delay amount of the liquid crystal display according to the embodiment of the present invention;

FIG. 4 is a block diagram of a conventional liquid crystal display device.

FIG. 5 is a block diagram of a delay switching circuit of a conventional liquid crystal display device.

[Explanation of symbols]

 101, 401 Information processing device 102, 402 Dot clock reproduction device 103, 403 Delay switching circuit 104, 404 Control circuit 105, 505 Liquid crystal display module 201, 501 Delay clock generation circuit 202 Horizontal counter 203 Vertical counter 204 Delay signal selection circuit 205, 502 Delayed clock switching circuit

Claims (3)

[Claims] 1. A dot clock reproducing circuit which synchronizes with a horizontal synchronizing signal of an input image signal and generates a dot clock signal having a frequency which is an integral multiple of the horizontal synchronizing signal, and a dot generated by the dot clock reproducing circuit. A horizontal counter that counts a clock signal and outputs a horizontal position value of the image signal on a display screen; and a vertical counter that counts the horizontal circumference synchronization signal and outputs a vertical position value of the image signal on a display screen. A control circuit for controlling and outputting a delay amount of the dot clock signal in accordance with the vertical position value output from the vertical counter and the horizontal position value, and a liquid crystal display for displaying an image by an output signal from the control circuit A liquid crystal display device comprising a module. 2. A liquid crystal display according to claim 1, wherein said control circuit stores said delay amount corresponding to a position on said display screen determined by said horizontal position value and vertical position value. Display device. 3. The control circuit according to claim 1, wherein said control circuit is configured to store the delay amount corresponding to a predetermined area on the display screen determined by the horizontal position value and the vertical position value. Liquid crystal display.