JP2000147453A - Liquid crystal display driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a constant display picture by preventing the signal processing of a video signal from being disturbed by the picture position adjusting of the display picture by only adding a circuit having a simple constitution to a controller in a liquid crystal display device. SOLUTION: A horizontal synchronizing signal generating circuit 64 is provided in the controller of the liquid crystal display device. This circuit 64 is consisting of an inverter INV and an OR circuit OR and a picture position adjusting signal PH from a horizontal decoder 56 is inputted to the inverter INV and a picture position adjusting and delaying signal PH1 from the output of the decoder and a delay control circuit 55 is inputted to the OR circuit OR and a horizontal color synchonizing signal HDS is obtained from the output of the circuit 64. The generation timing of the signal HDS is constant and is never deviated with respect to the signal PH1. Thus, when a burst gate pulse is made to be produced from the signal HDS in a video interface, a correct chroma processing and a correct pedestal clamping can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a liquid crystal display driving device, and more particularly to an improvement for preventing signal processing of display color information of an input video signal from being disturbed by adjusting a horizontal position of a display screen.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional liquid crystal display device. In the liquid crystal display device 1, 2 is an input terminal of a composite video signal, 3 is a video interface circuit including an RGB decoder, an inverting amplifier and the like, 5 is a controller,
6 is an amplifier, 7 is a scanning driver, 8 is a signal side driver,
9 is a liquid crystal display panel.

The liquid crystal display panel 9 has a plurality of scanning lines (gate lines) Xn and signal lines (drain lines) Ym arranged in a matrix on a substrate. Each of the scanning lines Xn and signal lines Ym is arranged in a matrix. Near the intersection is an n-channel MOS type TFT (Thin film transisto).
r) It has a switching element composed of an element, and a pixel made of liquid crystal sandwiched between a pixel electrode connected to a source electrode of the switching element and a counter electrode.

The composite video signal input from the video input terminal 2 is sent to a video interface circuit 3.

[0005] The video interface circuit 3 detects a sync separation for the input composite video signal and generates a burst signal in response to a burst gate pulse BGP generated based on the horizontal color synchronization signal HDB output from the controller 5. By extracting and performing processing such as chroma processing, it decodes and outputs the R, G, B primary color signals and the synchronizing signal CSY including the horizontal synchronizing signal H and the vertical synchronizing signal V, and obtains the obtained synchronizing signal CSY. To the controller 5 by pedestal clamping the primary color signals R, G, and B according to the BGP signal, and inverting the polarity appropriately in units of scanning lines and fields in accordance with the inversion signal FRP output from the controller 5. Inverted signal R,
G and B are output to the signal side driver 8.

FIG. 4 illustrates a detailed circuit configuration of the controller 5. The controller 5 includes a PLL circuit 5.
1, VCO (oscillation circuit) circuit 52, delay control circuit 55,
It comprises a horizontal decoder 56, a horizontal counter 57, a dot CK generation circuit 58, a synchronization control circuit 59, a vertical decoder 60, a vertical counter 61, an FRP generation circuit 62, a vertical synchronization signal separation circuit 63, and the like. First, the video signal horizontal synchronizing signal CSY from the video interface circuit 3 is input to the PLL circuit 51 and the vertical synchronizing signal separating circuit 63, and the vertical synchronizing signal V from the circuit 63 is input to the synchronizing control circuit 59.
Is input to

The horizontal counter 57 includes a VCO circuit 52
And the dot positions within one horizontal scanning period of the input video signal are counted.

The horizontal decoder 56, based on the count value of a horizontal counter 57 for counting the dot position within one horizontal scanning period of the input video signal, performs a sampling start pulse signal SRT, an output enable signal OE, and a clear signal CLR. Is output to the signal driver 8 as a part of the horizontal control signal, and the gate reset signal GRES and the gate pulse clock GPCK are output to the scanning driver 7 as a part of the vertical control signal. Also,
The horizontal decoder 56 outputs an internal horizontal synchronization signal H serving as a scanning line clock to the vertical counter 61 and the FRP generation circuit 62, and outputs the internal horizontal synchronization signal to the horizontal counter 57 as a reset signal R. Then, the horizontal decoder 56 generates an image position adjustment signal PH based on the count value of the horizontal counter 57 and outputs it to the delay control circuit 55.

The delay control circuit 55 generates an image position adjustment delay signal PH1 obtained by delaying the image position adjustment signal PH output from the horizontal decoder 56, and outputs it to the PLL circuit 51.

The PLL circuit 51 controls the VCO (voltage oscillation control) so that the image position adjustment delay signal PH1 supplied from the delay control circuit 55 and the video signal horizontal synchronization signal CSY supplied from the RGB decoder 3 have the same phase. Circuit) 52
The voltage of the oscillation control signal is controlled.

The VCO circuit 52 oscillates at a frequency corresponding to the voltage of the oscillation control signal and outputs a basic clock CK.

The controller 5 controls the horizontal display position of the video signal so that the video signal is displayed at the center position of the liquid crystal display panel 9. That is, the sampling start pulse signal SRT instructing the signal driver 8 to start driving the signal line to adjust the horizontal position of the video signal based on the delay amount of the image position adjustment delay signal PH1 in the delay control circuit 55. Adjust the output timing of.

FIG. 5 is a timing chart showing the operation of the above-described conventional device. The image position adjustment signal PH shown in FIG. 5C is delayed by a predetermined time by the delay control circuit 55 to generate an image position adjustment delay signal PH1 shown in FIG. 5D. Further, the rising position of the image position adjustment delay signal PH1 is controlled so as to be always at the center position of the video signal horizontal synchronization signal CSY waveform shown in FIG. The image display start timing is determined by the timing of the sampling start signal SRT shown in FIG. 5 (h) with respect to the image signal (FIG. 5 (i)), and the timing of the sampling start signal SRT is determined by the image position adjustment signal PH (FIG. 5).
There is a certain fixed timing from the rising position of (c)). Therefore, the image position adjustment signal PH (FIG. 5)
(C)) The image position adjustment delay signal PH1 (FIG. 5)
By adjusting the delay amount of (d)), the timing of the sampling start signal SRT with respect to the image signal changes, and the image display start timing, that is, the horizontal display position of the screen is adjusted.

On the other hand, processing such as chroma processing and pedestal clamping for accurately extracting and displaying color information of a video signal is performed based on a color burst signal included in the video signal. The timing at which this process is performed is determined by the burst gate pulse BGP (FIG. 5E) generated in the video interface circuit 3. This burst gate pulse BGP is applied to the horizontal color synchronizing signal H input from the controller 5 to the video interface circuit 3.
It is generated based on the DB (FIG. 5 (f)).

[0015]

As described above, signal processing such as chroma processing and pedestal clamp for correctly displaying the color of a video signal is performed at the timing of the horizontal color synchronizing signal HDB input to the video interface circuit 3. It is done based on. In the conventional model, the horizontal color synchronizing signal HDB and the sampling start signal SRT are generated by the same horizontal counter, and each has a certain fixed timing from the image position adjustment signal PH. Therefore, as described above, when the delay amount of the image position adjustment delay signal PH1 is adjusted to change the timing of the sampling start signal SRT for the image signal for adjusting the image display position of the display screen, the horizontal color synchronization signal for the image signal is adjusted. The timing of HDB also changed at the same time. Therefore, the timing of the burst gate pulse BGP with respect to the color burst signal of the video signal changes together with the above-described image display position adjustment, so that it becomes impossible to perform a proper chroma processing, pedestal clamp, and the like, and a displayed image may be disturbed. was there.

In order to solve the above problem, for example, Japanese Patent Laid-Open No. 10-011027 is disclosed. This is obtained by adding a horizontal counter and a decoder circuit for generating a horizontal color synchronization signal HDB from the image position adjustment delay signal PH1.

According to this configuration, the horizontal color synchronizing signal HDB
Is fixed at a fixed timing with respect to the image position adjustment delay signal PH1, so that a stable video signal burst extraction and pedestal clamp operation can be performed. However, this configuration has a problem that the circuit scale becomes large and power consumption also increases.

An object of the present invention is to solve the above problems.
A liquid crystal display drive device that is configured to perform stable chroma processing and pedestal clamp by adding a circuit with a simple configuration to the controller and adjusting the horizontal display position so that the horizontal color synchronization signal generation timing does not change. Is to provide.

[0019]

To achieve the above object, the present invention provides a delay means for delaying an image position adjustment signal for adjusting an image position of a liquid crystal display screen to generate an image position adjustment delay signal; Synchronizing means for synchronizing the image position adjustment delay signal with the input video signal, and video signal processing means for performing signal processing of display color information of the video signal from the color burst signal of the input video signal based on the timing of the horizontal color synchronizing signal And a horizontal color synchronizing signal generating means for generating the horizontal color synchronizing signal synchronized with the image position adjustment delay signal.

In the liquid crystal display driving device according to the present invention,
The horizontal color synchronizing signal generating means may comprise a horizontal color synchronizing signal generating circuit for generating a horizontal color synchronizing signal from the image position adjusting signal and the delayed image position adjusting signal.

[0021]

FIG. 1 shows a detailed circuit configuration of a controller 5 in one embodiment of a liquid crystal display driving device according to the present invention. The portions corresponding to those in FIG. Omitted. The controller 5 includes a PLL circuit 5
1, VCO (oscillation circuit) circuit 52, delay control circuit 55,
It comprises a horizontal decoder 56, a horizontal counter 57, a dot CK generation circuit 58, a synchronization control circuit 59, a vertical decoder 60, a vertical counter 61, an FRP generation circuit 62, a vertical synchronization signal separation circuit 63, a horizontal color synchronization signal generation circuit 64, and the like. ing.

First, the video signal horizontal synchronizing signal CSY from the video interface circuit 3 is input to the PLL circuit 51 and the vertical synchronizing signal separating circuit 63, and the vertical synchronizing signal V from the circuit 63 is input to the synchronizing control circuit 59, respectively. .

The horizontal counter 57 includes a VCO circuit 52
And the dot positions within one horizontal scanning period of the input video signal are counted.

The horizontal decoder 56, based on a count value of a horizontal counter 57 for counting the dot position within one horizontal scanning period of the input video signal, a sampling start pulse signal SRT, an output enable signal OE, and a clear signal CLR. Is output as a part of the horizontal control signal. Further, the horizontal decoder 56 outputs the internal horizontal color synchronizing signal H serving as the scanning line clock to the vertical counter 61 and F
In addition to outputting to the RP generation circuit 62, the internal horizontal color synchronizing signal is output to the horizontal counter 57 as a reset signal R. Then, the horizontal decoder 56 outputs the image position adjustment signal P based on the count value of the horizontal counter 57.
H is generated and output to the delay control circuit 55.

The delay control circuit 55 generates an image position adjustment delay signal PH1 obtained by delaying the image position adjustment signal PH output from the horizontal decoder 56, and outputs it to the PLL circuit 51.

The PLL circuit 51 controls the VCO (voltage oscillation control) so that the image position adjustment delay signal PH1 supplied from the delay control circuit 55 and the internal horizontal color synchronization signal H supplied from the RGB decoder 3 have the same phase. Circuit) 52 controls the voltage of the oscillation control signal.

The VCO circuit 52 oscillates at a frequency corresponding to the voltage of the oscillation control signal and outputs a basic clock CK.

The controller 5 controls the horizontal display position of the video signal so that the video signal is displayed at the center of the liquid crystal display panel. That is, the sampling start signal SR for instructing the signal driver to start driving the signal line to adjust the horizontal position of the video signal based on the delay amount of the image position adjustment delay signal PH1 in the delay control circuit 55.
Adjust the timing of T.

In the apparatus of the present invention, a horizontal color synchronizing signal generation circuit 64 for generating a horizontal color synchronizing signal HDB from the image position adjusting signal PH and the image position adjusting delay signal PH1 is added to the controller 5. ing. This circuit 6
Reference numeral 4 denotes, for example, a simple configuration including an inverter INV and an OR circuit OR. An image position adjustment signal PH is input to the inverter INV, and the output and the image position adjustment delay signal PH1 are sent to the OR circuit OR. The horizontal color synchronizing signal HDB is obtained at the output. The horizontal color synchronizing signal HDB is input to the video interface circuit 3 to generate a burst gate pulse BGP.

FIG. 2 is a timing chart showing the operation of the above-described apparatus of the present invention. The image position adjustment signal PH shown in FIG. 2C is delayed by the delay control circuit 55 for a predetermined time, and the image position adjustment delay signal PH1 shown in FIG.
Is generated. Further, the rising position of the image position adjustment delay signal PH1 is controlled so as to be always at the center position of the waveform of the video signal horizontal synchronizing signal CSY shown in FIG. Image display start timing is determined by the timing (FIG. 2 (i)) of the sampling start signal SRT shown in FIG. 2 (h) with respect to the image signal. The timing of the sampling start signal SRT is determined by the image position adjustment signal PH (FIG. 2).
There is a certain fixed timing from the rising position of (c)). Therefore, the image position adjustment signal PH (FIG. 2)
2 (c)), the image position adjustment delay signal PH1 (FIG. 2)
By adjusting the delay amount of (d)), the timing of the sampling start signal SRT with respect to the image signal changes, and the image display start timing, that is, the horizontal display position of the screen is adjusted.

On the other hand, processes such as chroma processing and pedestal clamp for accurately extracting and displaying color information of a video signal are performed based on a color burst signal included in the video signal. The timing at which this process is performed is determined by the burst gate pulse BGP (FIG. 2E) generated in the video interface circuit 3. This burst gate pulse BGP is applied to the horizontal color synchronizing signal H input from the controller 5 to the video interface circuit 3.
It is generated based on the DB (FIG. 2 (f)).

As described above, even if the timing of the sampling start signal SRT is changed by adjusting the delay amount of the image position adjustment delay signal PH1 for adjusting the horizontal position of the display image, the horizontal color synchronizing signal HDB (FIG. Since f)) is generated from the image position adjustment signal PH and the image position adjustment delay signal PH1, the rising timing is constant with respect to the image position adjustment delay signal PH1, and does not shift due to the horizontal display position adjustment of the display image. .

Since the rising timing of the horizontal color synchronizing signal HDB is synchronized with the image position adjustment delay signal PH1, the video interface circuit converts the horizontal color synchronizing signal HDB from the burst gate pulse BGP (FIG. 2).
By generating (e), stable chroma processing and pedestal clamping can be performed.

[0034]

As described above, according to the present invention, by simply adding a circuit having a simple structure to the controller, the signal processing of the video signal is not disturbed by the adjustment of the image position on the display screen, and the stable display is achieved. An image is obtained. In addition, the circuit scale hardly increases, and the power consumption hardly increases.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a controller according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the device of FIG.

FIG. 3 is a block diagram illustrating a schematic configuration of a conventional liquid crystal display device.

FIG. 4 is a block diagram showing a configuration of a controller in the apparatus shown in FIG.

FIG. 5 is a timing chart showing the operation of the device of FIG.

[Description of Signs] 51 PLL circuit 52 VCO 55 delay control circuit 56 horizontal decoder 57 horizontal counter 64 horizontal color synchronization signal generation circuit INV inverter OR OR circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NC16 NC21 NC27 ND39 ND49 5C006 AA01 AA22 AF52 AF71 BB11 BF07 BF16 BF22 BF25 BF26 BF27 BF49 FA21 FA41 FA47 5C060 HB08 HB09 HB21 5C082 AA02 BA41 BB02 BM02 BC41

Claims (2)

[Claims] 1. A delay means for delaying an image position adjustment signal for adjusting an image position of a liquid crystal display screen to generate an image position adjustment delay signal, and synchronizing the image position adjustment delay signal with an input video signal. Means for performing signal processing of display color information of a video signal from a color burst signal of an input video signal based on the timing of a horizontal color synchronizing signal. A liquid crystal display driving device comprising a horizontal color synchronizing signal generating means for generating the horizontal color synchronizing signal synchronized with a signal. 2. A horizontal color synchronizing signal generating circuit for generating a horizontal color synchronizing signal based on an image position adjusting signal and a delayed image position adjusting signal. The liquid crystal display driving device according to the above.