JPH10228266A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically adjust a screen position, size, and a sampling clock frequency in the liquid crystal display device which displays a variety of signals. SOLUTION: This device is provided with A/D converters 15 to 17, a PLL circuit 18, a scan converting circuit 1, counters 4 and 5, an OR circuit 3, flip- flops 9 to 13 which compare the phase of the signal outputted by the OR circuit 3 with that of an enable signal, and a CPU 14, and changes settings of the scan converting circuit 1, counters 4 and 5, and PLL circuit 18 according to the output values of the flip-flops 10 to 13 to automatically adjust the screen position and size on the liquid crystal display device and the sampling lock frequency at the time of A/D conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (International Patent Classification G09) provided with means for automatically optimizing the display position and display size of a screen on a liquid crystal display.
G 1/14).

[0002]

2. Description of the Related Art Conventionally, when a signal generated from a signal source such as a computer is displayed on a liquid crystal display screen, a phase difference between a horizontal and vertical synchronizing signal generated from the signal source and a video signal is generally determined by the signal source. Since the position of the image displayed on the liquid crystal display screen also differs because the
In order to adjust this automatically, see, for example,
No. 9486, a pulse for driving a liquid crystal display device based on input horizontal and vertical synchronization signals, and a signal obtained by slicing a video signal generated from a signal source at a constant level using a comparator or the like. Is generated,
Using an AND circuit, the phase of the liquid crystal display device driving pulse is compared with the phase of the output signal of the comparator.
By feeding back to the PU and controlling the phase of the liquid crystal display device driving pulse based on the phase comparison result, the position on the liquid crystal screen was automatically controlled.

The purpose of this conventional automatic position adjustment is to eliminate the trouble of the user adjusting the screen display position by the display position adjusting means while watching the screen displayed, and at the same time to use a switch for adjusting the screen display position. That is, there is no need for a simple adjusting means.

However, since the timing of a signal generated from a signal source, that is, the number of pixel data per horizontal period and the number of lines per vertical period are also various, the number of pixels included in a liquid crystal display device is generally different. Therefore, simply transmitting an A / D-converted video signal to a digital RGB signal to a liquid crystal display screen requires display using 100% of the display area (hereinafter, referred to as the following).
Just scan). Therefore, in order to perform the just scan, the input signal must be subjected to scan conversion, that is, a process of making the number of data in one horizontal period and the number of lines in one vertical period coincide with the number of pixels of the liquid crystal display screen to be used. Must.

As described above, in order to use the liquid crystal display device and perform the just scan in displaying various timings, it is necessary to drive the liquid crystal display device such that the image is accurately positioned at the center of the liquid crystal display area. In addition to setting the phase of the pulse, the optimum scan conversion rate must be set according to the timing of the signal source. However, the conventional automatic position adjustment can be applied only when the timing of the input signal source, in particular, the horizontal frequency and the frequency of the horizontal pulse for driving the liquid crystal display device can be made the same, that is, when the scan conversion need not be performed. Therefore, only the display position can be automatically adjusted, and the display size cannot be automatically adjusted.

Further, even when the frequency of the input signal source and the frequency of the pulse for driving the liquid crystal display device can be made the same, that is, even when the number of effective pixels of the input video signal is the same as the number of effective pixels of the liquid crystal display device, The original clock frequency at which a signal is generated generally depends on the signal source. To accurately reproduce an image on a liquid crystal display screen, the dot clock frequency of the signal source and the A / D conversion time are required. It is necessary to completely match the sampling clock frequency of the liquid crystal display.
There is no means for automatically adjusting the sampling clock frequency during A / D conversion.

[0007]

As described above, in the conventional liquid crystal display device, the timings of the signal sources are various, and the scan conversion must be performed on the liquid crystal display screen and the scan conversion rate must be set optimally. Contrary to the situation where just scan is not performed, automatic adjustment of position and size cannot be performed for an arbitrary signal timing. Even if the signal is limited to a signal that does not require scan conversion, since there is no means for matching the dot clock frequency on the signal source side with the sampling clock frequency at the time of A / D conversion, the signal is generated from a wide variety of signal sources. In order to accurately display the video signal to be displayed, the user must adjust the screen display position and size or the frequency of the sampling clock while watching the screen displayed at the end, and together with that, the screen display position and size In addition, there is a problem that an adjusting means such as a sampling clock frequency adjusting switch is required, and the configuration of the operating means is complicated.

In view of this problem, the present invention automatically adjusts the screen position, size, and sampling clock frequency so that the screen position, size, and sampling clock frequency are optimal for various timings in video display using a liquid crystal display unit. It is an object of the present invention to provide a video display device capable of adjusting a size and a sampling clock frequency.

[0009]

In order to solve the above-mentioned problems, the present invention provides a digital R / D conversion and a scan conversion as required, which can be displayed on a liquid crystal display unit.
The phase of the GB signal is compared with the phase of an enable signal indicating the display period of the liquid crystal display device, and the conversion rate of scan conversion, the phase of the enable signal, and A
By changing the sampling clock frequency of the / D conversion, the display position and display size of the image on the liquid crystal display device and the sampling clock frequency of the A / D conversion are automatically adjusted.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a digital RGB signal scan-converted so as to be displayed on a liquid crystal display,
By comparing a phase with an enable signal indicating a display period of the liquid crystal display unit, and changing a conversion rate of the scan conversion and a phase of the enable signal according to the result, an image of the image on the liquid crystal display unit is changed. It is characterized by automatically adjusting the display position and display size. By automatically setting the optimal position and size for various signal timings, the screen displayed by the user is This eliminates the need to manually adjust the screen display position, size, and sampling clock frequency while watching, and also eliminates the need for adjusting means such as a switch for adjusting the screen display position, size, and sampling clock frequency.

Hereinafter, an embodiment of the present invention will be described.
This will be described with reference to FIGS. 1, 2, 3, 3, 4, 5, 6, 7, and 8.

(Embodiment 1) In FIG. 1, an input analog video signal is converted into a digital video signal by A / D converters 15-17. A / D converter 15-1
The sampling clock ADCK 7 is generated by the PLL circuit 18. The PLL circuit 18 generates ADCK by multiplying the input horizontal synchronization signal H. The setting of the multiplication factor is performed by the control signal PLLCT.

The scan conversion circuit 1 shown in FIG. 1 is for converting the number of horizontal pixels and the number of vertical pixels of an input digital video signal into the number of pixels that can be displayed by the liquid crystal display unit 2, and has a scan conversion rate ( The ratio between the number of pixels before conversion and the number of pixels after conversion) is set by the control signal SCT. The digital video signal after scan conversion is R ', G', and B ', each having 6 bits.

The liquid crystal display unit 2 shown in FIG. 1 has R ', G', B '
Each of these displays a 6-bit digital video signal in color, and requires a horizontal synchronizing signal HP, a vertical synchronizing signal VP, an enable signal ENBP which becomes H level only during the display period of the liquid crystal display unit 2, and a clock CLK as control signals. I do. The frequency of the horizontal synchronization signal HP and the frequency of the vertical synchronization signal VP do not always match the horizontal synchronization and vertical synchronization frequencies of the signal source. This is because the scan conversion circuit 1 is inserted between the signal source and the liquid crystal display unit 2. Since the period in which the enable signal ENBP is at the H level indicates the display period in the liquid crystal display unit 2, the digital signal R ′ input to the liquid crystal display unit 2,
If the period between the G 'and B' displays and the period during which the enable signal ENBP is at the H level completely match, the image on the screen is necessarily optimized (just scan).

The frequency of the clock signal CLK in FIG. 1 may be different from the frequency of the sampling clock ADCK for A / D conversion.

The OR3 in FIG. 1 is for ORing the most significant bit of each of the output digital signals R ', G', and B 'of the scan conversion circuit 2. The output signal of the OR3 is a display of an RGB signal. The period is H, and the blanking period is L.

The counter 4 shown in FIG. 1 counts a clock CLK for driving the liquid crystal display unit 2 so that the horizontal synchronizing signal HP of the liquid crystal display unit 2, the signal HENB serving as a source of the enable signal ENBP, and the horizontal synchronizing signal HP are counted. To generate a signal HP2 whose phase is shifted. The phase setting of each signal is performed by the control signal HCCT.

The counter 5 shown in FIG. 1 counts a signal HP (which is a horizontal synchronizing signal of the liquid crystal display unit 2) generated by the counter 4, thereby obtaining a vertical synchronizing signal VP of the liquid crystal display unit 2 and an enable signal ENBP. Is generated. The phase setting of each signal is performed by the control signal VCCT.

AND 6 is a signal HENB generated by the counter 4 and a signal VEN generated by the counter 5.
By ANDing B, an enable signal ENBP for the liquid crystal display unit 2 is generated.

Reference numerals 7 to 13 in FIG. 1 denote flip-flops. The flip-flop 7 is for synchronizing the output signal of the OR3 again at the rising edge of the clock CLK. The output signal is Y.

The flip-flop 8 and the NOT 15
This is for synchronizing the enable signal ENBP at the falling edge of the clock CLK. The output signal is ENBP2 on the non-inverted side and / ENBP2 on the inverted side.

The flip-flop 9 has an enable signal E
This is for shifting the phase of the signal VENB, which is the source of the NBP, and synchronizes the signal VENB at the rise of the signal HP2 (which is out of phase with the horizontal synchronization signal HP).
The output signal is VENB2 on the non-inverting side and // on the inverting side.
VENB2.

The flip-flops 10 to 13 supply the signal Y to ENBP2, / ENBP2, VENB2, / V
This is for synchronization at the rising edge of ENB2.
The output signals are HF, HB, VF, and VB, respectively.

The CPU 14 has flip-flops 10-1.
3, the control signal SCT of the scan conversion circuit 1, the control signal HCCT of the counters 4 and 5,
This is for changing the setting of the signal PLLCT which controls the multiplication ratio of the VCCT and PLL circuit 18.

Next, referring to FIGS. 2, 3, 4 and 5,
Screen position / size and input signals HF, H to CPU 14
The relationship between B, VF, and VB will be described. In the following description, the number of effective pixels of the liquid crystal display unit 2 in FIG.
The number of pixels is 24 and the vertical is 768 lines. Therefore, the enable signal ENBP indicating the display period of the liquid crystal display device is 1024 CLK in the H period when viewed at the horizontal rate and 768 lines in the H period when viewed at the vertical rate.

FIG. 2 shows HF, HB, and HF when the size of the image on the liquid crystal display unit 2 in FIG. 1 is small both horizontally and vertically.
It is a timing diagram of VF and VB. For simplicity, the input signal is all white. In this case, the outputs R ', G', and B 'of the scan conversion circuit 1 all have the same waveform (because they are all white). Therefore, for the sake of simplicity, only R 'is described, but G',
B 'has the same waveform as R'.

First, the timing waveform at the horizontal rate will be described. The signal Y is a signal delayed by 1 CLK with respect to R ′. The signal ENBP2 is half CL with respect to the signal ENBP.
The signal is delayed by K, and / ENPB2 has an inverted waveform of ENPB2.

The signal HF is a signal obtained by latching the signal Y at the rising edge of the signal ENPB2.
Becomes Similarly, the signal HB is set to the signal / ENPB2
Is the signal latched at the rising edge of the signal, and in this case, it is always L.

Next, the timing waveform at the vertical rate will be described. The signal HP2 is a signal shifted by a half cycle from the signal HP as shown in the figure. The signal VENB2 is the signal VENB
Are latched at the rising edge of HP2. / VE
NBP2 is an inverted signal of VENBP2. Since the signal VF is a signal obtained by latching the signal Y at the rising edge of VENBP2, the signal VF is always L in this case. The signal VB is the signal Y
Is latched at the rising edge of / VENBP2, and therefore always becomes L in this case.

FIG. 3 shows that the size of the image on the liquid crystal display unit 2 is
HF, HB, VF, V when both horizontal and vertical are large
FIG. 4B is a timing chart of FIG. Here, for simplicity, the input signal is all white. In the case of this example, the signals HF, H
B, VF and VB all become H.

FIG. 4 shows HF, HB, and HF when the size of the image on the liquid crystal display unit 2 is optimal both horizontally and vertically.
It is a timing diagram of VF and VB. Here, for simplicity, the input signal is all white. In the case of this example, the signal H
F = L, HB = H, VF = H, and VB = L.

As described above, the signals HF,
FIG. 5 shows the relationship between the state of HB, VF, and VB and the position / size on the screen.

Next, in the automatic position / size adjustment, the CP
One example of the processing to be performed by U14 will be described with reference to FIGS. 6, 7, and 8. FIG. In the present embodiment, the number of effective display pixels of the input signal source is different from the number of effective display pixels of the liquid crystal display unit. Therefore, the control of the horizontal and vertical sizes is performed by controlling the conversion rate of the scan conversion circuit 1. PLL circuit 18
The setting of the dividing ratio may be an appropriate value.

FIG. 6 shows the main part of the flow (flow chart) of the automatic position / size adjustment process. In this example, the vertical position / size is optimized first.

FIG. 7 is a flowchart of automatic screen position / size adjustment in the vertical direction. HF and HB are not needed here because only the information on the vertical needs to be acquired, and VF and VB are read. The state of VF and VB,
Since the current state of the screen is in the relationship described above with reference to FIG. 5, it is sufficient to perform a process that reverses the screen state. For example, when (VF, VB) = (L, L), the current screen state in the vertical direction is in a small size state, so that processing for increasing the vertical size is performed. Specifically, the setting of the scan conversion rate in the vertical direction is changed by a control signal SCT from the CPU 14 to the scan conversion circuit 1 in FIG. In the case of (VF, VB) = (H, L), since the current screen state may already be optimal in the vertical direction, the screen state is deliberately shifted once, and it is confirmed that the screen is too low. Shift up again to end. Here, the control to shift the screen position downward or upward is performed by the control signal VCCT from the CPU 14 to the counter 5 in FIG. That is, the signals VP and VEN are independent of the signals R ', G', and B 'input to the liquid crystal display unit 2.
The phase of B is shifted.

FIG. 8 is a flowchart of the automatic adjustment of the screen position / size in the horizontal direction. VF and VB are unnecessary here, and HF and HB are read because only the information on the horizontal needs to be acquired. The state of HF, HB,
Since the current state of the screen is in the relationship described above with reference to FIG. 5, it is sufficient to perform a process that reverses the screen state. For example, when (HF, HB) = (L, L), the current horizontal screen state is in a small size state, and therefore, a process of increasing the horizontal size is performed. The change of the size setting is performed by the control signal SCT from the CPU 14 to the scan conversion circuit 1 as in the case of the vertical setting. (HF, H
In the case of B) = (L, H), the current screen state may already be optimal. Therefore, once shift to the left intentionally, confirm that the screen has left too far, shift to the right again to end. I do. To shift the screen to the left or right,
4 to the counter 4, the signals HP, HENB, and HP2 are simultaneously shifted in phase by the same amount by the control signal HCCT.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIGS. 1, 6, 7, 9, and 10. FIG. In the present embodiment, it is assumed that the number of effective display pixels of the input signal source is exactly the same as the number of effective display pixels of the liquid crystal display unit. Therefore, there is no need for scan conversion in the horizontal and vertical directions. Therefore, the conversion rate of the scan conversion circuit is set to 1 in both the horizontal and vertical directions by the control signal SCT from the CPU 14. Also in the following description, the number of effective pixels of the liquid crystal display unit 2 in FIG.
The number of pixels is 24 and the vertical is 768 lines. Therefore, the enable signal ENBP indicating the display period of the liquid crystal display device is 1024 CLK in the H period when viewed at the horizontal rate and 768 lines in the H period when viewed at the vertical rate.

The correlation between HF, HB, VF, and VB, the position on the screen, and the sampling clock frequency is as shown in FIG. In the present embodiment, since the timing is limited to the time when scan conversion is not necessary, if a video signal that displays the entire screen is input, (VF, VB)
Cannot be (L, L) or (H, H).

When (HF, HB) is (L, L), that is, when it is detected that the horizontal size is small,
This means that the frequency of the A / D conversion sampling clock ADCK is lower than the dot clock frequency of the signal source. This is because, for example, the number of dot clocks per horizontal period on the signal source side is 1200, and the effective display portion is 1024 of them. This is sampled at a frequency lower than the dot clock frequency. That is, for example, when the frequency division ratio of the PLL 18 per one horizontal period is sampled as 1100, of the 1100 samples,
(1100 × 1024/1200) = approximately 938 samples constitute the effective display portion.
Is 1024 in this case,
The portion of −938 = 86 pixels is blanked, and from the user's perspective, the horizontal size appears to be small. When (HF, HB) = (H, H), that is, when it is detected that the horizontal size is large, contrary to the above, the sampling clock frequency is actually higher than the dot clock frequency of the signal source.

Next, an example of the flow of the automatic adjustment process according to the present embodiment will be described with reference to FIGS. 6, 7, and 10. FIG.

Also in this embodiment, the vertical adjustment is performed prior to the horizontal adjustment. The main part of the processing is exactly the same as in FIG. 6 in the first embodiment. For vertical adjustment, FIG. 7 in Embodiment 1 can be used as it is. However, in the case of the present embodiment, (VF, VB) is (L, L) or (H, H) as described above.
It will not be.

FIG. 10 shows the CPU 1 according to this embodiment.
4 shows the flow of the horizontal adjustment to be performed. The difference from FIG. 8 in the first embodiment is that the horizontal size adjustment is performed not by changing the setting of the scan conversion circuit 1 but by changing the multiplication factor setting of the PLL circuit 18. is there.

[0043]

As described above, according to the present invention, it is not necessary to know in advance the method of the input signal (the number of effective display pixels, the horizontal synchronizing frequency, the vertical synchronizing frequency, the dot clock frequency). Provided is an automatic position size adjustment circuit that automatically adjusts the position, size, and A / D conversion sampling clock frequency of a screen so that just scan is automatically performed at various timings in all video displays. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an automatic position size adjustment circuit according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart of each signal according to the first embodiment of the present invention;

FIG. 3 is a timing chart of each signal according to the first embodiment of the present invention;

FIG. 4 is a timing chart of each signal according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a correlation between a detection signal and a screen state according to the first embodiment of the present invention.

FIG. 6 is a control flow diagram (main) according to the first embodiment of the present invention;

FIG. 7 is a control flowchart (vertical adjustment) according to the first embodiment of the present invention;

FIG. 8 is a control flowchart (horizontal adjustment) according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a correlation between a detection signal and a screen state according to the second embodiment of the present invention.

FIG. 10 is a control flowchart (horizontal adjustment) according to the second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 scan conversion circuit 2 liquid crystal display device 3 OR 4, 5 counter 6 AND 7 to 13 flip-flop 14 CPU 15 to 17 A / D converter 18 PLL circuit

Claims (4)

[Claims] 1. The phase of a digital RGB signal scan-converted so as to be displayed on a liquid crystal display unit is compared with the phase of an enable signal indicating a display period of the liquid crystal display unit. A liquid crystal display device wherein a display position and a display size of an image on the liquid crystal display section are automatically adjusted by changing a conversion rate and a phase of the enable signal. 2. An analog RGB signal generated from a signal source.
An A / D converter for converting a signal into a digital RGB signal, a PLL circuit for generating a sampling clock for the A / D converter, and one of the digital RGB signals so as to enable display on a liquid crystal display unit. A scan conversion circuit for converting the number of data per horizontal period and the number of lines per vertical period; a counter for generating an enable signal indicating a display period of the liquid crystal display unit; OR for ORing the most significant bit of each color to determine if
A circuit, a flip-flop for comparing a phase of a signal output by the OR circuit with a phase of the enable signal, and a conversion ratio of the scan conversion circuit and the enable signal according to an output value of the flip-flop. 2. The liquid crystal display device according to claim 1, further comprising a CPU for changing the setting of the counter. 3. An A / D converter for converting an analog RGB signal into a digital RGB signal for displaying on a liquid crystal display unit, a signal source which generates a frequency of a sampling clock at the time of the A / D conversion and generates the analog RGB signal. In order to completely match the dot clock frequency, the phase of the digital RGB signal is compared with the phase of an enable signal indicating the display period of the liquid crystal display unit, and the frequency of the sampling clock is automatically adjusted according to the phase comparison result. A liquid crystal display device characterized by adjustment. 4. An analog RGB signal generated from a signal source.
An A / D converter for converting a signal into a digital RGB signal, a PLL circuit for generating a sampling clock of the A / D converter, and a counter for generating an enable signal indicating a display period of the liquid crystal display unit And an OR circuit for ORing the most significant bit of each color to determine whether the digital RGB signal is at a certain level or higher, and comparing the phase of the signal output from the OR circuit with the phase of the enable signal. And the PLL according to an output value of the flip-flop.
4. The liquid crystal display device according to claim 3, further comprising a CPU for changing a multiplication factor setting in the circuit.