JP2000180885A - Array substrate and its inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a rise of a manufacturing cost as much as possible and to easily perform an inspection. SOLUTION: In an array substrate provided with first, second device arrays 2, 3 respectively provided with pixel area parts 24a, 24b arranging plural pixel electrodes in matrix, drive circuit parts 12a, 12b, 13a, 13b containing a shift register serial/parallel converting a serial image signal inputted based on a control signal and input terminals 6, 7 for inputting the control signal to a drive circuit, connection wiring 11a connecting one output of the shift register of the first device array to the input terminal of the second device array is provided on the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an array substrate and a method for inspecting the same.

[0002]

2. Description of the Related Art In recent years, memories and liquid crystal display devices (hereinafter referred to as L
An array substrate used for a CD has a structure called “multi-cavity” (or “multi-cavity”) for extracting a plurality of array substrates from one large-format array substrate in order to reduce production cost. It has become mainstream.

FIG. 7 shows a conventional example of a large-format array substrate having a multi-cavity structure. This conventional large-format array substrate 100 is L
A plurality of (four in the drawing) LCD device arrays 2, 3, 4, and 5 are individually and imposed on the large-format array substrate. Here, “independent” means that the device arrays are not electrically connected to each other.

The device array 2 has a plurality of input / output terminals 6
And a signal line driving circuit 12a and a scanning line driving circuit 12b
And a pixel region 24a. Pixel region section 24
a denotes a plurality of scanning lines 25, a plurality of signal lines 26 provided so as to intersect these scanning lines 25, and a plurality of scanning lines 2.
TFT (Thin) provided at each intersection of the signal line 5 and the signal line 26.
A switching element 27 comprising a film transistor (Film Transistor);
A capacitor 28 is provided corresponding to each switching element 27 and stores signal data received via the corresponding switching element. Drive circuits 12a and 12
b denotes a dynamic shift register having a configuration in which D-type flip-flops (hereinafter, also referred to as DFFs) 19 are connected in cascade, and the power, control signal, and logic input through the input / output terminal 6 are provided. The pixel region 24a is driven based on the signal. FIG. 9A shows a configuration of a shift register using the DFF, and FIG. 9B shows a timing chart of the operation of the shift register.

The device array 3 has a plurality of input / output terminals 7
And the signal line driving circuit 13a and the scanning line driving circuit 13b
And a pixel region 24b. Pixel region section 24
b has the same configuration as the pixel region 24a. Each of the drive circuits 13a and 13b has a dynamic shift register having a configuration in which DFFs 20 are cascaded,
The pixel region 24b is driven based on the power, control signal, and logic signal input via the input / output terminal 7.

The device array 4 has a plurality of input / output terminals 8
And a signal line driving circuit 14a and a scanning line driving circuit 14b
And a pixel region 24c. Pixel region section 24
c has the same configuration as the pixel region 24a. Each of the drive circuits 14a and 14b has a dynamic shift register having a configuration in which DFFs 21 are cascaded, and drives the pixel region 24c based on the power, control signal, and logic signal input through the input / output terminal 8. Drive.

The device array 5 has a plurality of input / output terminals 9
And the signal line driving circuit 15a and the scanning line driving circuit 15b
And a pixel region 24d. Pixel region section 24
d has the same configuration as the pixel region 24a. Each of the drive circuits 15a and 15b has a dynamic shift register having a configuration in which DFFs 22 are connected in cascade, and the power input through the input / output terminal 9, the control signal,
And drives the pixel region 24d based on the logic signal.

Next, a method of inspecting the conventional large-format array substrate 100 will be described with reference to FIG. First, the substrate 100 is placed on the stage 201 of the inspection device. Then, the probe 208 connected to the head 205 of the inspection device is
The input / output terminal 6 of the device array 2 is brought into contact. Thereafter, power, control signals, and logic signals are input from the head 205 via the probe 208 and the input / output terminal 6 to the drive circuit 12a, and the drive circuit 12
a or the drive circuit 12b is operated.

The inspection of the shift register constituting the drive circuit 12a or 12b is performed based on the output waveform of the last stage DFF constituting the shift register. This output waveform can be obtained, for example, via the input / output terminal 6. The other parts are also inspected based on the output waveform obtained via the input / output terminal 6.

[0010] After all the inspection items are completed, the stage 2 again
01 and the head 205 are relatively moved to
8 is brought into contact with the input / output terminal 7 of the device array 3 to inspect the device array 3.

Hereinafter, the inspection of the device arrays 4 and 5 is sequentially performed in the same manner.

[0012]

As described above, conventionally, device arrays are inspected one by one in order. Therefore, the number of device arrays imposed on one large-format array substrate 100 (hereinafter, also referred to as “imposition number”)
When the number of devices increases, the manufacturing cost becomes more advantageous, but on the contrary, there is a problem that the entire inspection time of the device array becomes longer.

As a countermeasure, there is a method in which a plurality of device arrays such as two or three are simultaneously probed (a fine needle is brought into contact with an input terminal of the device), a circuit is operated, and a test is performed at the same time. However, this method also has the following problems.

1. At the same time, a fine needle set for inspection (called a probe card) for use in inspection is required for each product, which is costly. Simply measuring two device arrays at a time would require two sets of probe cards.

2. There is a technical limit in probing a large number of test terminals at the same time. In addition, since several types of device arrays are often inspected by one test apparatus, when switching the device arrays to be inspected, it takes time to prepare for setup change, and the efficiency of the inspection process is low.

3. There is a difficulty in processing inspection result data obtained from a large number of device arrays in parallel.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an array substrate capable of suppressing an increase in manufacturing cost as much as possible and performing an inspection easily, and an inspection method thereof. Aim.

[0018]

According to a first aspect of the array substrate according to the present invention, a pixel region in which a plurality of pixel electrodes are arranged in a matrix and a serial image signal input based on a control signal are serially parallelized. A drive circuit unit including a shift register to be converted, and an input terminal for inputting the control signal to the drive circuit, wherein an array substrate provided on a substrate with first and second device arrays each having A connection wiring for connecting one output of the shift register of the first device array to the input terminal of the second device array is provided on a substrate.

It is preferable that the second device array includes an output terminal connected to one output of a shift register of the device array.

It should be noted that an amplifier circuit may be provided in the middle of the connection wiring.

In the above-described method for inspecting an array substrate, a signal is input to an input terminal of the first device array, and the quality of the device array is determined based on a signal obtained from an output terminal of the second device array. Is determined.

After the quality of the device array is determined, the array substrate is cut and divided into device arrays.

According to a second aspect of the array substrate according to the present invention, there is provided a pixel region in which a plurality of pixel electrodes are arranged in a matrix, and a shift register for serial-to-parallel conversion of a serial image signal input based on a control signal. And a drive circuit unit including: a drive circuit unit; and an input terminal for inputting the control signal to the drive circuit. A first connection wiring for connecting the input terminal of the array and the input terminal of the second device array is provided on a substrate.

Each of the drive circuit sections of the device array includes a scan line drive circuit for sequentially selecting the pixel electrodes, and one output of the scan line drive circuit of the first device array and the second scan line drive circuit of the first device array. A second connection wiring for connecting an input of the scanning line driving circuit of the device array is provided on the substrate.

Each of the drive circuit sections of the device array includes a scan line drive circuit for sequentially selecting the pixel electrodes, and an input of the scan line drive circuit of the first device array and the second drive circuit section. It is preferable that a second connection wiring connecting the input of the scanning line drive circuit of the device array be provided on the substrate.

Each of the drive circuit sections of the device array includes a scan line drive circuit for sequentially selecting the pixel electrodes, and one output of the scan line drive circuit of the first device array and the second scan line drive circuit of the second device array. A second connection line for connecting an input of the scanning line driving circuit of the device array; an input of the scanning line driving circuit of the first device array; and the scanning line driving circuit of the second device array A third connection line for connecting the first and second input lines, and control means for selectively conducting one of the second connection line and the third connection line and cutting off the other, on the substrate. Is preferred.

It should be noted that an amplifier circuit may be provided in the middle of the connection wiring.

In the above method for inspecting an array substrate, the control means may be operated to make the third connection wiring conductive, and a signal may be input to an input terminal of the first device array, and Writing data to the pixel area portions of the first and second device arrays; operating the control means to make the second connection wiring conductive; and applying a signal to an input terminal of the first device array. And sequentially reading data from the pixel electrodes of the first and second device arrays, and determining the acceptability of the first and second device arrays based on the read data. And

After the quality of the first and second device arrays is determined, the array substrate is cut and divided into device arrays.

[0030]

FIG. 1 shows the configuration of a first embodiment of a large-sized array substrate according to the present invention. The array substrate 1 according to the first embodiment is used for an LCD.
LCD device arrays 2, 3, 4, and 5, a plurality of wirings 11a, 11b, 11c, and 11d for electrically connecting these device arrays, and pads 16 are formed. That is, the large-format array substrate 1 of the present embodiment is different from the conventional large-format array substrate 100 shown in FIG. 7 in that the wirings 11a, 11b, 11c, 11d and the pads 16
Are newly provided.

The device array 2 has a plurality of input / output terminals 6
And a signal line driving circuit 12a and a scanning line driving circuit 12b
And a pixel region 24a. Pixel region section 24
a denotes a plurality of scanning lines 25, a plurality of signal lines 26 provided so as to intersect these scanning lines 25, and a plurality of scanning lines 2.
A switching element 27 formed of a TFT provided at each intersection of the signal line 5 and the signal line 26, and a capacitor 28 provided corresponding to each switching element 27 and storing signal data received via the corresponding switching element. Have. Each of the driving circuits 12a and 12b has a dynamic shift register in which DFFs (D-type flip-flops) 18 are connected in cascade, and the power, control signals, and logic signals input via the input / output terminal 6 are provided. The pixel region 24a is driven based on (data).

The device array 3 includes a plurality of input / output terminals 7
And the signal line driving circuit 13a and the scanning line driving circuit 13b
And a pixel region 24b. Pixel region section 24
b has the same configuration as the pixel region 24a. Each of the drive circuits 13a and 13b has a dynamic shift register having a configuration in which DFFs 20 are cascaded,
The pixel region 24b is driven based on the power, control signal, and logic signal (data) input via the input / output terminal 7.

The device array 4 has a plurality of input / output terminals 8
And a signal line driving circuit 14a and a scanning line driving circuit 14b
And a pixel region 24c. Pixel region section 24
c has the same configuration as the pixel region 24a. Each of the drive circuits 14a and 14a has a dynamic shift register having a configuration in which DFFs 21 are cascaded,
The pixel region 24c is driven based on the power, control signal, and logic signal (data) input via the input / output terminal 8.

The device array 5 has a plurality of input / output terminals 9
And the signal line driving circuit 15a and the scanning line driving circuit 15b
And a pixel region 24d. Pixel region section 24
d has the same configuration as the pixel region 24a. Each of the drive circuits 15a and 15b has a dynamic shift register having a configuration in which DFFs 22 are connected in cascade, and the power input through the input / output terminal 9, the control signal,
And drives the pixel region 24d based on the logic signal.

The pad 16 is provided near the input / output terminal 6 of the device array 2. The wiring 11a connects the output terminal 6 of the device array 2 and the input terminal 7 of the device array 3, and the wiring 11b connects the output terminal 7 of the device array 3.
And the input terminal 8 of the device array 4 are connected. Wiring 1
1c connects the output terminal 8 of the device array 4 to the input terminal 9 of the device array 5, and the wiring 11d connects the output terminal 9 of the device array 5 to the pad 16. Therefore, in this embodiment, as shown in FIG. 2, the signal line drive circuits 12a, 13a, 14a, 15a or the scan line drive circuits 12b, 13b, 14b, 15b of each of the device arrays 2, 3, 4, 5 are provided. Are connected in cascade by wirings 11a, 11b, 11c, and 11d. The wirings 11a, 1
1b, 11c, and 11d are formed in a region of the large-format array substrate 1 excluding regions where the device arrays 2, 3, 4, and 5 are formed, that is, in a peripheral region 10.

The input / output terminals to which the power of the device arrays 2, 3, 4, and 5 are supplied are commonly connected by power supply wiring (not shown) formed in the peripheral region 10 of the array substrate 1. Similarly, the device arrays 2, 3,
Input / output terminals for receiving clock signals supplied to the fourth and fifth drive circuits 12a, 13a, 14a, and 15a are commonly connected by wiring (not shown) formed in the peripheral region 10 of the array substrate 1.

Next, a method of inspecting the large-sized array substrate 1 according to the first embodiment will be described with reference to FIG. First, the array substrate 1 is mounted on the stage 201 of the inspection device for inspecting the array substrate 1 (see FIG. 3). Subsequently, the probe 208 connected to the head 205 of the inspection apparatus is brought into contact with the input / output terminal 6 and the pad 16 of the device array 2. Thereafter, power, a control signal, and a logic signal are input from the head 205 via the probe 208 and the input / output terminal 6 to the signal line driving circuit 12a. Then, since the shift registers constituting the signal line driving circuits 12a, 13a, 14a, 15a or the scanning line driving circuits 12b, 13b, 14b, 15b are cascade-connected, all the signal line driving circuits 12a, 13a, 14a, 15a or all the scanning line driving circuits 12b, 13b, 14b, 15
b operates sequentially, and all the drive circuits operate. Then, the output terminal 9 of the device array 5 and the wiring 11
The drive circuit 12a, 13a, 14a, 15a or the scan line drive circuit 12b, 13b, 14b, 15b operates normally by monitoring the output of the device array 5 obtained through the pad 205 and the pad 16 using the head 205. Is determined.

The start pulse used for this inspection is a signal line drive circuit 12a, 13a, 14a, 15a
Or the scanning line driving circuits 12b, 13b, 14b, 15b
, And clocks, electric power, and the like are sent in parallel by wires (not shown).

As described above, in the inspection of the array substrate of the present embodiment, each device array on the array substrate can be inspected at a time by using an inspection head corresponding to one device array. . For this reason, the inspection can be easily performed, and the inspection time can be reduced to about 1/4 as compared with the conventional case. In addition, a wiring 11 is provided in a peripheral area of each device array on a conventional array substrate.
Since a to d and the pad 16 may be provided in the same process, an increase in manufacturing cost can be suppressed as much as possible.

As in the case of the device array 2, pads are provided near the input terminals of the other device arrays 3, 4, and 5, and the pads and the output terminals of the corresponding device arrays are connected by wiring. If the drive circuit 12
a, 12b, 13a, 13b, 14a, 14b, 15
If any one of a and 15b does not operate normally, it is possible to inspect each drive circuit, and it is possible to increase the yield of the device array.

In the above embodiment, the wiring 11
When the lengths a, 11b, 11c, and 11d are long, the waveforms transmitted through these wirings 11a, 11b, 11c, and 11d are attenuated or rounded. In this case, FIG.
As shown in the figure, each wiring 11a, 11b, 11c, 11d
The above-mentioned problem can be solved by installing the amplifier 23 in FIG.

FIG. 5 shows the configuration of an array substrate according to a second embodiment of the present invention.

The array substrate 1A according to the second embodiment includes a plurality (two in the drawing) of LCD device arrays 2 and 3, and a plurality of wirings 17, 17 for electrically connecting these device arrays. 18a, 18b, and 18c, a switch circuit 50, and a pad 60.

The device array 2 has a plurality of input / output terminals 6a.
, Input terminals 6b and 6c, a signal line driving circuit 12a and a scanning line driving circuit 12b, and a pixel region 24a. The pixel region 24a includes a plurality of scanning lines 25,
A plurality of signal lines 26 provided so as to intersect these scanning lines, a switching element 27 composed of a TFT provided at each intersection of the scanning line 25 and the signal line 26, and a switching element corresponding to each switching element. A capacitor 2 for storing signal data received via a corresponding switching element
8 is provided.

The signal line drive circuit 12a drives the signal line 26 of the pixel area 24a based on the power input via the plurality of input / output terminals 6a, the clock X _ck , the start pulse X _ST , and the data DATA. . The scanning line driving circuit 12b drives the scan lines 25 of the pixel region portion 24a on the basis of the clock Y _ck and a start pulse Y _ST is inputted through the input terminal 6b and 6c. The driving power of the scanning line driving circuit 12b is supplied from the signal line driving circuit 12a via a wiring (not shown).

The device array 3 has a plurality of input / output terminals 7a.
, Input terminals 7b and 7c, a signal line driving circuit 13a and a scanning line driving circuit 13b, and a pixel region 24b. The pixel region 24b has the same configuration as the pixel region 24a.

The signal line drive circuit 13a receives the signal, the clock, the start pulse, and the data input through the plurality of input / output terminals 7a based on the signal line 2 of the pixel region 24b.
6 is driven. Further, the scanning line driving circuit 12b, based on the clock and the start pulse input via the input terminals 7b and 7c, scans the scanning lines 25 of the pixel region 24b.
Drive. The driving power of the scanning line driving circuit 13b is supplied from the signal line driving circuit 13b via a wiring (not shown).

Each of the plurality of input / output terminals 6a of the device array 2 is connected to the corresponding input / output terminal 7a of the device array 3 by a wiring 17.

The switch circuit 50 has a switch 51, an inverter 52, and a switch 53. The switch 51 is connected to the input terminals 6 b and 6 c of the device array 2 and the input terminals 7 and 6 of the device array 3 based on a switch signal (switching command) SW input via the pad 60.
b and 7c are connected or disconnected through the wiring 18a. The inverter 52 inverts the switch signal SW. The switch 53 is the inverter 5
2, the wiring 18b connected to the output terminal of the scanning line driving circuit 12b and the wiring 18c connected to the input terminal of the scanning line driving circuit 13b are connected or disconnected. .

Therefore, the switches 51 and 53 are configured to always perform the opposite operations. When the switch 51 is ON, the switch 53 is OFF, and when the switch 51 is OFF, the switch 53 is OFF. It is in the ON state.

The wirings 17, 18a, 18b, 18c
The switch circuit 50 is formed in an area (peripheral area of the device array) other than the area where the device arrays 2 and 3 are formed on the array substrate 1A. The pad 60 is preferably provided near the input terminals 6b and 6c.

Next, the array substrate 1 of the second embodiment
The inspection method of A will be described. This inspection method uses the array substrate 1
A of the pixel regions 24 of the device arrays 2 and 3 formed in A
This is a method for inspecting a and 24b using an inspection apparatus having a write / read circuit 30 shown in FIG. The write / read circuit 30 includes a switch 31 and a sense amplifier 32
And an A / D converter 32. Switch 3
1 has three terminals 31a, 31b, and 31c;
The configuration is such that the connection with 1a is switched to the writing terminal 31b or the reading terminal 31c. Terminal 31 during inspection
a is connected to any one of the device arrays 2 and 3, for example, the drive circuit 12 of the device array 2 via the input / output terminal 6 a. Write-side terminal 31b
Is connected to a signal source 40, and the reading side terminal 31c is connected to an A / D converter 33 via a sense amplifier 32.

When inspecting the array substrate 1A, the array substrate 1A is placed on a stage (not shown) of the inspection apparatus as in the case of the first embodiment. Subsequently, a probe (not shown) connected to the head (not shown) of the inspection apparatus
Are input / output terminals 6a, input terminals 6b,
6c and the pad 60. Thereafter, drive power is supplied from the head to the signal line drive circuit 12a via the probe and the input / output terminal 6a. Then, the wiring 17
Drive power is also supplied to the signal line drive circuit 13a via the input / output terminal 7a. The scanning line driving circuits 12b and 13b are also supplied with driving power from the signal line driving circuits 12a and 13a via wiring (not shown).

Next, the switch 31 of the write / read circuit 30
Is connected to the write-side terminal 31b, a switch signal SW is sent from the head to the switch circuit 50 via the probe and the pad 60, and the switch 51 is turned on and the switch 53 is turned off. Subsequently, the clock X _ck , the start pulse X _ST , and the image signal data output from the signal source 40 are transmitted from the head of the inspection apparatus to the signal line driving circuit 12 via the input terminal 6a.
sends out to a, the input terminal 6b, through 6c transmits the even clock Y _ck and a start pulse Y _ST to the scanning line driving circuit 12b from the head. At this time, the clock X _ck , the start pulse X _ST , and the image signal data are transmitted to the device 3 via the wiring 17 and the input / output terminal 7a.
Is also transmitted to the signal line driving circuit 13a. The clock _Yck and the start pulse _YST are also sent to the scanning line drive circuit 13b via the switch 51 and the wiring 18a.

Then, in the device array 2, the TFTs 27 connected to the scanning lines 25 selected by the scanning line driving circuit 12b are turned ON, and these TFTs 27 are turned on.
The image signal data is sequentially written to the capacitor 28 connected to the device array 3 by the signal line driving circuit 12a, and the device array 3
In this case, the TFTs 27 connected to the scanning lines 25 selected by the scanning line driving circuit 13b are turned ON, and the image data is sequentially written into the capacitors 28 connected to these TFTs 27 by the signal line driving circuit 13a. That is, the same data is simultaneously written to the corresponding pixels in the device array 2 and the device array 3. For this reason, the writing time can be reduced to half as compared with the conventional case where the image signal data is separately written into the device arrays 2 and 3.

Next, a method of reading the written image signal data will be described.

First, a switch signal SW is sent from the head to the switch circuit 50 via the pad 60, and the switch 51 is turned off and the switch 53 is turned on. Then, the scanning line driving circuit 13 of the device array 3
The input terminal b is disconnected from the input terminals 6b and 6c of the device array 2 by the switch 51, and is connected to the output terminal of the scanning line drive circuit 12b of the device array 2 and the wiring 18b.
The connection is made via the switch 53 and the wiring 18c.

Next, switch 31 of write / read circuit 30
Is connected to the reading-side terminal 31c. Subsequently, the clock Y _ck and the start pulse Y _ST are sent from the head of the inspection apparatus via the input terminals 6b and 6c to the scanning line drive circuit 12b of the device array 2, and the clock X _ck and the clock X _ck via the input / output terminal 6a. and it sends a start pulse X _ST to the signal line driving circuit 12a of the device array 2. Then, the scanning line 2 selected by the scanning line driving circuit 12b
The TFTs 27 connected to the TFTs 5 are turned on, the data stored in the capacitors 28 connected to these TFTs 27 are sequentially selected by the signal line drive circuit 12a, and the data is read to the write / read circuit 30 via the input / output terminal 6a. Sent out.
Then, these data are detected by the sense amplifier 32, and the detected data is converted into digital data by the A / D converter 33 and read.

In this manner, the scanning lines 25 of the device array 2 are sequentially selected by the scanning line driving circuit 12b based on the clock Y _ck and the start pulse Y _ST , and the signal lines are driven by the signal line driving circuit 12a based on the clock X _ST. If 26 is selected sequentially, all data written in the pixel area 24a of the device array 2 will be read.

When the reading of the data written in the device array 2 is completed, the clock Y _ck and the start pulse Y _ST
Is sent from the output end of the scanning line driving circuit 12b to the scanning line driving circuit 13b of the device array 3 via the wiring 18b, the switch 53, and the wiring 18c. At this time, the clock X _ck and the start pulse X _ST are transmitted to the input / output terminal 7a of the device array 3 via the wiring 17. The scanning line driving circuit 13b sequentially selects the scanning lines 25 of the device array 3 based on the clock Y _ck and the start pulse Y _ST , and the signal line driving circuit 13a operates based on the clock X _ck and the start pulse X _ST. By sequentially selecting the signal lines of the array 3, the data written in the pixel region 24b of the device array 3 is detected and read out by the inspection device via the input / output terminal 7a, the wiring 17, and the input / output terminal 6a. You.

As described above, according to the present embodiment, the device arrays 2 and 3 are formed using one inspection head.
, Image signal data can be simultaneously written into the pixel region portions 24a and 24b, so that the inspection can be performed and the inspection time can be shortened. Further, the array substrate 1A of the present embodiment is formed by connecting the wiring 1 to a conventional array substrate.
7, 18a, 18b, 18c, the switch circuit 50, and the pad 60 are provided, so that an increase in manufacturing cost can be suppressed as much as possible.

The wirings 17, 18a, 18b, 18c
If the transmitted waveform is attenuated or rounded, the first
Similarly to the case described in the embodiment, the wirings 17, 18
Amplifying circuits may be provided in a, 18b, and 18c.

In the array substrates of the first and second embodiments, after the inspection is completed, the peripheral region of each device array is cut and divided into individual device arrays to obtain good devices. Can be.

[0064]

As described above, according to the present invention,
An increase in manufacturing cost can be suppressed as much as possible, and inspection can be performed easily, and inspection time can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an array substrate according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating connection of a driving circuit of a device array formed on the array substrate according to the first embodiment;

FIG. 3 is a view for explaining an array substrate inspection method according to the first embodiment;

FIG. 4 is a block diagram illustrating a modification of the first embodiment.

FIG. 5 is a diagram showing a configuration of an array substrate according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of an inspection circuit used for inspecting an array substrate according to the second embodiment.

FIG. 7 is a diagram showing a configuration of a conventional array substrate.

FIG. 8 is a diagram illustrating a conventional array substrate inspection method.

FIG. 9 illustrates a structure of a driving circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Array board 1A Array board 2,3,4,5 Device array 6,7,8,9 Input / output terminal 10 Peripheral area 11a-11d, 17,18a-18c Wiring 12a, 13a, 14a, 15a Signal line drive circuit 12b , 13b, 14b, 15b Scan line drive circuit 16 Pad 19, 20, 21, 22 D-type flip-flop 23 Amplification circuit 24a to 24d Pixel region section 25 Scan line 26 Signal line 27 TFT 28 Capacitance 30 Write / read circuit 31 Switch 31a To 31c terminal 32 sense amplifier 33 A / D converter 40 signal source 50 switch circuit 60 pad

Claims (12)

[Claims] A driving circuit including a shift register for serial-to-parallel conversion of a serial image signal input based on a control signal; An input terminal for inputting to the drive circuit, an array substrate provided on the substrate with first and second device arrays each having an input terminal; one output of the shift register of the first device array; An array substrate, comprising: connection wiring for connecting the input terminal of the second device array to the input terminal. 2. The array substrate according to claim 1, wherein said second device array includes an output terminal connected to one output of a shift register of said device array. 3. The array substrate according to claim 1, wherein an amplifier circuit is provided in the middle of the connection wiring. 4. The method for inspecting an array substrate according to claim 2, wherein a signal is input to an input terminal of the first device array.
A method for inspecting an array substrate, wherein the quality of the device array is determined based on a signal obtained from an output terminal of the second device array. 5. After deciding the quality of the device array,
5. The method according to claim 4, wherein the array substrate is cut and divided into device arrays. 6. A drive circuit section including a pixel area section in which a plurality of pixel electrodes are arranged in a matrix, a shift register for serial-to-parallel conversion of a serial image signal input based on a control signal, and An array substrate having, on a substrate, first and second device arrays each having an input terminal for inputting to the drive circuit, wherein the input terminal of the first device array and the second device An array substrate, comprising: first connection wiring for connecting the input terminal of the array to the substrate. 7. Each of the drive circuit sections of the device array includes a scan line drive circuit for sequentially selecting the pixel electrodes, one output of the scan line drive circuit of the first device array, and the second 7. The array substrate according to claim 6, further comprising a second connection wiring for connecting an input of the scanning line drive circuit of the device array to the substrate. 8. Each of the drive circuit sections of the device array includes a scan line drive circuit for sequentially selecting the pixel electrodes, and an input of the scan line drive circuit of the first device array and the second drive circuit section. 7. The array substrate according to claim 6, further comprising a second connection wiring for connecting an input of the scanning line drive circuit of the device array to the substrate. 9. Each of the drive circuit units of the device array includes a scan line drive circuit for sequentially selecting the pixel electrodes, one output of the scan line drive circuit of the first device array, and the second A second connection line for connecting an input of the scanning line driving circuit of the device array; an input of the scanning line driving circuit of the first device array; and the scanning line driving circuit of the second device array A third connection line connecting the input of the second connection line and a control unit for selectively conducting one of the second connection line and the third connection line and cutting off the other of the second connection line and the third connection line. 7. The array substrate according to claim 6, wherein: 10. The array substrate according to claim 6, wherein an amplifier circuit is provided in the middle of the connection wiring. 11. The inspection method of an array substrate for inspecting an array substrate according to claim 10, wherein the step of operating the control means to make the third connection wiring conductive includes the step of: Input a signal to the input terminal,
A step of writing data into a pixel area of the first and second device arrays; a step of operating the control means to make the second connection wiring conductive; and an input terminal of the first device array And sequentially reading data from the pixel electrodes of the first and second device arrays, and determining pass / fail of the first and second device arrays based on the read data. A method for inspecting an array substrate, comprising: 12. After the quality of said first and second device arrays is determined, said array substrate is cut,
2. The device according to claim 1, wherein the device is divided into device arrays.
2. The method for inspecting an array substrate according to 1.