JP2000174284A - Thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation in the properties as much as possible. SOLUTION: A thin film transistor is provided with an active layer 4 of non single crystal silicon which is formed on a transparent insulating substrate, and has a first conductivity type channel region 6 and a source region 7, and a drain region 8 of second conductivity type which is different from the first conductivity type; a gate insulating film 12 formed on the active layer 4; and a gate electrode 14 formed on the gate insulating film 12. The end of gate electrode 12 of the drain side is in the offset position from the junction between the drain region 8 and the channel region 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor.

[0002]

2. Description of the Related Art MOS type field effect transistors (MOS)
FETs are used in thin film transistors (hereinafter also referred to as TFTs) as pixel switching elements of active matrix type liquid crystal display devices, semiconductor integrated circuits, and the like. In the case of a TFT, polycrystalline silicon or amorphous silicon is often used for the active layer. Above all, most TFTs using polycrystalline silicon for the active layer have a gate-mounted structure (coplanar structure) due to the necessity of the polycrystalline silicon manufacturing method.

FIG. 4 shows a configuration of a conventional TFT. This conventional TFT uses an insulating transparent substrate (eg, a glass substrate).
Undercoat film 2 formed on 1 for example of SiO ₂ is formed. An active layer 3 made of polycrystalline silicon is formed on the undercoat film 2. The active layer 3 includes a channel region 5 provided at the center and impurity regions 9a and 9b formed so as to sandwich the channel region 5.
And a source region 7 and a drain region 8 formed outside these impurity regions 9a and 9b. A high concentration impurity of the same conductivity type is introduced into the source region 7 and the drain region 8. Further, impurity regions 9a, 9
b has a lower concentration than the source region 7 and the drain region 8 and an impurity of the same conductivity type as the source region 7 and the drain region 8 is introduced. That is, this TFT is LD
It has a D (Lightly Doped Drain) structure.

[0004] A gate insulating film 12 is formed on the active layer 3, and a gate electrode 14 is formed on the gate insulating film 12. On the gate electrode 14, an interlayer insulating film 16 is formed. Contact holes for connecting to the source region 7 and the drain region 8 are provided in the interlayer insulating film 16 and the gate insulating film 12, respectively.
A source electrode 17 and a drain electrode 18 connected to the source region and the drain region 8 via these contact holes are formed.

The gate electrode 14 is formed on the gate insulating film 12.
Are formed on the channel region 5 through the gate electrode. And
The end of the gate electrode 14 is at a position offset from the end of the source region 7 and the end of the drain region 8 by the width of the impurity regions 9a and 9b.

[0006]

As described above, in the conventional TFT, by adopting the LDD structure,
The electric field at the end of the drain region 8 is relaxed to suppress hot carriers.

However, a transparent insulating substrate such as a glass substrate used for a display device is inferior in shrinkage and dimensional accuracy as compared with a silicon wafer, and has a large external dimension, so that alignment at the time of exposure by a stepper or the like is required. The accuracy is not good.
For this reason, since the impurity regions 9a and 9b are formed using another mask, the width dimension of these regions 9a and 9b cannot be reduced to a predetermined value (for example, 3 μm) or less.

In addition, unless the sheet resistance of the impurity regions 9a and 9b is higher than the sheet resistance of the active layer when the TFT is on, the effect of reducing the electric field cannot be exhibited.

For these reasons, in the conventional TFT, the TF is reduced by the sheet resistance of the impurity regions 9a and 9b.
There is a problem that the field-effect mobility of T is reduced and the characteristics of the TFT are deteriorated.

[0010] The present invention has been made in view of the above circumstances, and has as its object to provide a thin film transistor capable of preventing deterioration of characteristics as much as possible.

[0011]

A thin film transistor according to the present invention is formed on a transparent insulating substrate, and has a channel region of the first conductivity type and the first conductivity type formed separately so as to sandwich the channel region. An active layer made of non-single-crystal silicon having source and drain regions of different second conductivity types, a gate insulating film formed on the active layer, and a gate electrode formed on the gate insulating film The end of the gate electrode on the drain side is located at a position offset from a junction surface between the drain region and the channel region.

Preferably, the active layer is formed of polycrystalline silicon.

It is preferable that an insulating film is provided between the transparent insulating substrate and the active layer.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a structure of an embodiment of a thin film transistor (hereinafter also referred to as TFT) according to the present invention.
Shown in The TFT according to this embodiment is used for a liquid crystal display device and has an outer dimension of 400 × 500 m.
undercoat film 2 on an insulating transparent substrate (glass substrate, for example) 1 m composed for example of SiO ₂ is formed. The undercoat film 2 is formed to prevent diffusion of impurities from the transparent substrate 1 and is formed of Si
In addition to the O ₂ film, a Si ₃ N ₄ film or a film of Si ₃ N ₄ and SiO ₂
May be used.

An active layer 4 made of polycrystalline silicon is formed on the undercoat film 2. The active layer 4 is provided substantially at the center and has a channel region 6 into which a p-type impurity is introduced, and a source region 7 and a drain region which are provided so as to sandwich the channel region 6 and into which an n-type impurity is introduced. 8 is provided.

The active layer 4 is covered with, for example, SiO
_A gate insulating film 12 of 2 is formed. Then, a gate electrode 14 is formed on the gate insulating film 12. The gate electrode 14 is formed on the channel region 6 with the gate insulating film 12 interposed therebetween. The end of the gate electrode 14 on the source region side is located on the source region 7, and the end on the drain region side is It is formed so as to be located on channel region 6.

Accordingly, the end of the gate electrode 14 on the side of the drain region and the end of the drain region 8 on the side of the gate electrode are offset from each other by △ x (≠ 0) as shown in FIG.

This gate electrode 14 is covered with an interlayer insulating film 16. Contact holes for connecting to the source region 7 and the drain region 8 are formed in the interlayer insulating film 16 and the gate insulating film 12, respectively, and a source electrode 17 and a drain electrode 18 are formed so as to fill the contact holes. ing.

Next, a method of manufacturing the TFT of this embodiment will be described. First, on a transparent insulating substrate 1, for example, to form an undercoat film 2 made of SiO ₂ using a chemical vapor phase reaction method or a sputtering method.

Subsequently, a polycrystalline silicon film to be the active layer 4 is formed on the undercoat film 2. This polycrystalline silicon film is formed, for example, by plasma CVD, LP
After an amorphous silicon film is first formed by a film forming method such as a CVD method or a sputtering method, boron is implanted with impurities for the purpose of controlling the threshold voltage of the TFT element. This implantation is performed by ion shower doping using B ₂ H ₆ (diborane) gas, and the boron implantation concentration is, for example, 1.2 × 10 ¹² cm ⁻² . Then, the amorphous silicon film is subjected to laser annealing to be polycrystallized. Further, as another forming method, for example, a polycrystalline silicon film is formed directly by a method of forming from amorphous silicon (seed) by solid phase growth or a plasma CVD method using SiH ₄ + SiF ₄ + H ₂ as a source gas. May be. It should be noted that an amorphous silicon film may be used as the active layer 4 in addition to the polycrystalline silicon film. The amorphous silicon film is formed by, for example, plasma CVD, L
It is formed by a film forming method such as a PCVD method or a sputtering method. It is effective that the above-described formation of the undercoat film 2 and the formation of the amorphous silicon film are performed continuously without being exposed to the atmosphere.

Next, the polycrystalline silicon film is etched into an island shape. The etching is performed by, for example, chemical dry etching (CDE) using CF ₄ + O ₂ gas. The etching conditions were as follows: 02 / CF4 flow ratio = 4, etching pressure = 40 Pa, microwave power supply = 800 W,
The substrate temperature is set to 60 ° C. Through such etching, the angle between the transparent substrate 1 and the side surface of the active layer 4 in the channel width direction becomes 30 degrees, and the trapezoidal active layer 4 is formed.

Next, an SiO ₂ film serving as the gate insulating film 12 is formed by using tetraethylorthosilicate (TEOS) + O ₂
Is formed by a plasma CVD method using as a source gas. As a method for forming the gate insulating film 12, instead of the plasma CVD method, other CV methods such as a normal pressure CVD method, an LPCVD method, an ECR plasma CVD method, and a remote plasma CVD method are used.
A method D, a sputtering method, or the like may be used. Also as a material gas other than TEOS + 0 ₂ gas may be used SiH ₄ + O _2. After the gate insulating film 12 is formed, annealing may be performed, for example, in a nitrogen atmosphere at 600 ° C. for 5 hours in order to further improve the film quality of the gate insulating film 12.

Next, a gate electrode 14 is formed on the SiO _{2 serving as the} gate insulating film 12. As a material of the gate electrode 14, a low resistance metal such as molybdenum-tungsten alloy (MoW) or aluminum (Al), polycrystalline silicon into which impurities are introduced, or the like is used. Next, the gate electrode 14
Is patterned into a predetermined shape by using a lithography technique. After forming the gate electrode 14 having a predetermined shape,
Using this gate electrode 14 as a mask, phosphorus (P), which is an n-type impurity, is doped into active layer 4 from a direction inclined at a predetermined angle with respect to the normal line of substrate 1, for example, at a dose of 5 × 10 ¹⁶ cm ^−2.
The source region 7 and the drain region 8
Is formed (see FIG. 2). Thereby, the gate electrode 14
, An offset region 6a into which an n-type impurity is not implanted is formed on the drain region 8 side.

When the n-type impurity is implanted, as shown in FIG. 3, a resist pattern 15 made of a photoresist used for patterning the gate electrode 14 is used.
Is performed, the width (offset amount Δx) of the offset region 6a can be made smaller than that in the case where the resist pattern 15 is not left as shown in FIG.

Thereafter, the ion-implanted phosphorus is activated by laser annealing or thermal annealing.

When a p-type channel TFT is manufactured, a p-type impurity such as boron (B) is ion-implanted. In this case, an n-type impurity is implanted in channel region 6.

Next, an interlayer insulating film 16 is formed on the entire surface, and contact holes connecting the drain region 8 and the source region 7 are opened in the interlayer insulating film 16 and the gate insulating film 12. Then, after a metal film such as Al is formed on the entire surface so as to fill the contact hole, the metal film is patterned to form a drain electrode 18 and a source electrode 17, thereby completing a TFT. After that, a passivation film made of, for example, a SiN film may be formed to protect the TFT element from absorption of moisture or the like.

The inventor manufactured a TFT in the above-described TFT manufacturing process by setting the thickness of the gate insulating film 12 to 1400 angstroms and the thickness of the gate electrode 14 to 2500 angstroms. Drain side offset length Δ
x was obtained by injecting impurities at an angle of 58 degrees with respect to the normal line of the substrate 1 to obtain 2 μm. The TFT has a channel width of 9 μm and a channel length of 4.5 μm. The measurement results of the field effect mobility of the TFT of this embodiment and the conventional TFT are as follows.

Electric field relaxation unit TFT field-effect mobility Drain-side offset structure (this embodiment) 104.9 (cm ² / Vsec) Source and drain both-side LDD structure (conventional) 95.5 (cm ² / Vsec) According to the present embodiment, the offset region 6a
Can be made smaller than before, and the field effect mobility of the TFT can be improved. Further, since the offset region 6a has a slightly boron-doped p-type, the off-state current can be extremely reduced. Thereby, deterioration of the characteristics can be prevented.

Further, unlike the conventional case, it is not necessary to form the impurity regions 9a and 9b having the LDD structure, so that the number of manufacturing steps can be reduced as compared with the conventional case, and the productivity can be improved. .

[0031]

As described above, according to the present invention, deterioration of characteristics can be prevented as much as possible.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the configuration of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an ion implantation method used for forming source / drain regions of a thin film transistor of the present invention.

FIG. 3 is a diagram illustrating an ion implantation method used for forming source / drain regions of a thin film transistor of the present invention.

FIG. 4 is a cross-sectional view illustrating a configuration of a conventional TFT.

[Explanation of symbols]

 Reference Signs List 1 substrate 2 undercoat film 3 active layer 4 active layer 5 channel region 6 channel region 6a offset region 7 source region 8 drain region 9a, 9b impurity region 12 gate insulating film 14 gate electrode 16 interlayer insulating film 17 source electrode 18 drain electrode

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2H092 JA24 JA34 JA41 JA46 KA04 KA05 KA10 MA05 MA06 MA08 MA15 MA19 MA29 MA30 NA21 NA27 PA01 5F110 AA06 AA08 AA30 CC02 DD13 DD14 DD17 DD24 EE03 EE04 EE06 EE09 FF02 FF28 FF31 GG02 FF28 GG15 GG28 GG29 GG32 GG45 GG47 GG52 HJ01 HJ14 HJ23 HL03 HM14 NN02 NN24 PP03 QQ04

Claims (3)

[Claims] A second conductive type source region and a drain formed on a transparent insulating substrate, the first conductive type being different from the first conductive type formed in a channel region of the first conductive type and insulated and separated so as to sandwich the channel region; An active layer made of non-single-crystal silicon having a region, a gate insulating film formed on the active layer, and a gate electrode formed on the gate insulating film, and a drain-side end of the gate electrode Is a position offset from a junction surface between the drain region and the channel region. 2. The thin film transistor according to claim 1, wherein said active layer is formed of polycrystalline silicon. 3. The thin film transistor according to claim 1, wherein an insulating film is provided between said transparent insulating substrate and said active layer.