JP2000174277A - Thin film transistor and its manufacture - Google Patents
Thin film transistor and its manufactureInfo
- Publication number
- JP2000174277A JP2000174277A JP10341347A JP34134798A JP2000174277A JP 2000174277 A JP2000174277 A JP 2000174277A JP 10341347 A JP10341347 A JP 10341347A JP 34134798 A JP34134798 A JP 34134798A JP 2000174277 A JP2000174277 A JP 2000174277A
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- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- phthalocyanine
- semiconductor layer
- manufacturing
- Prior art date
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- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、薄膜トランジスタ
に関わり、特にアクティブマトリクス液晶表示装置或い
はＩＣカードに関わる。The present invention relates to a thin film transistor, and more particularly, to an active matrix liquid crystal display device or an IC card.
【０００２】[0002]
【従来の技術】近年、薄膜トランジスタ（ＴＦＴ）に代
表されるスイッチング素子を用いたアクティブマトリク
ス液晶表示装置は、ＣＲＴと同等の高画質性能，低消費
電力，省スペースといった点からパソコンやワークステ
ーションなどのモニタとしても使用されつつある。2. Description of the Related Art In recent years, active matrix liquid crystal display devices using switching elements typified by thin film transistors (TFTs) have been used in personal computers and workstations because of their high image quality, low power consumption, and space saving equivalent to those of CRTs. It is also being used as a monitor.
【０００３】しかし、アクティブマトリクス液晶装置
は、ＣＲＴに比べて値段が高く、より普及していくため
には、一層の低価格化が求められている。低価格化の手
法の一つとして、簡便な作製法の有機薄膜トランジスタ
（有機ＴＦＴ）をアクティブ素子に適用することが考え
られている。現在のアモルファスシリコンＴＦＴの絶縁
層及び半導体層を作製するプラズマ化学気相成長（ＣＶ
Ｄ）装置、及び電極を作製するスパッタ装置は高額であ
る。[0003] However, active matrix liquid crystal devices are more expensive than CRTs, and in order to become more widespread, further reductions in prices are required. As one of the methods for reducing the cost, application of an organic thin film transistor (organic TFT) of a simple manufacturing method to an active element has been considered. Plasma-enhanced chemical vapor deposition (CV) for fabricating current amorphous silicon TFT insulation and semiconductor layers
D) An apparatus and a sputtering apparatus for producing an electrode are expensive.
【０００４】また、ＣＶＤ法では成膜温度が２３０〜３
５０度と高く、また、クリーニング等の保守を頻繁に行
う必要があり、スループットが低い。一方、有機ＴＦＴ
を作製する塗布装置，真空蒸着装置はＣＶＤ装置，スパ
ッタ装置と比べて安価であり、それらの装置では、成膜
温度が低く、メンテナンスが簡単である。そのため、液
晶表示装置に有機ＴＦＴを適用した際は、コストの大幅
な削減が期待できる。特開平10−93104 号公報には、フ
タロシアニン配位化合物を半導体層５０８に用いた有機
ＴＦＴ素子が記載されている。この公報では、銅，亜
鉛、或いはスズ等を中心金属に有する下記化２で表され
るフタロシアニン化合物を半導体に用いた有機ＴＦＴ素
子、及び半導体層の作製に基板温度を１２５〜１７５℃
に設定した真空蒸着法を用いた有機ＴＦＴ素子の作製方
法が開示されている。[0004] In the CVD method, the film forming temperature is 230 to 3
The temperature is as high as 50 degrees, and maintenance such as cleaning needs to be performed frequently, and the throughput is low. On the other hand, organic TFT
A coating apparatus and a vacuum vapor deposition apparatus for manufacturing are cheaper than a CVD apparatus and a sputtering apparatus. In these apparatuses, a film forming temperature is low and maintenance is simple. Therefore, when an organic TFT is applied to a liquid crystal display device, a significant reduction in cost can be expected. JP-A-10-93104 describes an organic TFT device using a phthalocyanine coordination compound for the semiconductor layer 508. In this publication, an organic TFT element using a phthalocyanine compound represented by the following formula 2 having copper, zinc, tin or the like as a central metal for a semiconductor, and a substrate temperature of 125 to 175 ° C. for producing a semiconductor layer:
Discloses a method for manufacturing an organic TFT element using a vacuum deposition method set in the above.
【０００５】しかし、この作製方法では基板加熱を行う
ため、蒸着終了後、基板を冷却するための時間を要し、
スループットが低くなってしまう。However, in this manufacturing method, since the substrate is heated, it takes time to cool the substrate after the deposition is completed.
The throughput will be low.
【０００６】[0006]
【化２】ＭＰｃ （Ｍ：中心金属、Ｐｃ：フタロシアニン環）Embedded image MPc (M: central metal, Pc: phthalocyanine ring)
【０００７】[0007]
【発明が解決しようとする課題】本発明の目的は、室
温、或いは室温に近い低温プロセスを用いた有機半導体
膜の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an organic semiconductor film using a low-temperature process at or near room temperature.
【０００８】[0008]
【課題を解決するための手段】上記目的は、基板，ゲー
ト電極，ゲート絶縁層，ソース電極，ドレイン電極、及
びフタロシアニン配位化合物層の半導体層からなる薄膜
トランジスタの製造方法において、前記半導体層の作製
過程において、溶媒処理を用いることにより達成され
る。The object of the present invention is to provide a method of manufacturing a thin film transistor comprising a substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, and a semiconductor layer of a phthalocyanine coordination compound layer. In the process, this is achieved by using a solvent treatment.
【０００９】また、本発明は、下記化１で表される金属
フタロシアニン化合物を半導体層に用いることを特徴と
する。Further, the present invention is characterized in that a metal phthalocyanine compound represented by the following formula 1 is used for a semiconductor layer.
【００１０】次に、本発明は、半導体層として、チタニ
ルフタロシアニンを用いることを特徴とする。ここで、
チタニルフタロシアニンは、波長８４１ｎｍに最大のピ
ークを有し、７１９ｎｍと８４１ｎｍの吸光度比が０.
６ 以下である吸収スペクトルを有することが望まし
い。Next, the present invention is characterized in that titanyl phthalocyanine is used as the semiconductor layer. here,
Titanyl phthalocyanine has a maximum peak at a wavelength of 841 nm, and has an absorbance ratio of 719 nm and 841 nm of 0.8.
It is desirable to have an absorption spectrum of 6 or less.
【００１１】ここでいう有機ＴＦＴとは、導電ゲート電
極，ゲート絶縁層，水平に間隔を置くソース電極とドレ
イン電極、及び有機半導体層によって構成される。有機
TFTは、ゲート電極に印加される電圧の極性に応じて、
蓄積状態または空乏状態の何れかで動作する。The organic TFT referred to here is composed of a conductive gate electrode, a gate insulating layer, horizontally spaced source and drain electrodes, and an organic semiconductor layer. Organic
TFTs are driven by the polarity of the voltage applied to the gate electrode.
It operates in either the accumulation state or the depletion state.
【００１２】本発明のゲート電極としては、電極形成プ
ロセスが簡便な塗布法を用いたポリアニリン，ポリチオ
フェン等の有機材料、或いは導伝性インクが望ましい。
また、既存のフォトリソグラフ法を用いて電極形成が可
能な金，白金，クロム，パラジウム，アルミニウム，イ
ンジウム，モリブデン，ニッケル、等の金属や、これら
金属を用いた合金や、ポリシリコン，アモルファスシリ
コン，錫酸化物，酸化インジウム，インジウム・錫酸化
物（ＩＴＯ）等の無機材料が望ましい。もちろんこれら
の材料に限られるわけではなく、また、これらの材料を
２種以上併用しても差し支えない。The gate electrode of the present invention is preferably made of an organic material such as polyaniline or polythiophene, or a conductive ink, using a coating method in which the electrode forming process is simple.
In addition, metals such as gold, platinum, chromium, palladium, aluminum, indium, molybdenum, nickel, and the like, which can form electrodes using existing photolithographic methods, alloys using these metals, polysilicon, amorphous silicon, Inorganic materials such as tin oxide, indium oxide, and indium tin oxide (ITO) are desirable. Of course, it is not limited to these materials, and two or more of these materials may be used in combination.
【００１３】本発明のゲート絶縁膜に用いる材料とし
て、ゲート電極と同じように塗布法が可能なポリクロロ
ピレン，ポリエチレンテレフタレート，ポリオキシメチ
レン，ポリビニルクロライド，ポリフッ化ビニリデン，
シアノエチルプルラン，ポリメチルメタクリレート，ポ
リサルフォン，ポリカーボネート，ポリイミド等の有機
材料が望ましい。また、既存パターンプロセスを用いる
ことができるＳｉＯ2 ，ＳｉＮx ，Ａｌ2Ｏ3等の無機材
料が望ましい。もちろんこれらの材料に限られるわけで
はなく、また、これらの材料を２種以上併用しても差し
支えない。As the material used for the gate insulating film of the present invention, polychloropyrene, polyethylene terephthalate, polyoxymethylene, polyvinyl chloride, polyvinylidene fluoride, which can be coated in the same manner as the gate electrode,
Organic materials such as cyanoethyl pullulan, polymethyl methacrylate, polysulfone, polycarbonate, and polyimide are desirable. In addition, inorganic materials such as SiO 2 , SiN x , and Al 2 O 3 that can use an existing pattern process are desirable. Of course, it is not limited to these materials, and two or more of these materials may be used in combination.
【００１４】本発明で用いるソース電極及びドレイン電
極の材料としては、ほとんどの有機半導体が、電荷を輸
送するキャリアがホールであるＰ型半導体であることか
ら、半導体層とオーミック接触をとるために、仕事関数
の大きい金属が望ましい。具体的には、金，白金が挙げ
られるが、これらの材料に限定されるわけではない。こ
こでいう仕事関数とは、固体中の電子を外部に取り出す
のに必要な電位差であり、真空準位とフェルミ準位のエ
ネルギー差を電荷量で割った値として定義される。ま
た、半導体層表面にドーパントを高密度にドープした場
合は、金属／半導体間をキャリアがトンネルすることが
可能となり、金属の材質によらなくなるため、ゲート電
極であげた金属材料或いは有機導電性材料も対象とな
る。As a material for the source electrode and the drain electrode used in the present invention, most organic semiconductors are P-type semiconductors in which carriers for transporting electric charges are holes. A metal having a large work function is desirable. Specific examples include gold and platinum, but are not limited to these materials. The work function here is a potential difference required to extract electrons in a solid to the outside, and is defined as a value obtained by dividing an energy difference between a vacuum level and a Fermi level by a charge amount. Further, when the semiconductor layer surface is doped with a dopant at a high density, carriers can tunnel between the metal and the semiconductor, and the carrier does not depend on the material of the metal. Is also targeted.
【００１５】本発明の有機ＴＦＴ製造方法では、無機絶
縁膜等にはプラズマＣＶＤ法，金属膜，錫酸化物，酸化
インジウム，ＩＴＯ等には、スパッタ法が用いられる。
また、パターン加工には、既存のフォトリソグラフ法と
ドライエッチング或いはウエットエッチング法が用いら
れる。これら作製法に関する詳細な説明は、松本正一編
「液晶ディスプレイ技術−アクティブマトリクス ＬＣ
Ｄ−」第２章 産業図書（１９９６年）に記載されてい
る。また、導電性有機材料，導電性インク，絶縁性有機
材料、を原料とする薄膜の作製方法は、スピンコート
法，キャスト法，引き上げ法，真空蒸着法が挙げられ
る。In the method of manufacturing an organic TFT according to the present invention, a plasma CVD method is used for an inorganic insulating film and the like, and a sputtering method is used for a metal film, tin oxide, indium oxide, ITO and the like.
For the pattern processing, an existing photolithographic method and dry etching or wet etching are used. For a detailed description of these fabrication methods, see Shoichi Matsumoto, "Liquid Crystal Display Technology-Active Matrix LC"
D- ", Chapter 2, Industrial Books (1996). In addition, as a method for forming a thin film using a conductive organic material, a conductive ink, and an insulating organic material as raw materials, a spin coating method, a casting method, a pulling method, and a vacuum deposition method can be given.
【００１６】本発明の半導体層の作製方法としては、基
板温度を室温にした、真空蒸着法，スピンコート法，キ
ャスト法，引き上げ法、が挙げられる。該作製法で作ら
れた半導体膜を蒸気圧が飽和状態に近い有機溶媒の入っ
た密閉容器で溶媒処理を行う。該溶媒としては、テトラ
ヒドラフラン，クロロベンゼンと水の混合溶液，キシレ
ン等が望ましい。The method for producing the semiconductor layer of the present invention includes a vacuum deposition method, a spin coating method, a casting method, and a pulling method in which the substrate temperature is set to room temperature. The semiconductor film formed by this manufacturing method is subjected to solvent treatment in a closed container containing an organic solvent whose vapor pressure is close to a saturated state. As the solvent, tetrahydrafuran, a mixed solution of chlorobenzene and water, xylene and the like are desirable.
【００１７】本発明の半導体材料としては、フタロシア
ニン配位化合物層が望ましい。具体的には、銅フタロシ
アニン，錫フタロシアニン，亜鉛フタロシアニン，鉛フ
タロシアニンが望ましい。また、化１で表される金属フ
タロシアニン化合物が望ましい。ＭＸiＰｃ では、中心
金属Ｍとフタロシアニン環Ｐｃで形成される平面からＸ
i がでているため、結晶中の分子配列が通常の平面フタ
ロシアニンＭＰｃと異なり、溶媒処理の影響が大きい。
具体的には、チタニルフタロシアニン，バナジウムフタ
ロシアニン，二塩化錫フタロシアニン等が挙げられる。
なお、ＭＸiＰcの溶媒処理について詳細な説明は、文献
（T.Saito,Y.Iwakabe,T.Kobayashi,S.Suzuki,and T.Iwa
yanagi,J.Phys.Chem.,Vol.９８，P.P.２７２６−２７２
８ （１９９４））に記載されている。The semiconductor material of the present invention is preferably a phthalocyanine coordination compound layer. Specifically, copper phthalocyanine, tin phthalocyanine, zinc phthalocyanine, and lead phthalocyanine are desirable. Further, a metal phthalocyanine compound represented by Chemical Formula 1 is desirable. In MX i Pc, X is determined from the plane formed by the central metal M and the phthalocyanine ring Pc.
Due to the occurrence of i , the molecular arrangement in the crystal is different from that of normal planar phthalocyanine MPc, and the influence of the solvent treatment is large.
Specific examples include titanyl phthalocyanine, vanadium phthalocyanine, tin dichloride phthalocyanine, and the like.
A detailed description of the solvent treatment of MX i Pc can be found in the literature (T. Saito, Y. Iwakabe, T. Kobayashi, S. Suzuki, and T. Iwa
yanagi, J. Phys. Chem., Vol. 98, PP2726-272.
8 (1994)).
【００１８】[0018]
【発明の実施の形態】（実施例１）本発明により有機Ｔ
ＦＴ素子を、図１により説明する。(Embodiment 1) Organic T according to the present invention
The FT element will be described with reference to FIG.
【００１９】図１に実施例１の有機ＴＦＴ素子構造断面
図を示す。１０１はガラス基板、１０２はゲート電極、
１０３はゲート絶縁層、１０４はソース電極、１０５は
ドレイン電極、１０６は有機半導体層、である。FIG. 1 is a cross-sectional view of the structure of the organic TFT device according to the first embodiment. 101 is a glass substrate, 102 is a gate electrode,
103 is a gate insulating layer, 104 is a source electrode, 105 is a drain electrode, and 106 is an organic semiconductor layer.
【００２０】図１に示した実施例１の有機ＴＦＴ素子
は、図２の工程に従って作成された。コーニング１７３
７ガラス基板１０１上に厚さ約１５０ｎｍのＣｒＭｏ膜
をスパッタリング法により形成する。ホト工程によりＣ
ｒＭｏをパターニングしてゲート電極１０２を形成す
る。その上にＣＶＤ法により、厚さ３００ｎｍの酸化シ
リコン(ＳｉＯ2）膜のゲート絶縁層１０３を形成する。The organic TFT device of Example 1 shown in FIG. 1 was manufactured according to the process shown in FIG. Corning 173
7. A CrMo film having a thickness of about 150 nm is formed on the glass substrate 101 by a sputtering method. C by photo process
The gate electrode 102 is formed by patterning rMo. A gate insulating layer 103 of a silicon oxide (SiO 2 ) film having a thickness of 300 nm is formed thereon by a CVD method.
【００２１】ＳｉＯ2 膜の形成に用いた原料ガスは以下
の通りである：ＳｉＨ4＋Ｎ2Ｏ。ホト工程により、Ｓｉ
Ｏ2 膜にゲート電極取り出し用の穴を形成する。その上
に蒸着法を用いて形成した厚さ１５０ｎｍのＡｕをホト
エッチングによりパターニングして、ソース電極１０
４，ドレイン電極１０５、を形成する。ＡｕとＳｉＯ2
膜の密着性を向上させるため、Ａｕ電極と同じ形状のＣ
ｒＭｏ層を形成し、その上にＡｕ電極を作製した。The source gases used to form the SiO 2 film are as follows: SiH 4 + N 2 O. By photo process, Si
A hole for taking out a gate electrode is formed in the O 2 film. A 150-nm-thick Au formed thereon by using an evaporation method is patterned by photoetching to form a source electrode 10.
4, a drain electrode 105 is formed. Au and SiO 2
In order to improve the adhesion of the film, a C
An rMo layer was formed, and an Au electrode was formed thereon.
【００２２】ソース電極，ドレイン電極の大きさは、
(１０００×５０μｍ2）である。この場合、チャネル幅
Ｗは１０００μｍとなる。ソース／ドレイン電極間のギ
ャップ、すなわち、チャネル長Ｌは５０μｍである。そ
の上に厚さ１００ｎｍのチタニルフタロシアニン（Ｔｉ
ＯＰｃ）有機半導体膜を真空蒸着法により形成する。The size of the source electrode and the drain electrode is
(1000 × 50 μm 2 ). In this case, the channel width W is 1000 μm. The gap between the source / drain electrodes, that is, the channel length L is 50 μm. On top of that, a 100 nm-thick titanyl phthalocyanine (Ti
OPc) An organic semiconductor film is formed by a vacuum evaporation method.
【００２３】ＴｉＯＰｃ膜の作製条件は以下の通りであ
る。The conditions for forming the TiOPc film are as follows.
【００２４】蒸着装置チャンバー内に真空度は、３〜５
×１０-6torrである。基板温度は室温である。昇華精製
したＴｉＯＰｃ粉末をＭｏ製抵抗加熱ボートにのせ、約
300℃に加熱して蒸着する。作製した有機ＴＦＴ素子を
テトラヒドロフラン５０ｍｌを入れた密閉容器の中に入
れ、約１３時間おく。密閉容器中の温度を数度上げるこ
とにより、溶媒処理の短縮が可能である。以上により、
有機ＴＦＴが完成する。The degree of vacuum in the chamber of the vapor deposition device is 3 to 5
× 10 -6 torr. The substrate temperature is room temperature. Place the sublimated and purified TiOPc powder on a Mo resistance heating boat,
Heat to 300 ° C to deposit. The prepared organic TFT element is placed in a closed container containing 50 ml of tetrahydrofuran and left for about 13 hours. By increasing the temperature in the closed vessel by several degrees, it is possible to shorten the solvent treatment. From the above,
The organic TFT is completed.
【００２５】本実施例では、図３に示したように、ＴＨ
Ｆ溶媒処理を行う前の吸収スペクトルは６５４ｎｍ，７
１９ｎｍと２つのピークを有するのに対して、ＴＨＦ溶
媒処理後の吸収スペクトルは、８４１ｎｍにピークと６
５０〜８００ｎｍの範囲に２つのピークが重ね合わされ
た形状となる。また、溶媒処理後の有機ＴＦＴ素子で
は、溶媒未処理の有機ＴＦＴ素子に比べて、オン電流が
２桁増加し、ＴＦＴ特性が向上した。In this embodiment, as shown in FIG.
The absorption spectrum before the F solvent treatment was 654 nm, 7
While having two peaks at 19 nm, the absorption spectrum after THF solvent treatment showed a peak at 841 nm and a peak at 641 nm.
It has a shape in which two peaks are overlapped in the range of 50 to 800 nm. Further, in the organic TFT element after the solvent treatment, the on-state current increased by two digits compared to the organic TFT element without solvent treatment, and the TFT characteristics were improved.
【００２６】この結果、本発明によれば、半導体層にチ
タニルフタロシアニン蒸着膜を用いた高性能有機ＴＦＴ
素子が得られることが判る。As a result, according to the present invention, a high performance organic TFT using a titanyl phthalocyanine deposited film for the semiconductor layer
It turns out that an element is obtained.
【００２７】（実施例２）次に、本発明による有機ＴＦ
Ｔ素子を、チタニルフタロシアニン膜を半導体層に用い
た実施形態について説明する。(Example 2) Next, an organic TF according to the present invention was used.
An embodiment using a T element as a semiconductor layer with a titanyl phthalocyanine film will be described.
【００２８】コーニング１７３７ガラス基板１０１上
に、印刷法を用いて可溶性ポリアニリンでゲート電極１
０２形成する。その上に、スピンコート法を用いて、ポ
リイミドでゲート絶縁層１０３を形成する。その上に、
ゲート電極と同じように、ポリアニリンでソース電極１
０４、およびドレイン電極１０５を形成する。さらに、
その上に塗布法により、半導体層であるチタニルフタロ
シアニン膜を形成する。作製した有機ＴＦＴ素子をテト
ラヒドロフラン５０ｍｌを入れた密閉容器の中に入れ、
約１３時間おく。以上により、有機ＴＦＴが完成する。On a Corning 1737 glass substrate 101, a gate electrode 1 was formed of soluble polyaniline using a printing method.
02 is formed. A gate insulating layer 103 is formed thereover using polyimide by spin coating. in addition,
As with the gate electrode, the source electrode 1 is made of polyaniline.
04 and the drain electrode 105 are formed. further,
A titanyl phthalocyanine film as a semiconductor layer is formed thereon by a coating method. Put the produced organic TFT device in a closed container containing 50 ml of tetrahydrofuran,
Leave for about 13 hours. Thus, the organic TFT is completed.
【００２９】本実施例では、ゲート電極，ゲート絶縁
層，ソース電極，ドレイン電極、及び半導体層が全て塗
布法を用いており、製造プロセスの大幅な簡略化が可能
となった。また、実施例１同様、溶媒処理後の有機ＴＦ
Ｔ素子では、オン電流が２桁増加し、ＴＦＴ特性が向上
した。In this embodiment, the gate electrode, the gate insulating layer, the source electrode, the drain electrode, and the semiconductor layer are all applied by the coating method, so that the manufacturing process can be greatly simplified. Also, as in Example 1, the organic TF after the solvent treatment
In the T element, the ON current increased by two digits, and the TFT characteristics were improved.
【００３０】この結果、本発明によれば、高性能塗布型
チタニルフタロシアニンＴＦＴ素子が得られることが判
る。As a result, according to the present invention, it is understood that a high performance coating type titanyl phthalocyanine TFT device can be obtained.
【００３１】[0031]
【発明の効果】本発明を用いれば、低温プロセスを用い
た高性能有機ＴＦＴ素子の作製が可能となる。According to the present invention, a high-performance organic TFT device can be manufactured using a low-temperature process.
【図１】本発明の一形態である有機ＴＦＴ素子の構造を
示す断面図である。FIG. 1 is a cross-sectional view illustrating a structure of an organic TFT element which is one embodiment of the present invention.
【図２】実施例１に示す有機ＴＦＴ素子の作製プロセス
を示すフローチャートである。FIG. 2 is a flowchart showing a manufacturing process of the organic TFT element shown in Example 1.
【図３】本発明の一形態である有機ＴＦＴ素子の半導体
層に用いるチタニルフタロシアニン蒸着膜のＴＨＦ溶媒
処理による吸収スペクトルの変化を示す特性図である。FIG. 3 is a characteristic diagram showing a change in absorption spectrum of a titanyl phthalocyanine vapor-deposited film used for a semiconductor layer of an organic TFT element which is one embodiment of the present invention due to a THF solvent treatment.
１０１…ガラス基板、１０２…ゲート電極、１０３…ゲ
ート絶縁膜、１０４…ソース電極、１０５…ドレイン電
極、１０６…有機半導体膜、３０１…ＴＨＦ溶媒処理前
のチタニルフタロシアニン蒸着膜の吸収スペクトル、３
０２…ＴＨＦ溶媒処理後のチタニルフタロシアニン蒸着
膜の吸収スペクトル。DESCRIPTION OF SYMBOLS 101 ... Glass substrate, 102 ... Gate electrode, 103 ... Gate insulating film, 104 ... Source electrode, 105 ... Drain electrode, 106 ... Organic semiconductor film, 301 ... Absorption spectrum of titanyl phthalocyanine vapor deposition film before THF solvent treatment, 3
02: absorption spectrum of the titanyl phthalocyanine vapor-deposited film after the THF solvent treatment.
フロントページの続き (72)発明者 安藤 正彦 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 斎藤 俊郎 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 Ｆターム(参考） 2H092 JA26 JA49 KA09 KA13 KA20 MA04 MA10 NA27 5F110 AA05 AA07 AA17 BB01 BB20 CC03 DD02 EE01 EE02 EE03 EE04 EE06 EE07 EE08 EE09 EE14 EE41 EE43 EE44 EE45 FF01 FF02 FF03 FF09 FF21 FF29 FF30 GG05 GG06 GG28 GG29 GG41 GG42 GG58 HK02 HK04 HK21 HK32 Continued on the front page (72) Inventor Masahiko Ando 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Toshiro Saito 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratories, Hitachi, Ltd. F-term (reference) 2H092 JA26 JA49 KA09 KA13 KA20 MA04 MA10 NA27 5F110 AA05 AA07 AA17 BB01 BB20 CC03 DD02 EE01 EE02 EE03 EE04 EE06 EE07 EE08 EE09 EE14 FF41 FF23 FF44 FF44 GG05 GG06 GG28 GG29 GG41 GG42 GG58 HK02 HK04 HK21 HK32
Claims (4)
電極，ドレイン電極、及びフタロシアニン配位化合物層
の半導体層からなる薄膜トランジスタの製造方法におい
て、前記半導体層の作製過程において、溶媒処理を用い
ることを特徴とする薄膜トランジスタの製造方法。1. A method for manufacturing a thin film transistor comprising a semiconductor layer of a substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, and a phthalocyanine coordination compound layer, wherein a solvent treatment is used in the process of manufacturing the semiconductor layer. A method for manufacturing a thin film transistor, comprising:
属フタロシアニン化合物を半導体層に用いることを特徴
とする薄膜トランジスタ。 【化１】ＭＸiＰｃ （Ｍ：中心金属、Ｘi：配位子ｉ＝１，２、Ｐｃ：フタ
ロシアニン環）2. The thin film transistor according to claim 1, wherein a metal phthalocyanine compound represented by the following formula 1 is used for a semiconductor layer. Embedded image MX i Pc (M: central metal, X i : ligand i = 1, 2, Pc: phthalocyanine ring)
ルフタロシアニンを用いることを特徴とする薄膜トラン
ジスタ。3. The thin film transistor according to claim 1, wherein titanyl phthalocyanine is used for the semiconductor layer.
のピークを有し、７１９ｎｍと841ｎｍの吸光度比が０.
６ 以下である吸収スペクトルを有する半導体層を用い
ることを特徴とする薄膜トランジスタ。4. The method according to claim 3, wherein the peak has a maximum peak at a wavelength of 841 nm, and the absorbance ratio between 719 nm and 841 nm is 0.1.
6. A thin film transistor using a semiconductor layer having an absorption spectrum of 6 or less.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10341347A JP2000174277A (en) | 1998-12-01 | 1998-12-01 | Thin film transistor and its manufacture |
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|---|---|
| JP2000174277A true JP2000174277A (en) | 2000-06-23 |
Family
ID=18345368
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|---|---|---|---|
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| Country | Link |
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