JP2000162645A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device reduced in the area of a TFT formation region. SOLUTION: This device is designed, such that a gate signal line 51 and the semiconductor layer of a TFT, which is formed in proximity to the intersection between a drain signal line 50 and the gate signal line 51, are arranged to cross at right angles to each other, with an inclination with respect to the longitudinal direction of an insulated substrate, at two places between the source and the drain, and that the device being equipped with a double gate electrode structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device having a thin film transistor.

[0002]

2. Description of the Related Art Hitherto, a liquid crystal display device having a thin film transistor has been proposed.

FIG. 5 is a plan view of a liquid crystal display device, and FIG.
FIG. 7 is a sectional view taken along the line CC in FIG. 5, and FIG.
An enlarged view of the vicinity of a TFT forming region is shown.

As shown in FIG. 5, a plurality of gate signal lines 51 and a plurality of gate signal lines 51 are provided on a TFT substrate 10 formed of an insulating substrate such as glass or quartz and formed with a thin film transistor (hereinafter referred to as “TFT”). The drain signal lines 50 cross each other, and the switching element T
FT is arranged. Further, a display electrode 19 made of a transparent conductive film such as ITO (Indium Thin Oxide) is connected to the source 13s of the TFT. Drain signal line 50
Intersects the gate signal line 51 and the display electrode 19
And are superimposed.

Further, a gate signal line 5 is provided near the TFT.
A storage capacitor electrode line 52 is arranged in parallel with the storage capacitor electrode line 1. This auxiliary capacitance electrode line 52 is an auxiliary capacitance made of chromium or the like and accumulating charge between the source 53 s of the TFT and the electrode 53 connected thereto via the interlayer insulating film 15. The auxiliary capacitor is provided in parallel with the liquid crystal 21 which is a capacitor for suppressing the charge stored in the liquid crystal 21 also being reduced due to the leak current of the TFT and holding the charge storage. ing.

The counter electrode 34 on the counter electrode substrate 30 side
In FIG. 5, an orientation control formed by removing ITO as a counter electrode material so that one end of a letter "Y" as shown by a dotted line in FIG. A window 36 is provided.

As shown in FIGS. 5 and 6, the insulating substrate 1
An interlayer insulating film 15, a drain signal line 50 disposed for each display pixel, and a planarizing insulating film 17 are sequentially formed on the display electrode 0, and a display electrode 19 made of ITO is formed thereon.
Is provided for each display pixel. This display electrode 19 is arranged so as to overlap with the drain signal line 50. Further, on the display electrode 19, a vertical alignment film 20 for aligning the liquid crystal 21 is provided. Further, a polarizing plate 41 is provided on the side of the insulating substrate 10 where the liquid crystal 21 is not arranged.

On the counter electrode substrate 30, a color filter 31 composed of red (R), green (G), and blue (B) of each color and a black matrix for shielding light is provided. On the color filter 31, a protective film 33 made of resin for protecting the surface is provided. Then, a counter electrode 34 made of a transparent conductive film such as ITO is formed thereon. As described above, the liquid crystal 2 is provided on the opposite electrode 34.
An orientation control window 36 for controlling the orientation of No. 1 is provided.
A vertical alignment film 35 for vertically aligning the liquid crystal 21 is disposed thereon. The liquid crystal 21 on the counter electrode substrate 30
The polarizing plate 42 is provided on the side where is not disposed. The polarizing axes of the polarizing plate 42 and the polarizing plate 41 are arranged orthogonal to each other.

Then, the insulating substrate 10 and the counter electrode substrate 2
0 and the periphery are bonded by a seal adhesive (not shown),
The formed void is filled with, for example, a nematic liquid crystal 21 having a negative dielectric anisotropy to complete a liquid crystal display panel.

[0010]

However, the conventional TF
The gate electrode 11 of T has a structure formed by projecting two vertically from the gate signal line 50. Therefore, for example, an LDD (Lightly Doped) in which a TFT is doped on both sides of the gate electrode 11 of the semiconductor layer 13 and further doped on both sides to form a source region and a drain region.
In the case of adopting a ped drain structure, as shown in FIG.
After covering the regions 61, 62, 63, 64 on both sides of the gate electrode 11 with the resist 60 in the doped region, the source 13 s and the source 13 s and Drain 1
3d will be formed.

If the resist 60 for forming the low-concentration regions 62 and 63 between the two gate electrodes is not formed with an interval between the low-concentration regions 62 and 63,
The low-concentration region cannot be separated into the region 62 and the region 63 between the gate electrodes 11, and the LDD structure cannot be formed. For this reason, in order to surely separate the two regions 62 and 63, a sufficiently large region in which the resist 60 can be surely separated is required.

Further, since the gate signal line 51 has a linear shape and the gate electrode 11 is formed vertically from the gate signal line 51, it is difficult to reduce the distance between the source 13s and the drain 13d. was there.

The present invention has been made in view of the above-mentioned conventional disadvantages, and has as its object to provide a liquid crystal display device in which the area of a TFT formation region is reduced.

[0014]

According to the liquid crystal display device of the present invention, a gate signal line and a drain signal line intersect on a substrate, and the gate signal line is connected to the gate signal line near an intersection of the two signal lines. And a thin film transistor having a semiconductor layer having a drain connected to the drain signal line and a source connected to the display electrode, wherein the gate signal line is disposed in a longitudinal direction of the substrate. Incline,
The semiconductor layer between the source and the drain is substantially perpendicular to each other a plurality of times.

Further, in the liquid crystal display device of the present invention, liquid crystal is sealed between the first and second substrates disposed opposite to each other on the substrate, and the first substrate includes a gate signal. A line and a drain signal line intersect, and a gate connected to the gate signal line, a drain connected to the drain signal line, and a source connected to the display electrode are provided near the intersection of the two signal lines. Comprising a thin film transistor having a semiconductor layer and a vertical alignment film for aligning the liquid crystal,
A counter electrode provided with an alignment control window at a position overlapping with the display electrode for controlling the alignment of the liquid crystal on the second substrate;
And the vertical alignment film, wherein the gate signal line is inclined with respect to a major axis direction of the substrate, and is substantially orthogonal to the semiconductor layer between the source and the drain a plurality of times. Things.

Further, the above-mentioned liquid crystal display device includes a thin film transistor having a double gate structure in which the gate signal line is orthogonal to the semiconductor layer between the source and the drain twice.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The liquid crystal display of the present invention will be described below.

FIG. 1 is a plan view of the liquid crystal display device of the present invention, FIG. 2 is a sectional view taken along the line AA in FIG. 1, FIG. 3 is an enlarged view of the vicinity of the TFT, and FIG. BB in FIG.
FIG. 4 shows a sectional view along the line.

As shown in FIG. 1, a thin film transistor (TFT), which is a switching element, is connected near an intersection between a gate signal line 51 also serving as the gate electrode 11 and a drain signal line 50 partially having the drain electrode 16. ITO
A display electrode 19 made of a transparent conductive material such as

At this time, the gate signal line 5 in FIG.
In a TFT forming region 1 including a source, a drain, and a gate, a part of the gate signal line 51 is bent and formed in a “mountain” shape below. Further, the semiconductor layer 13 is also generally formed in a “mountain” shape on the upper side. That is, the gate signal line 5
Numeral 1 is provided, for example, at an angle of about 45 ° with respect to the longitudinal direction of the insulating substrate forming the liquid crystal display device. The semiconductor layer connected to one of the drains forms an angle of approximately 45 ° in the upper right direction in the figure, extends almost horizontally, and further forms an angle of approximately 45 ° in the lower right direction to the source. The other gate signal line 51 extends in the lower right direction at an angle of approximately 45 ° near the drain electrode 16, and at this time, after being substantially orthogonal to the semiconductor layer 13, It extends substantially horizontally and further extends at an angle of approximately 45 ° in the upper right direction, at which time it is substantially orthogonal to the semiconductor layer 13 again. Note that neither the gate signal line 51 nor the semiconductor layer 13 may have a horizontally extending portion, and may have an "L" shape.

Thus, the gate signal line 51 and the semiconductor layer 1
3 cross each other so as to be substantially orthogonal to each other, and a channel 13c is formed at a position where the gate signal line 51 and the semiconductor layer 13 overlap.

The angle at which the gate signal line 51 intersects with the semiconductor layer 13 preferably intersects at right angles. This is because the distance between the drain and the source can be reduced, and the area of the overlapping portion between the gate signal line 51 and the semiconductor layer 13 can be maximized.

FIG. 3 is a partially enlarged view showing the vicinity of the TFT shown in FIG.

As shown in FIG. 1, a low concentration doping is performed on the entire semiconductor layer 13, and then a resist 60 for forming low concentration regions 61, 62, 63, 64 of the LDD region is formed on the semiconductor layer. Semiconductor layer 1 of gate signal line 51
Then, doping is performed so as to cover the intersection with the channel 3, that is, the channel 13 c and between the two channels 13 c.
By doing so, a low-concentration region and a high-concentration region are formed on both sides of the gate electrode 11, thereby forming an LDD structure.

At this time, the gate signal line 51 and the semiconductor layer 13
Are orthogonal to each other, so that the adjacent gate electrode 11
The space between the low-concentration regions 62 and 63 therebetween can be sufficiently ensured, and the resist 60 covering both regions 62 and 63 does not come into contact. Therefore, a low-concentration region can be reliably formed even in a small area, and a TFT having an LDD can be formed.

In this embodiment, the case where the LDD structure is formed has been described. However, according to the present invention, not only when the LDD structure is formed but also when the gate signal line 51 is formed.
And the semiconductor layer 13 are orthogonal to each other at an angle of about 45 ° with respect to each other, so that the distance between the source 13s and the drain 13d is smaller than that in the case where the gate signal line 51 is linear as in the related art. Can be reduced. Therefore, the area of the TFT formation region can be reduced.

In the case of the present embodiment, the gate signal line 51
Shows a case of a so-called double gate structure in which the semiconductor layer 13 and one TFT element are orthogonal to each other twice, but a so-called multi-gate structure having three or more crossings may be used. However, in that case, the width of the gate signal line 51 or the semiconductor layer 13 must be reduced in order to reduce the intersecting region, that is, the distance between the drain and the source.

In FIG. 1, the counter electrode substrate 30
Similar to the one shown in FIG. 5 described above, the opposite electrode 34 is made of an opposite electrode material such that one end of a letter “Y” indicated by a dotted line has a bifurcated shape similarly to the other end. An orientation control window 36 formed by removing ITO is provided.

The drain signal line 50 is connected to the counter electrode substrate 30
It is formed along the orientation control window 36 provided above. That is, in FIG.
Is bent to the lower right corresponding to the upper left branch of the letter "Y" in the orientation control window 36, and the orientation control window 3
6 extend vertically in the figure accordingly, and further extend vertically in the orientation control window 36.
It is bent and extends toward the lower left corresponding to the lower left branch of the character. Thus, the drain signal line 50 is arranged so as to overlap the left branch portion and the vertical portion of the orientation control window 36. Note that the shape of the drain signal line 50 is not limited to the above-described shape, and if the orientation control window 36 is, for example, a letter “X”, the shape is in accordance with the shape.

Here, the sectional structure of the liquid crystal display device along the line AA in FIG. 1 will be described.

As shown in FIG. 2, chromium (C) is formed on an insulating substrate 10 made of quartz glass, non-alkali glass or the like.
r), a gate signal line 51 also serving as the gate electrode 11 made of a high melting point metal such as molybdenum (Mo) is formed.

A gate insulating film 12 and an active layer 13 made of a polycrystalline silicon film are sequentially formed.

In the active layer 13, a channel 13c above the gate electrode 11 and both sides of the channel 13c are ion-doped using the stopper insulating film 14 on the channel 13c as a mask. Covered with ion doping, a low-concentration region on both sides of the gate electrode 11 and a high-concentration region
s and a drain 13d are provided. That is, it is a so-called LDD structure. Then, the entire surface of the gate insulating film 12, the active layer 13 and the stopper insulating film 14 is covered with SiO 2.
₂ film, an SiN film, and an SiO ₂ film are laminated in this order, and a contact hole provided corresponding to the drain 13 d is filled with a metal such as Al to form a drain electrode 1.
6 is formed. Further, a flattening insulating film 17 made of, for example, an organic resin and flattening the surface is formed on the entire surface. Then, a contact hole is formed at a position corresponding to the source 13 s of the planarization insulating film 17, and a display electrode 19, which is a transparent electrode made of ITO in contact with the drain 13 d via this contact hole and also serves as the drain electrode 18, is formed. It is formed on the planarization insulating film 17. And the display electrode 19
A vertical alignment film 20 made of an organic resin such as polyimide and vertically aligning the liquid crystal 21 is formed thereon. This vertical alignment film 2
No rubbing to zero is required. A polarizing plate 41 is provided on the side of the insulating substrate 10 where no liquid crystal is arranged, that is, on the outside.

On the other side of the counter electrode substrate 30 on which the liquid crystal 21 is disposed, a color filter 3 having a black matrix 32 having R, G, and B colors and a light shielding function is provided.
1. A protective film 33 made of an acrylic resin or the like for protecting the color filter 31 is provided. On the protective film 33, a counter electrode 34 facing each display electrode 19 is provided with an alignment control window 36 in a part thereof. A vertical alignment film 35 made of polyimide is formed on the entire surface.

Further, a polarizing plate 42 is sequentially provided on the side of the counter electrode substrate 30 where no liquid crystal is arranged, that is, on the viewer 101 side.

Further, as the liquid crystal 21, a nematic liquid crystal having a negative dielectric anisotropy is used.

When no voltage is applied to the liquid crystal 21, the liquid crystal molecules between the substrates 10, 30 are applied between the substrates 10, 30.
Are oriented perpendicular to. Therefore, the TFT substrate 1
The incident light linearly polarized by the zero-side polarizing plate 41 is not subjected to birefringence in the liquid crystal 21 and is blocked by the polarizing plate 42 on the counter electrode substrate 30 side, resulting in black display. This is a so-called normally black method.

When a voltage is applied to the liquid crystal 21, the incident light linearly polarized by the polarizing plate 41 undergoes birefringence by the liquid crystal 21 having a negative dielectric anisotropy to become elliptically polarized light, and passes through the polarizing plate 42. And a white display is obtained.

That is, a liquid crystal is used in which liquid crystal molecules are oriented perpendicular to the substrate when no voltage is applied and are oriented substantially parallel when a voltage is applied.

The insulating substrate 10 provided with the TFT thus manufactured and the counter substrate 30 provided with the counter electrode 34 and the alignment film 35 facing the substrate 10 are bonded around the periphery thereof with a sealing adhesive (not shown). Then, the liquid crystal 2 is filled in the formed gap.
1 to complete the liquid crystal display panel.

As shown in FIG. 4, the drain signal line 50 provided on the interlayer insulating film 15 is formed so as to overlap the orientation control window 36. That is, it has a wiring shape bent toward the center of the display electrode 19.

At this time, it is preferable that either one of the line width of the drain signal line 50 and the width of the orientation control window 36 is made large. That is, even if a displacement occurs when the TFT substrate 10 and the counter electrode substrate 30 are bonded to each other,
If any of the widths is larger than the displacement width due to the displacement, the area of the region shielded by the displacement will not be larger than the width of the drain signal line 50 or the orientation control window 36. For example, the width of the orientation control window 36 is set to 4 μm.
m, the width of the drain signal line 50 is set to 6 to 8 μm.
By doing so, it is possible to prevent a decrease in the aperture ratio due to displacement.

As described above, the area of the TFT formation region is reduced by providing the gate signal line 51 at an angle to the semiconductor layer between the source and the drain and at right angles to the major axis direction of the substrate. Therefore, the ratio of the displayable area to the display electrode, that is, the aperture ratio can be improved.

[0044]

According to the present invention, it is possible to obtain a liquid crystal display device in which the area of the TFT forming region is reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a liquid crystal display device of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display device taken along line AA in FIG. 1 of the present invention.

FIG. 3 is an enlarged view of the vicinity of a TFT forming region in FIG.

FIG. 4 is a cross-sectional view of the liquid crystal display device taken along the line BB in FIG. 1 of the present invention.

FIG. 5 is a plan view of a conventional liquid crystal display device.

FIG. 6 is a cross-sectional view of the liquid crystal display device taken along line CC in FIG.

FIG. 7 is an enlarged view of the vicinity of a TFT forming region in FIG.

[Explanation of symbols]

 Reference Signs List 10 TFT substrate 13 Polycrystalline silicon film 15 Interlayer insulating film 17 Flattening insulating film 19 Display electrode 21 Liquid crystal 30 Counter electrode substrate 50 Drain signal line 51 Gate signal line 52 Auxiliary capacitance signal line

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Katsuya Kihara 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 2H092 JA26 JA28 JA36 JA40 JA44 JB23 JB25 JB32 JB58 KA04 KA18 KB04 KB25 MA27 MA41 NA07 PA08 QA07 5F110 AA04 BB01 CC08 DD02 DD03 EE04 EE24 EE28 EE37 GG02 GG13 GG23 HJ13 HL03 HL07 HM15 NN03 NN12 NN23 NN24 NN27 NN72 NN77 QQ19

Claims (3)

[Claims] A gate signal line and a drain signal line intersect on a substrate, and a gate connected to the gate signal line and a gate connected to the drain signal line are provided near an intersection of the two signal lines. A thin film transistor having a drain and a semiconductor layer having a source connected to the display electrode, wherein the gate signal line is inclined with respect to a major axis direction of the substrate, and the gate signal line is disposed between the source and the drain. A plurality of times substantially perpendicular to the semiconductor layer. 2. A liquid crystal is sealed between a first substrate and a second substrate which are arranged on a substrate so as to face each other, and a gate signal line and a drain signal line intersect on the first substrate. A thin film transistor having a gate connected to the gate signal line, and a semiconductor layer having a drain connected to the drain signal line and a source connected to the display electrode, near the intersection of the two signal lines. And a vertical alignment film for aligning the liquid crystal, wherein the second substrate is provided with an alignment control window at a position overlapping with the display electrode for controlling the alignment of the liquid crystal, and the vertical alignment film. Wherein the gate signal line is inclined with respect to a major axis direction of the substrate, and is substantially orthogonal to the semiconductor layer between the source and the drain a plurality of times. Liquid crystal display. 3. The liquid crystal according to claim 1, wherein the thin film transistor has a double gate structure in which the gate signal line is orthogonal to the semiconductor layer between the source and the drain twice. Display device.