KR101200878B1 - Thin film transistor substrate and fabricating method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor substrate including a shielding electrode capable of suppressing poor image quality and a method of manufacturing the same.

A thin film transistor substrate according to an embodiment of the present invention includes a gate line formed on the substrate; A data line intersecting the gate line to form a pixel area; A polysilicon thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the polysilicon thin film transistor and formed of a transparent conductive film; A common electrode formed of the same metal on the same plane as the pixel electrode and forming a horizontal electric field with the pixel electrode; And a shielding electrode formed between at least one signal line of the gate line and the data line and the pixel electrode and overlapping the common electrode.

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR SUBSTRATE AND FABRICATING METHOD THEREOF}

1 is a cross-sectional view showing a conventional horizontal field type liquid crystal display panel.

2 is a plan view illustrating a horizontal field type thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a thin film transistor substrate taken along lines "I-I '" and "II-II'" in FIG.

4A and 4B are cross-sectional views showing another form of the shielding electrode shown in FIG. 3.

5A and 5B show a liquid crystal arrangement of a thin film transistor substrate according to the prior art and the present invention.

6A to 6F are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 3.

7 is a plan view illustrating a horizontal field type thin film transistor substrate according to a second exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating the thin film transistor substrate taken along the line “III-III ′” in FIG. 7.

Description of the Related Art

102: gate line 104: data line

106: gate electrode 108: source electrode

110: drain electrode 111: buffer film

112 gate insulating film 114 active layer

118: protective film 119: interlayer insulating film

122: pixel electrode 124: common electrode

126: common line 130: shielding electrode

154, 158: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate using a horizontal electric field, and more particularly, to a thin film transistor substrate capable of suppressing image quality defects due to vertical crosstalk and a method of manufacturing the same.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. In the liquid crystal display, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. Such a vertical electric field type liquid crystal display device has a disadvantage that the aperture ratio is large, but the viewing angle is as narrow as 90 degrees.

Accordingly, in recent years, a horizontal field type liquid crystal display having a wide viewing angle of about 160 degrees is driven by driving a liquid crystal in In Plane Switching (IPS) mode by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. The device has been proposed.

As illustrated in FIG. 1, the horizontal field type liquid crystal display includes a thin film transistor substrate 40 and a color filter substrate 30 which are bonded to each other with the liquid crystal 26 interposed therebetween.

The color filter substrate 30 includes a color filter array including a black matrix 12 for preventing light leakage, a color filter 14 for color implementation, and an upper alignment layer coated thereon for liquid crystal alignment on the upper substrate 11. ) Is formed on.

The thin film transistor substrate 40 has a gate line and a data line 4 formed to cross each other, a thin film transistor formed at an intersection thereof, a pixel electrode 22 connected to the thin film transistor, and a horizontal line with the pixel electrode 22. A thin film transistor array including a common electrode 24 constituting an electric field and a lower alignment layer coated thereon for liquid crystal alignment is formed on the lower substrate 1.

In order to increase the aperture ratio of the pixel electrode 22 and the common electrode 24 of the conventional horizontal field type liquid crystal display panel, a transparent conductive film is formed on the same plane. In this case, in the conventional horizontal field type liquid crystal display panel, a parasitic capacitor is formed between the pixel electrode 22 and the common electrode 24, and a parasitic capacitor is formed between the drain electrode 10 and the data line 4 of the thin film transistor. . In particular, when the black matrix 12 is formed of a black conductive metal, parasitic capacitors may be formed between the pixel electrode 22 (common electrode 24, drain electrode 10, data line 4) and the black matrix 12. Is formed. Due to such parasitic capacitors, the pixel voltage signal supplied to the pixel electrode 22, the data line 4, and the drain electrode 10 and the common voltage signal supplied to the common electrode 24 become unstable. This causes a problem in that the liquid crystal array is uniform and vertical crosstalk occurs.

Accordingly, an object of the present invention is to provide a thin film transistor substrate and a method for manufacturing the same, which can suppress a liquid crystal twist phenomenon by reducing the capacitance of a parasitic capacitor formed between electrodes.

In order to achieve the above object, a thin film transistor substrate according to an embodiment of the present invention includes a gate line formed on the substrate; A data line intersecting the gate line to form a pixel area; A polysilicon thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the polysilicon thin film transistor and formed of a transparent conductive film; A common electrode formed of the same metal on the same plane as the pixel electrode and forming a horizontal electric field with the pixel electrode; And a shielding electrode formed between at least one signal line of the gate line and the data line and the pixel electrode and overlapping the common electrode.

The polysilicon thin film transistor may include: a gate electrode connected to the gate line and formed on a gate insulating film; A source electrode connected to the data line on an interlayer insulating film formed to cover the gate electrode; A drain electrode connected to the pixel electrode on the interlayer insulating film; And a polysilicon active layer having a channel region overlapping the gate electrode, a source region connected to the source electrode, and a drain region connected to the drain electrode.

The shielding electrode is formed on the gate insulating layer between the data line and the pixel electrode and is formed on the same plane as the gate electrode.

The shielding electrode may be formed of the same material as the active layer on a substrate on which the active layer between the data line and the pixel electrode is formed.

The shielding electrode may include a first shielding electrode formed on the same plane as the active layer on the substrate on which the active layer between the data line and the pixel electrode is formed; And a second shielding electrode formed of the same material as the gate electrode on the gate insulating layer between the data line and the pixel electrode.

The shielding electrode overlaps the data line with a width less than or equal to the common electrode overlapping the data line.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a polysilicon active layer on the substrate; Forming a gate insulating film to cover the polysilicon active layer; Forming a first conductive pattern group including a gate electrode, a gate line, and a shielding electrode on the gate insulating film; Forming an interlayer insulating film to cover the first conductive pattern group; Forming a second conductive pattern group on the interlayer insulating layer, the second conductive pattern group including a data line, a source electrode, and a drain electrode to form a pixel region crossing the gate line; Forming a protective film to cover the second conductive pattern group; And forming a pixel electrode in the pixel area on the passivation layer, and forming a common electrode in the pixel area to form a horizontal electric field with the pixel electrode and overlap the data line adjacent to the shielding electrode. It is done.

The method of manufacturing the thin film transistor substrate may further include forming an auxiliary shielding electrode on the same plane as the active layer when the polysilicon active layer is formed on the substrate.

The forming of the shielding electrode may include forming the shielding electrode to overlap the data line with a width less than or equal to the common electrode overlapping the data line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 8.

2 is a plan view illustrating a horizontal field type thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view illustrating a thin film transistor substrate taken along lines "I-I '" and "II-II'" in FIG. 2. to be.

2 and 3, a horizontal field type thin film transistor according to an exemplary embodiment of the present invention may include a gate line 102 and a data line 104 formed to cross on a lower substrate 101, and a thin film formed at each intersection thereof. A pixel electrode 122 and a common electrode 124 formed to form a horizontal electric field in a pixel region provided with a crossover structure thereof, and a shielding electrode 130 positioned between the data line 104 and the pixel electrode 122. Equipped.

The thin film transistor allows the pixel voltage signal on the data line 104 to be charged and held in the pixel electrode 122 in response to the scan signal of the gate line 102. The thin film transistor includes a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, a drain electrode 110 connected to the pixel electrode 122, and a gate electrode 106. And an active layer 114 for forming a channel between the source electrode 108 and the drain electrode 110.

The gate electrode 106 connected to the gate line 102 is formed to overlap the channel region 114C of the active layer 114 and the gate insulating layer 112 therebetween. The source electrode 108 and the drain electrode 110 are formed to be insulated from each other with the gate electrode 106 and the interlayer insulating layer 119 therebetween. The source electrode 108 and the drain electrode 110 are active in which n + impurities are injected through the source contact hole 124S and the drain contact hole 124D that pass through the interlayer insulating layer 119 and the gate insulating layer 112, respectively. It is connected to each of the source region 114S and the drain region 114D of the layer 114. In addition, the active layer 114 is formed to include the channel region 114C and the source and drain regions 114S and 114D on the lower substrate 101. The active layer 114 may include a lightly doped drain (LDD) region (not shown) in which n- impurity is injected between the channel region 114C and the source and drain regions 114S and 114D to reduce the off current. It may be further provided.

The pixel electrode 122 is connected to the drain electrode 110 of the thin film transistor 130 through the contact hole 120 penetrating the passivation layer 118 and is formed in the pixel area. In particular, the pixel electrode 122 is formed between the first and second pixel portions 122a and 122b and the first and second pixel portions 122a and 122b formed in parallel with the common electrode 124. And a third pixel portion 122c connected to the 110. The pixel electrode 122 is formed of a transparent metal such as ITO to improve the aperture ratio.

The common electrode 124 is connected to the common line 126 to be formed in the pixel area. In particular, the common electrode 124 is formed to be parallel to them between the first and second pixel portions 122a and 122b of the pixel electrode. In addition, the common electrode 124 is formed to overlap the data line 104 in a wider width than the data line 104. As described above, the common electrode 124 formed in a wider width than the data line 104 reduces the influence of the liquid crystal on the pixel voltage signal of the data line 104 and the influence of the gate signal on the gate line 102. Will decrease. The common electrode 124 is formed of a transparent metal such as ITO to improve the aperture ratio.

In the thin film transistor substrate, a horizontal electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor and the common electrode 124 supplied with the reference voltage through the common line 126. The horizontal electric field causes liquid crystal molecules arranged in a horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region is changed, thereby realizing an image.

The shielding electrode 130 is formed to overlap the common electrode 124 between each of the first and second pixel portions 122a and 122b of the pixel electrode 122 and the data line 104, and the common line 126. It is formed to overlap. The shielding electrode 130 is formed of the same material as the gate line 102 and the gate electrode 106 on the gate insulating film 112. Alternatively, as shown in FIG. 4A, the buffer layer 111 may be formed of the same material as the active layer 114. That is, the shielding electrode 130 is formed of polysilicon implanted with n + impurities or n − impurities. Alternatively, as shown in FIG. 4B, the first shielding electrode 130a is formed of the same material as the active layer 114 on the buffer layer 111, and the same material as the gate electrode 106 is formed on the gate insulating layer 112. It is formed of a second shielding electrode 130b. Here, the first shielding electrode 130a is formed of polysilicon into which impurities are not injected.

The shielding electrode 130 is supplied with a bias voltage including a common voltage Vcom or a ground voltage GND which is a reference for driving the liquid crystal. The shielding electrode 130 supplied with the bias voltage shields the pixel voltage signal of the data line 104 and the gate signal of the gate line 102 together with the common electrode 124 overlapping the data line 104. The coupling phenomenon between the 104 and the pixel electrode 122 is suppressed. Since the shielding electrode 130 is formed to be adjacent to the data line 104 with the interlayer insulating layer 119 therebetween, a shielding effect capable of shielding the pixel voltage signal of the data line 104 is increased. The shielding electrode 130 may reduce the width of the common electrode 124 overlapping the data line 104. For example, the width of the common electrode 124 extending from the end of the data line 104 toward the pixel electrode 122 is about 10 μm or more, whereas in the present invention, it is about 3 to 5 μm, preferably 4 μm. to be. By reducing the common electrode 124, the aperture ratio is improved compared to the conventional. In addition, since the shielding electrode 130 may be used as an alignment mark when the thin film transistor substrate and the color filter substrate are bonded together, the bonding margin is improved.

It can be seen that the liquid crystal according to the present invention shown in FIG. 5A positioned between the data line and the pixel electrode by the shielding electrode suppresses the twist motion of the liquid crystal compared to the conventional liquid crystal shown in FIG. 5B.

6A to 6F are cross-sectional views illustrating a method of manufacturing a horizontal field type thin film transistor substrate according to a first embodiment of the present invention. Here, the structure shown in FIG. 3 will be described as an example.

Referring to FIG. 6A, a buffer layer 111 is formed on the lower substrate 101, and an active layer 114 layer is formed on the buffer layer 111.

The buffer layer 111 is formed by depositing an inorganic insulating material such as SiO ₂ on the lower substrate 101.

The active layer 114 deposits amorphous silicon on the buffer film 111 and crystallizes the amorphous silicon with a laser to become poly-silicon, and then pattern the poly-silicon by a photolithography process and an etching process. It is formed by.

Referring to FIG. 6B, a gate insulating layer 112 is formed on the buffer layer 111 on which the active layer 114 is formed, and includes a gate electrode 106, a gate line 102, and a shielding electrode 130 thereon. A first conductive pattern group is formed.

The gate insulating layer 112 is formed by depositing an inorganic insulating material such as SiO ₂ on the buffer layer 111 on which the active layer 114 is formed.

In the first conductive pattern group including the gate electrode 106, the gate line 102, and the shielding electrode 130, a gate metal layer is formed on the gate insulating layer 112, and the gate metal layer is subjected to a photolithography process and an etching process. It is formed by patterning.

The n + impurity is implanted into the active layer 114 using the gate electrode 106 as a mask, so that the source region 114S and the drain region 114D of the active layer 114 which are not overlapped with the gate electrode 106 are formed. Is formed. The source and drain regions 114S and 114D of the active layer 114 face each other with the channel region 114C overlapping the gate electrode 106 interposed therebetween.

Referring to FIG. 6C, an interlayer insulating layer 119 is formed on the gate insulating layer 112 on which the first conductive pattern group is formed, and source and drain contact holes 154S penetrating through the interlayer insulating layer 119 and the gate insulating layer 112. , 154D) is formed.

The interlayer insulating layer 119 is formed by depositing an inorganic insulating material such as SiO ₂ on the gate insulating layer 112 on which the first conductive pattern group is formed.

Subsequently, source and drain contact holes 154S and 154D penetrating the interlayer insulating layer 119 and the gate insulating layer 112 are formed by a photolithography process and an etching process. The source and drain contact holes 154S and 154D pass through the interlayer insulating layer 119 and the gate insulating layer 112 to expose the source and drain regions 114S and 114D of the active layer 114, respectively.

Referring to FIG. 6D, a second conductive pattern group including a data line 104, a source electrode 108, and a drain electrode 110 is formed on the interlayer insulating layer 119.

The second conductive pattern group including the data line 104, the source electrode 108, and the drain electrode 110 may form a source / drain metal layer on the interlayer insulating layer 119, and then photolithography the source / drain metal layer. It is formed by patterning in a process and an etching process.

The source electrode 108 and the drain electrode 110 are connected to each of the source region 114S and the drain region 114D of the active layer 114 through the source and drain contact holes 154S and 154D, respectively.

Referring to FIG. 6E, a passivation layer 118 is formed on the interlayer insulating layer 119 on which the second conductive pattern group is formed, and a pixel contact hole 158 penetrating the passivation layer 118 is formed.

In the passivation layer 118, an organic insulating material or an inorganic insulating material such as photoacrylic or the like is entirely deposited on the interlayer insulating film 119 on which the second conductive pattern group is formed.

Subsequently, the pixel contact hole 158 penetrating the passivation layer 118 is formed by a photolithography process and an etching process. The pixel contact hole 158 penetrates the passivation layer 118 to expose the drain electrode 110.

Referring to FIG. 6F, a third conductive pattern group including the pixel electrode 122, the common line 126, and the common electrode 124 is formed on the passivation layer 118.

The third conductive pattern group including the pixel electrode 122, the common line 126, and the common electrode 124 is formed by depositing a transparent conductive film such as ITO on the protective film 118, and then subjecting the transparent conductive film to a photolithography process and It is formed by patterning in an etching process.

FIG. 7 is a plan view illustrating a horizontal field type thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view illustrating a thin film transistor substrate taken along the line “III-III ′” in FIG. 7.

7 and 8, the horizontal field type thin film transistor substrate according to the second exemplary embodiment of the present invention is formed so that the shielding electrode overlaps the data line in comparison with the thin film transistor substrate shown in FIGS. 2 and 3. Has the same components. Accordingly, detailed description of the same constituent elements will be omitted.

7 and 8, the shielding electrode 130 is formed to overlap the data line 104 and overlaps the data line 104 and the pixel electrode 122 together with the common electrode 124 overlapping the data line 104. Suppresses the coupling phenomenon of the liver. Since the shielding electrode 130 is formed to overlap the data line 104 with the interlayer insulating layer 119 therebetween, the shielding electrode 130 may shield the pixel voltage signal of the data line 104 from the related art. The shielding electrode 130 may reduce the width of the common electrode 124 overlapping the data line 104. By reducing the common electrode 124, the aperture ratio is improved compared to the conventional. In addition, since the shielding electrode 122 may be used as an alignment mark when the thin film transistor substrate and the color filter substrate are bonded together, the bonding margin is improved.

The horizontal field type thin film transistor substrate according to the second exemplary embodiment having the structure as described above includes a shielding electrode 130 having a width greater than or equal to the data line 104 in the lower region of the data line 104. Such a shielding electrode can suppress the twist motion of the liquid crystal.

On the other hand, the horizontal field type thin film transistor substrate according to the present invention has been described with the example that the shielding electrode is formed between the data line and the pixel electrode, in addition to the shielding electrode can be formed between the gate line and the pixel electrode.

As described above, the thin film transistor substrate and the method of manufacturing the same according to the present invention include a shielding electrode formed between the data line and the pixel electrode or overlapping the data line. By suppressing the parasitic capacitor formed between the data line and the common electrode, the pixel electrode and the drain electrode, and the black matrix formed on the upper color filter array substrate in the pixel region where the liquid crystal is oriented by the shielding electrode, the twist motion of the liquid crystal can be prevented. Will be. As a result, the thin film transistor substrate and the manufacturing method thereof according to the present invention can prevent the twist motion of the liquid crystal, thereby suppressing vertical crosstalk and improving image quality defects.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A gate line formed on the substrate; A data line intersecting the gate line to form a pixel area; A polysilicon thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the polysilicon thin film transistor and formed of a transparent conductive film; A common electrode formed of the same metal on the same plane as the pixel electrode and forming a horizontal electric field with the pixel electrode; And a shielding electrode formed between the signal line of at least one of the gate line and the data line and the pixel electrode, and a portion of the common electrode overlapping the data line and corresponding to the common line connected to the common electrode. A thin film transistor substrate. The method of claim 1, The polysilicon thin film transistor, A gate electrode connected to the gate line and formed on a gate insulating film; A source electrode connected to the data line on an interlayer insulating film formed to cover the gate electrode; A drain electrode connected to the pixel electrode on the interlayer insulating film; And a polysilicon active layer having a channel region overlapping the gate electrode, a source region connected to the source electrode, and a drain region connected to the drain electrode. The method of claim 2, The shielding electrode, And a thin film transistor substrate formed on the gate insulating layer between the data line and the pixel electrode and formed on the same plane as the gate electrode. The method of claim 2, The shielding electrode The thin film transistor substrate of claim 1, wherein the active layer between the data line and the pixel electrode is formed of the same material as the active layer. The method of claim 2, The shielding electrode A first shielding electrode formed on the same plane as the active layer on the substrate on which the active layer between the data line and the pixel electrode is formed; And a second shielding electrode formed of the same material as the gate electrode on the gate insulating layer between the data line and the pixel electrode. The method of claim 1, The shielding electrode And the data line overlapping the data line with a narrower width than the common electrode overlapping the data line. Forming a polysilicon type active layer on the substrate; Forming a gate insulating film to cover the polysilicon active layer; Forming a first conductive pattern group including a gate electrode, a gate line, and a shielding electrode on the gate insulating film; Forming an interlayer insulating film to cover the first conductive pattern group; Forming a second conductive pattern group on the interlayer insulating layer, the second conductive pattern group including a data line, a source electrode, and a drain electrode to form a pixel region crossing the gate line; Forming a protective film to cover the second conductive pattern group; Forming a pixel electrode in the pixel region on the passivation layer, and forming a common electrode in the pixel region, the common electrode partially overlapping the data line and forming a horizontal electric field with the pixel electrode; And the shielding electrode is formed between the data line and the pixel electrode to correspond to a part of a common electrode overlapping the data line and a common line connected to the common electrode. The method of claim 7, wherein And forming an auxiliary shielding electrode on the same plane with the same material as the active layer when the polysilicon type active layer is formed on the substrate. The method of claim 7, wherein Forming the shielding electrode, And forming the shielding electrode to overlap the data line with a width narrower than that of the common electrode overlapping the data line. The method of claim 1, The shielding electrode may have a shape in which an English U is inverted or a Korean U in response to a portion of a common electrode overlapping the data line and a common line connected to the common electrode. . The method of claim 7, wherein The shielding electrode may have a shape in which an English U is inverted or a Korean U in response to a portion of a common electrode overlapping the data line and a common line connected to the common electrode. Manufacturing method.

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