JP2000156450A - Lead for electronic part - Google Patents
Lead for electronic partInfo
- Publication number
- JP2000156450A JP2000156450A JP10329714A JP32971498A JP2000156450A JP 2000156450 A JP2000156450 A JP 2000156450A JP 10329714 A JP10329714 A JP 10329714A JP 32971498 A JP32971498 A JP 32971498A JP 2000156450 A JP2000156450 A JP 2000156450A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- plating layer
- alloy
- plating
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
- H01L2224/438—Post-treatment of the connector
- H01L2224/43848—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/4557—Plural coating layers
- H01L2224/45572—Two-layer stack coating
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品用リード
に関し、特に、電子機器配線用導体としてのリード、あ
るいは半導体装置のアウターリードなどとして好適な電
子部品用リードに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead for an electronic component, and more particularly to a lead for an electronic component suitable as a lead for a wiring of an electronic device or an outer lead of a semiconductor device.
【０００２】[0002]
【従来の技術】ダイオード、抵抗器、コンデンサ、ある
いはトランジスタ等の電子部品に使用されるリードとし
て、たとえば、銅あるいは銅合金のワイヤー上にＳｎ‐
Ｐｂ合金、つまり、はんだめっきを施したものが知られ
ている。2. Description of the Related Art Leads used in electronic components such as diodes, resistors, capacitors, transistors, etc. are, for example, Sn-wires on copper or copper alloy wires.
Pb alloys, that is, those subjected to solder plating are known.
【０００３】また、ＩＣパッケージ等の半導体装置にお
いては、接続対象のプリント基板との接続性を良好にす
るために、電解法、あるいは溶解法によりアウターリー
ドの表面にはんだめっき層を形成することが行われてい
る。In a semiconductor device such as an IC package, a solder plating layer may be formed on the surface of an outer lead by an electrolytic method or a dissolving method in order to improve the connectivity with a printed circuit board to be connected. Is being done.
【０００４】このような構成のリードは、熱酸化に対す
る優れた耐性と良好なはんだ濡れ性を備えていることに
よって特徴づけられ、電子機器の配線、あるいは電子品
のプリント基板への実装等の用途において多用されてお
り、この種リードによる接合プロセスは、高密度な接合
技術を必要とする電子部品の分野においては完全に定着
している。A lead having such a structure is characterized by having excellent resistance to thermal oxidation and good solder wettability, and is used for wiring of electronic equipment or mounting of electronic goods on a printed circuit board. This type of lead bonding process has been fully established in the field of electronic components requiring high-density bonding technology.
【０００５】しかし、このようなはんだめっき層を形成
したリードによると、めっき層の中のＰｂ成分が、酸性
雨などによって溶出される性質のものであることから、
地下水汚染、延いては人体への影響が懸念されており、
このため、環境保護上の観点から、その使用に制約が加
えられる傾向にある。However, according to the lead having such a solder plating layer formed thereon, the Pb component in the plating layer has a property of being eluted by acid rain or the like.
There is concern about groundwater pollution and, in turn, its effects on the human body.
Therefore, from the viewpoint of environmental protection, there is a tendency that the use thereof is restricted.
【０００６】このため、Ｐｂを含有しないＰｂフリーの
はんだ合金の開発が各方面で進められており、その代表
的な例として、Ｓｎめっき層を形成したリードを挙げる
ことができる。このリードは、シンプルな材料系であ
り、Ｐｂフリー合金との濡れ性もよく、強度的にも適し
ている。For this reason, the development of Pb-free solder alloys containing no Pb has been promoted in various fields. A typical example thereof is a lead having an Sn plating layer formed thereon. This lead is a simple material, has good wettability with a Pb-free alloy, and is suitable for strength.
【０００７】[0007]
【発明が解決しようとする課題】しかし、Ｓｎめっき層
を形成したリードによると、ウイスカーが発生しやす
く、また、変色する傾向があり、Ｓｎ‐Ｐｂ合金の代替
めっきとしては特性的に充分とは言えない。However, according to the lead on which the Sn plating layer is formed, whiskers are liable to occur and discoloration tends to occur, so that the characteristics are not sufficient as an alternative plating for the Sn-Pb alloy. I can not say.
【０００８】従って、本発明の目的は、これまで多用さ
れてきたＳｎ‐Ｐｂ合金めっきのリードと同等の性能を
有しながら地下水を汚染せず、また、ウイスカーの発生
および変色を抑えた電子部品用リードを提供することに
ある。Accordingly, an object of the present invention is to provide an electronic component which has the same performance as Sn-Pb alloy plating leads which have been frequently used, does not contaminate groundwater, and suppresses generation and discoloration of whiskers. To provide a lead for use.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記の目的を
達成するため、リード母材と、前記リード母材の上に形
成された内部めっき層と、前記内部めっき層の上に形成
された外部めっき層から構成されるリードにおいて、前
記内部めっき層をＳｎあるいはＳｎ合金により構成し、
前記外部めっき層をＡｇにより構成したことを特徴とす
る電子部品用リードを提供するものである。In order to achieve the above object, the present invention provides a lead base material, an internal plating layer formed on the lead base material, and an internal plating layer formed on the internal plating layer. Wherein the inner plating layer is made of Sn or a Sn alloy,
It is another object of the present invention to provide a lead for an electronic component, wherein the external plating layer is made of Ag.
【００１０】上記のリード母材としては、たとえば、対
象が電子機器の配線に使用されるリードであれば、銅、
あるいは銅合金等から構成されたワイヤーが使用され
る。リードフレームを使用した半導体装置のアウターリ
ードが、本発明におけるリード母材を構成する用途は可
能であり、また、リードフレームの代わりに銅箔の配線
パターンと絶縁フィルムを積層したテープキャリアを使
用し、これにより構成される半導体装置のアウターリー
ドに本発明を適用することも可能である。The above-mentioned lead base material may be, for example, copper or copper if the object is a lead used for wiring of electronic equipment.
Alternatively, a wire made of a copper alloy or the like is used. The outer lead of a semiconductor device using a lead frame can be used to constitute a lead base material in the present invention, and a tape carrier in which a copper foil wiring pattern and an insulating film are laminated in place of the lead frame is used. It is also possible to apply the present invention to the outer leads of the semiconductor device constituted by this.
【００１１】内部めっき層を構成するＳｎ合金として
は、Ｓｎ‐Ｂｉ合金、Ｓｎ‐Ｓｂ合金、Ｓｂ‐Ｉｎ合金
などが使用される。内部および外部に、Ｓｎ系のめっき
層とＡｇのめっき層を形成した本発明の電子部品用リー
ドは、伸線アニールとスキンパス加工（塑性流動を起こ
させない加工）を施されることが好ましい。As the Sn alloy constituting the internal plating layer, a Sn-Bi alloy, a Sn-Sb alloy, a Sb-In alloy or the like is used. It is preferable that the lead for electronic parts of the present invention in which the Sn-based plating layer and the Ag plating layer are formed inside and outside are subjected to wire drawing annealing and skin pass processing (processing that does not cause plastic flow).
【００１２】外部めっき層を構成するＡｇには、伸線ア
ニールとスキンパス加工を経ることによって、Ｓｎある
いはＳｎ合金めっき層の中に拡散する性質があり、従っ
て、これにより、リード母材の表面には、Ｓｎ‐Ａｇ合
金、Ｓｎ‐Ｂｉ‐Ａｇ合金、Ｓｎ‐Ｓｂ‐Ａｇ合金、あ
るいはＳｎ‐Ｉｎ‐Ａｇ合金等のＳｎ‐Ａｇ系めっき層
が形成されることになる。The Ag constituting the external plating layer has a property of diffusing into the Sn or Sn alloy plating layer through wire drawing annealing and skin pass processing. Means that a Sn-Ag-based plating layer such as a Sn-Ag alloy, a Sn-Bi-Ag alloy, a Sn-Sb-Ag alloy, or a Sn-In-Ag alloy is formed.
【００１３】これらの合金めっき層は、リード母材への
密着性、はんだ濡れ性（はんだ付け性）、耐変色性、お
よびウイスカー性において、特に良好な特性を示し、Ｓ
ｎ‐Ｐｂめっきに劣らない特性を有することが確認され
た。[0013] These alloy plating layers exhibit particularly good characteristics in adhesion to the lead base material, solder wettability (solderability), discoloration resistance, and whisker properties.
It was confirmed that it had characteristics not inferior to n-Pb plating.
【００１４】[0014]
【発明の実施の形態】次に、本発明による電子部品用リ
ードの実施の形態について説明する。図１は、本実施形
態における電子部品用リードの断面構造を示したもの
で、１は外径０．６ｍｍの銅合金ワイヤー、２は銅合金
ワイヤー１の上に形成された内部めっき層、３は内部め
っき層２の上に形成された外部めっき層を示す。Next, an embodiment of an electronic component lead according to the present invention will be described. FIG. 1 shows a cross-sectional structure of an electronic component lead according to the present embodiment, wherein 1 is a copper alloy wire having an outer diameter of 0.6 mm, 2 is an internal plating layer formed on the copper alloy wire 1, Indicates an external plating layer formed on the internal plating layer 2.
【００１５】[0015]
【実施例１】酸洗したワイヤー１の上に、厚さ６μｍの
Ｓｎの内部めっき層２を電解法により形成し、次いで、
これに、同じく電解法により厚さ０．０５μｍのＡｇの
外部めっき層３を形成し、所定の電子部品用リードを得
た。Example 1 An inner plating layer 2 of Sn having a thickness of 6 μm was formed on a pickled wire 1 by an electrolytic method.
An external plating layer 3 of Ag having a thickness of 0.05 μm was similarly formed thereon by the electrolytic method to obtain predetermined electronic component leads.
【００１６】内部めっき層２は、有機スルフォン酸系の
めっき液を使用し、電流密度４Ａ／ｄｍ2 およびめっき
時間３分の条件のもとで成膜させ、一方、外部めっき層
３は、シアン系のめっき液を使用し、電流密度２Ａ／ｄ
ｍ2 、めっき時間１０秒の条件下で成膜させた。成膜
後、これに伸線アニールとスキンパス工程を施すことに
より、所定の電子部品用リードとした。The inner plating layer 2 is formed by using an organic sulfonic acid-based plating solution under the conditions of a current density of 4 A / dm 2 and a plating time of 3 minutes. Current density 2A / d
The film was formed under the conditions of m 2 and a plating time of 10 seconds. After the film was formed, the wire was subjected to wire drawing annealing and a skin pass process to obtain a predetermined electronic component lead.
【００１７】[0017]
【実施例２】実施例１において、内部めっき層２の構成
材をＳｎ‐Ｂｉ合金とした以外、他を同一条件とするこ
とにより所定の電子部品用リードを得た。Example 2 A predetermined lead for an electronic component was obtained under the same conditions as in Example 1 except that the constituent material of the internal plating layer 2 was an Sn—Bi alloy.
【００１８】[0018]
【実施例３】実施例１において、内部めっき層２の構成
材をＳｎ‐Ｓｂ合金とした以外、他を同一条件とするこ
とにより所定の電子部品用リードを得た。Example 3 A predetermined electronic component lead was obtained under the same conditions as in Example 1 except that the constituent material of the internal plating layer 2 was an Sn—Sb alloy.
【００１９】[0019]
【実施例４】実施例１において、内部めっき層２の構成
材をＳｎ‐Ｉｎ合金とした以外、他を同一条件とするこ
とにより所定の電子部品用リードを得た。Example 4 A predetermined lead for an electronic component was obtained under the same conditions as in Example 1 except that the constituent material of the internal plating layer 2 was an Sn-In alloy.
【００２０】[0020]
【従来例】図２において、銅合金ワイヤー１の上に厚さ
６μｍのＳｎ‐Ｐｂ合金めっき層４を電解法により形成
し、所定の電子部品用リードを得た。2. Prior Art Referring to FIG. 2, a Sn-Pb alloy plating layer 4 having a thickness of 6 .mu.m was formed on a copper alloy wire 1 by an electrolytic method to obtain predetermined leads for electronic parts.
【００２１】[0021]
【参考例】図２において、めっき層４を電解法による厚
さ６μｍのＳｎめっきにより形成し、所定の電子部品用
リードを得た。REFERENCE EXAMPLE In FIG. 2, a plating layer 4 was formed by Sn plating with a thickness of 6 μm by an electrolytic method to obtain predetermined electronic component leads.
【００２２】表１に、以上の実施例、従来例、および参
考例により得られた電子部品用リードの特性試験結果を
示す。試験項目としては、めっき層の密着性、はんだ濡
れ性、耐変色性、およびウイスカーの発生有無を選択し
た。Table 1 shows the characteristic test results of the leads for electronic parts obtained in the above Examples, Conventional Examples and Reference Examples. As test items, adhesion of the plating layer, solder wettability, discoloration resistance, and presence or absence of whiskers were selected.
【００２３】めっき層の密着性は、水素雰囲気中におい
てサンプルを３５０℃で１５分間加熱し、引き続きこれ
を大気中において２５０℃で２時間加熱した後、自己径
巻き付けを行ったときのめっき層の剥離の有無によって
評価した。The adhesion of the plating layer was determined by heating the sample in a hydrogen atmosphere at 350 ° C. for 15 minutes, subsequently heating the sample in the air at 250 ° C. for 2 hours, and then performing self-diameter winding. The evaluation was based on the presence or absence of peeling.
【００２４】自己径巻き付けは、サンプルの一端をバイ
スに挟み、他端を９０°に曲げた状態で固定することに
よりサンプルを所定の個所に張り、これに９０°に曲げ
た部分を支点としてサンプルを数１０回巻き付けること
によって行った。この試験で、めっき層に剥離が発生し
ない場合を１、若干の剥離発生を２、完全な剥離発生を
３とした。The self-diameter winding is performed by sandwiching one end of a sample between vise and fixing the other end in a state bent at 90 ° so that the sample is stretched at a predetermined position, and the sample bent at 90 ° is used as a fulcrum. Was wound several tens of times. In this test, the case where no peeling occurred in the plating layer was designated as 1, the slight peeling occurred as 2, and the complete peeling occurred as 3.
【００２５】はんだ濡れ性は、ＭＩＬ−ＳＴＤ−２０２
Ｄ−２０８Ｂの試験法に基づき、フラックスなしの状態
で密着性試験におけるのと同じ加熱処理を施したとき
の、はんだ濡れ面積によって評価した。濡れ面積が９０
％以上を１、７０〜９０％未満を２、７０％未満を３と
した。The solder wettability was determined by MIL-STD-202.
Based on the test method of D-208B, the evaluation was made based on the solder wetting area when the same heat treatment as in the adhesion test was performed in the state of no flux. 90 wet area
% Or more, 1, 70 to less than 90% was 2, and less than 70% was 3.
【００２６】耐変色性は、４０℃／９５％ＲＨの恒温恒
湿の雰囲気にサンプルを１０日間放置したときの変色の
有無により評価し、変色なしを１、若干変色を２、変色
を３とした。The discoloration resistance was evaluated by the presence or absence of discoloration when the sample was allowed to stand for 10 days in an atmosphere of constant temperature and humidity of 40 ° C./95% RH. did.
【００２７】ウイスカーの発生有無は、１２１℃／６０
％ＲＨの恒温恒湿の雰囲気にサンプルを２４時間放置し
た後の目視判定によって確認した。発生なしを１、若干
発生を２、発生を３とした。The presence or absence of whiskers is determined at 121 ° C./60.
The sample was allowed to stand in a constant temperature and constant humidity atmosphere of% RH for 24 hours, and was confirmed by visual judgment. No occurrence was set to 1, slight occurrence was set to 2, and occurrence was set to 3.
【００２８】[0028]
【表１】 [Table 1]
【００２９】表１によれば、実施例による電子部品用リ
ードが、めっき層の密着性、はんだ濡れ性、耐変色性、
およびウイスカー発生有無のいずれにおいても従来例と
同じ１の評価を得ている。According to Table 1, the lead for an electronic component according to the embodiment has a good adhesion of a plating layer, solder wettability, discoloration resistance, and the like.
Regarding the occurrence of whiskers and the presence / absence of whiskers, the same evaluation as the conventional example was obtained.
【００３０】これらの項目は、従来、長い間にわたって
電子部品の接合プロセスに定着してきたＳｎ‐Ｐｂ合金
めっきリードの特性を評価するための試験項目であり、
従って、これらの試験項目において、Ｓｎ‐Ｐｂ合金め
っきリードと遜色のない試験結果を示していることは、
本発明によるリードが、Ｓｎ‐Ｐｂ合金めっきリードに
代わる電子部品用リードとして、有効に活用可能なこと
を意味している。Ｓｎめっき層を形成した参考例のリー
ドの場合には、ウイスカー発生有無のテスト結果が悪
く、実用性において問題がある。These items are test items for evaluating the characteristics of Sn—Pb alloy plating leads that have long been established in the joining process of electronic components for a long time.
Therefore, in these test items, it shows that the test results are comparable to those of Sn-Pb alloy plating leads.
This means that the lead according to the present invention can be effectively used as a lead for electronic components instead of a Sn-Pb alloy plating lead. In the case of the lead of the reference example in which the Sn plating layer is formed, the test result of the presence or absence of whisker is poor, and there is a problem in practicality.
【００３１】[0031]
【発明の効果】以上説明したように、本発明による電子
部品用リードによれば、リード母材の上にＳｎあるいは
Ｓｎ合金の内部めっき層と、Ａｇの外部めっき層を順に
形成したため、これまで多用されてきたＳｎ‐Ｐｂ合金
めっきリードと同等の特性を有しながら地下水を汚染す
ることもなく、また、ウイスカーの発生および変色の抑
制によって信頼性を高めることができる。As described above, according to the lead for electronic parts of the present invention, the inner plating layer of Sn or Sn alloy and the outer plating layer of Ag are sequentially formed on the lead base material. It has the same characteristics as the Sn-Pb alloy plating lead, which has been widely used, without polluting groundwater, and can improve reliability by suppressing generation of whiskers and discoloration.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明による電子部品用リードの実施の形態を
示す説明図。FIG. 1 is an explanatory view showing an embodiment of an electronic component lead according to the present invention.
【図２】従来の電子部品用リードの説明図。FIG. 2 is an explanatory view of a conventional electronic component lead.
２ 内部めっき層 ３ 外部めっき層 2 Internal plating layer 3 External plating layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉岡 修 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 Ｆターム(参考） 4K024 AA10 AA21 AB02 BA09 BB09 BB10 BC03 DA03 DB01 DB07 GA14 GA16 5F067 AA04 AA09 DC12 DC18 EA04 ──────────────────────────────────────────────────続 き Continued on the front page (72) Osamu Yoshioka, 3550 Kida Yomachi, Tsuchiura-shi, Ibaraki F-term in the System Materials Research Laboratory, Hitachi Cable, Ltd. AA04 AA09 DC12 DC18 EA04
Claims (5)
された内部めっき層と、前記内部めっき層の上に形成さ
れた外部めっき層から構成されるリードにおいて、 前記内部めっき層をＳｎあるいはＳｎ合金により構成
し、 前記外部めっき層をＡｇにより構成したことを特徴とす
る電子部品用リード。1. A lead comprising a lead base material, an internal plating layer formed on the lead base material, and an external plating layer formed on the internal plating layer, wherein the internal plating layer is A lead for an electronic component, wherein the lead is made of Sn or a Sn alloy, and the external plating layer is made of Ag.
Ｓｂ合金、Ｓｎ‐Ｉｎ合金のいずれかであることを特徴
とする請求項第１項記載の電子部品用リード。2. The Sn alloy according to claim 1, wherein the Sn alloy is an Sn—Bi alloy,
2. The lead according to claim 1, wherein the lead is one of an Sb alloy and a Sn-In alloy.
から構成されるワイヤーであることを特徴とする請求項
第１項あるいは第２項記載の電子部品用リード。3. The electronic component lead according to claim 1, wherein said lead base material is a wire made of copper, a copper alloy, or the like.
加工を施されたことを特徴とする請求項第１項ないし第
３項のいずれかに記載の電子部品用リード。4. The lead for an electronic component according to claim 1, wherein said lead has been subjected to wire drawing annealing and skin pass processing.
リードであることを特徴とする請求項第１項ないし第３
項のいずれかに記載の電子部品用リード。5. The semiconductor device according to claim 1, wherein said lead base material is an outer lead of a semiconductor device.
Item 14. An electronic component lead according to any one of the above items.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10329714A JP2000156450A (en) | 1998-11-19 | 1998-11-19 | Lead for electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10329714A JP2000156450A (en) | 1998-11-19 | 1998-11-19 | Lead for electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000156450A true JP2000156450A (en) | 2000-06-06 |
Family
ID=18224457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10329714A Pending JP2000156450A (en) | 1998-11-19 | 1998-11-19 | Lead for electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000156450A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005002368A (en) * | 2003-06-09 | 2005-01-06 | Ishihara Chem Co Ltd | Tin plating bath for preventing whisker |
| JP2007046150A (en) * | 2005-04-06 | 2007-02-22 | Misuzu:Kk | Lead wire for electronic part and flat cable comprising the same |
| JP2007100148A (en) * | 2005-10-03 | 2007-04-19 | C Uyemura & Co Ltd | Whisker-suppressive surface treating method |
| US7501578B2 (en) * | 2002-12-18 | 2009-03-10 | Paolo Agostinelli | Electric conductors |
| WO2015147213A1 (en) * | 2014-03-26 | 2015-10-01 | 新日鉄住金マテリアルズ株式会社 | Conductor, and solar-cell interconnector |
| WO2020071002A1 (en) * | 2018-10-01 | 2020-04-09 | 富山住友電工株式会社 | Method and device for manufacturing plated wire |
-
1998
- 1998-11-19 JP JP10329714A patent/JP2000156450A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7501578B2 (en) * | 2002-12-18 | 2009-03-10 | Paolo Agostinelli | Electric conductors |
| JP2005002368A (en) * | 2003-06-09 | 2005-01-06 | Ishihara Chem Co Ltd | Tin plating bath for preventing whisker |
| JP2007046150A (en) * | 2005-04-06 | 2007-02-22 | Misuzu:Kk | Lead wire for electronic part and flat cable comprising the same |
| JP2007100148A (en) * | 2005-10-03 | 2007-04-19 | C Uyemura & Co Ltd | Whisker-suppressive surface treating method |
| WO2015147213A1 (en) * | 2014-03-26 | 2015-10-01 | 新日鉄住金マテリアルズ株式会社 | Conductor, and solar-cell interconnector |
| WO2020071002A1 (en) * | 2018-10-01 | 2020-04-09 | 富山住友電工株式会社 | Method and device for manufacturing plated wire |
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