JP2000150709A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JP2000150709A
JP2000150709A JP32246298A JP32246298A JP2000150709A JP 2000150709 A JP2000150709 A JP 2000150709A JP 32246298 A JP32246298 A JP 32246298A JP 32246298 A JP32246298 A JP 32246298A JP 2000150709 A JP2000150709 A JP 2000150709A
Authority
JP
Japan
Prior art keywords
semiconductor package
solder
memory alloy
shape memory
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32246298A
Other languages
Japanese (ja)
Inventor
Wataru Oikawa
渉 及川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP32246298A priority Critical patent/JP2000150709A/en
Publication of JP2000150709A publication Critical patent/JP2000150709A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package which is high in bonding strength to a mounting board and excellent in solder jointing reliability when the semiconductor package is mounted on a mounting board by solder joint. SOLUTION: This BGA semiconductor package 50 is equipped with two support poles 52 of shape memory alloy located at the opposed peripheral parts of an interposer board 12. The support pole 52 is extended along the underside of the interposer board 12 at a critical temperature or below, made to protrude downward from the underside of the interposer board 12, and extended at a critical temperature or above. When the semiconductor package 50 is mounted on a mounting board 28, the semiconductor package 50 is mounted on the mounting board 28 at an accurate position first and then heated in an reflow oven to melt the solder balls. While the solder balls are melted, the support poles 52 of shape memory alloy provided to the semiconductor package 50 are made to protrude and extended downward by the heat of the reflow oven. The semiconductor package is pushed up by the support poles 52, so that solder joint 54 is formed like a column or a barrel getting from constriction and becomes excellent in shape where no stress is concentrated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半田接合により実
装基板に実装する半導体パッケージ、例えばBGA型半
導体パッケージ、LGA半導体パッケージ等の半導体パ
ッケージに関し、更に詳細には、半田接合により実装す
る際、実装基板との間の接合強度が高く、長期にわたり
高い半田接合信頼性を有するBGA型半導体パッケージ
又はLGA半導体パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package mounted on a mounting board by solder bonding, for example, a semiconductor package such as a BGA type semiconductor package or an LGA semiconductor package. The present invention relates to a BGA type semiconductor package or an LGA semiconductor package having a high bonding strength with a substrate and having high solder bonding reliability for a long time.

【0002】[0002]

【従来の技術】BGA型半導体パッケージ10は、半導
体装置の高集積化に伴い開発された方式の半導体パッケ
ージであって、従来、図5(a)に示すように、ガラス
エポキシ樹脂等のインタポーザ基板12と、インタポー
ザ基板12上にエポキシ系接着剤等で接着された半導体
チップ14と、インタポーザ基板12の複数個の下面電
極16上に形成された半田ボール18とから構成されて
いる。
2. Description of the Related Art A BGA type semiconductor package 10 is a semiconductor package of a type developed with an increase in the degree of integration of a semiconductor device. Conventionally, as shown in FIG. The semiconductor device comprises a semiconductor chip 14 bonded to the interposer substrate 12 with an epoxy-based adhesive or the like, and solder balls 18 formed on a plurality of lower electrodes 16 of the interposer substrate 12.

【0003】半導体チップ14は、上面に電極パッド2
0を有し、電極パッド20は、ボンディングワイヤ22
によりインタポーザ基板12上の印刷配線24に接続さ
れている。半導体チップ14は、ボンディングされた状
態で封止用樹脂26によりオーバーモールドされてい
る。インタポーザ基板12の下面に設けられた多数個の
下面電極16は、印刷配線24、ボンディングワイヤ2
2及び電極パッド20を介して、半導体チップ14の回
路に接続されている。各下面電極16には、電極ピッチ
の約1/2の直径を有する球形の半田ボール18が固着
されている。
The semiconductor chip 14 has electrode pads 2 on the upper surface.
0, and the electrode pad 20 is
Is connected to the printed wiring 24 on the interposer substrate 12. The semiconductor chip 14 is overmolded with a sealing resin 26 in a bonded state. A large number of lower electrodes 16 provided on the lower surface of the interposer substrate 12
2 and the electrode pads 20 are connected to the circuit of the semiconductor chip 14. A spherical solder ball 18 having a diameter of about の of the electrode pitch is fixed to each lower surface electrode 16.

【0004】BGA型半導体パッケージ10を実装基板
28上に実装する際には、半導体パッケージ10を実装
基板28上に配置してリフロー炉に送入し、半田ボール
18を溶融、固化して、図5(b)に示すように、イン
タポーザ基板12の下面電極16と実装基板28の電極
30との間に半田接合部32を形成する。
When the BGA type semiconductor package 10 is mounted on the mounting substrate 28, the semiconductor package 10 is placed on the mounting substrate 28 and is sent to a reflow furnace, where the solder balls 18 are melted and solidified. As shown in FIG. 5B, a solder joint 32 is formed between the lower electrode 16 of the interposer substrate 12 and the electrode 30 of the mounting substrate 28.

【0005】また、LGA半導体パッケージ40は、同
じく、半導体装置の高集積化に伴い開発された方式の半
導体パッケージであって、図6(b)に示すように、ガ
ラスエポキシ樹脂等のインタポーザ基板12と、インタ
ポーザ基板12上にエポキシ系接着剤等で接着された半
導体チップ14と、インタポーザ基板12の下面電極兼
半田ランド42とから構成されている。半導体チップ1
4は、上述のBGA型半導体パッケージ10と同様に、
上面に電極パッド20を有し、電極パッド20は、ボン
ディングワイヤ22によりインタポーザ基板12上の印
刷配線24に接続されている。半導体チップ14は、ボ
ンディングされた状態で封止用樹脂26によりオーバー
モールドされている。インタポーザ基板12の下面に設
けられた多数個の下面電極兼半田ランド42は、印刷配
線24、ボンディングワイヤ22及び電極パッド20を
介して、半導体チップ14の回路に接続されている。
[0005] The LGA semiconductor package 40 is a semiconductor package of a type developed in accordance with high integration of a semiconductor device. As shown in FIG. 6B, the interposer substrate 12 made of glass epoxy resin or the like is used. And a semiconductor chip 14 bonded to the interposer substrate 12 with an epoxy-based adhesive or the like, and a lower surface electrode / solder land 42 of the interposer substrate 12. Semiconductor chip 1
4 is similar to the above-mentioned BGA type semiconductor package 10,
An electrode pad 20 is provided on the upper surface, and the electrode pad 20 is connected to a printed wiring 24 on the interposer substrate 12 by a bonding wire 22. The semiconductor chip 14 is overmolded with a sealing resin 26 in a bonded state. A large number of lower surface electrodes and solder lands 42 provided on the lower surface of the interposer substrate 12 are connected to the circuit of the semiconductor chip 14 via the printed wiring 24, the bonding wires 22 and the electrode pads 20.

【0006】LGA型半導体パッケージ40を実装基板
28上に実装する際には、半導体パッケージ40の半田
ランド42に半田ペースト(図示せず)を塗布し、次い
で実装基板28上に半導体パッケージ40を配置して一
緒にリフロー炉に送入する。これにより、半田ペースト
を溶融、固化して、図6(b)に示すように、インタポ
ーザ基板12の下面電極兼半田ランド42と実装基板2
8の電極30との間に半田接合部44を形成する。
When mounting the LGA type semiconductor package 40 on the mounting board 28, a solder paste (not shown) is applied to the solder lands 42 of the semiconductor package 40, and then the semiconductor package 40 is placed on the mounting board 28. And send it to the reflow furnace together. Thus, the solder paste is melted and solidified, and as shown in FIG. 6B, the lower surface electrode / solder land 42 of the interposer substrate 12 and the mounting substrate 2
The solder joints 44 are formed between the electrodes 30 and 8.

【0007】[0007]

【発明が解決しようとする課題】インタポーザ基板2の
下面電極16又は半田ランド42と実装基板28の電極
30との間に形成される半田接合部32又は44の好ま
しい形状が、図7に示すように、円柱状若しくは鼓状で
あるにもかかわらず、上述のように、現在の実装方法に
従って実装したBGA半導体パッケージ10及びLGA
半導体パッケージ40と実装基板28との間に形成され
る半田接合部32、44は、図5(b)に示すように、
球状に、または図6(b)に示すように、偏平な円板状
になっている。その結果、温度サイクルによるストレス
及び外部応力は、半田接合部32、44のくびれに集中
する。そのため、くびれに集中したストレス又は外部応
力によって、そのくびれに亀裂が入り、やがて半田接合
部32、44がインターポーザ基板12から剥離し、実
装基板28との電気的及び機械的接合が破壊される。
The preferred shape of the solder joint 32 or 44 formed between the lower electrode 16 or the solder land 42 of the interposer substrate 2 and the electrode 30 of the mounting substrate 28 is as shown in FIG. In addition, as described above, the BGA semiconductor package 10 and the LGA mounted in accordance with the current mounting method despite being cylindrical or drum-shaped
As shown in FIG. 5B, the solder joints 32 and 44 formed between the semiconductor package 40 and the mounting board 28
As shown in FIG. 6 (b), it has a flat disk shape. As a result, the stress due to the temperature cycle and the external stress concentrate on the constriction of the solder joints 32 and 44. For this reason, stress or external stress concentrated on the constriction causes a crack in the constriction, and the solder joints 32 and 44 are separated from the interposer substrate 12 and the electrical and mechanical connection with the mounting substrate 28 is broken.

【0008】また、LGA半導体パッケージ40の場
合、その構造上から、図6(b)に示すように、実装基
板28と電極半田ランド42との間隔が短いため、実装
した際、温度サイクルにより発生するストレスが増大
し、半田接合部44の強度的信頼性及び寿命に不安があ
る。
In the case of the LGA semiconductor package 40, due to its structure, as shown in FIG. 6B, the distance between the mounting substrate 28 and the electrode solder lands 42 is short. Stress increases, and there is concern about the strength reliability and life of the solder joint 44.

【0009】そこで、本発明の目的は、半田接合により
実装する際、実装基板との間の接合強度が高く、長期に
わたり高い半田接合信頼性を有するBGA型半導体パッ
ケージ又はLGA半導体パッケージを提供することであ
る。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a BGA type semiconductor package or an LGA semiconductor package which has a high bonding strength with a mounting substrate when mounted by solder bonding and has a long-term high reliability of solder bonding. It is.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る半導体パッケージ(以下、第1の発明
と言う)は、半田接合により実装基板に実装する半導体
パッケージにおいて、半導体パッケージの下面の対向す
る両周縁部に、それぞれ、形状記憶合金製の棒状の支持
柱を備え、支持柱は、変態点以上の温度では下面に沿っ
て延在し、形状記憶合金の変態点以上の温度では、半導
体パッケージの下面から下方に突起、延在することを特
徴としている。
In order to achieve the above object, a semiconductor package according to the present invention (hereinafter referred to as a first invention) is a semiconductor package mounted on a mounting board by solder bonding. Each of the opposing peripheral edges of the lower surface has a rod-shaped support column made of a shape memory alloy, and the support column extends along the lower surface at a temperature equal to or higher than the transformation point, and has a temperature equal to or higher than the transformation point of the shape memory alloy. Is characterized in that it protrudes and extends downward from the lower surface of the semiconductor package.

【0011】また、本発明に係る別の半導体パッケージ
(以下、第2の発明と言う)は、半田接合により実装基
板に実装する半導体パッケージにおいて、半導体パッケ
ージの下面の対向する両周縁部に、それぞれ、形状記憶
合金製のコイルバネ状の支持柱を備え、支持柱は、形状
記憶合金の変態点以下の温度では、半導体パッケージの
下面から上方に収縮し、変態点以上の温度では伸長して
下面から下方に突起、延在することを特徴としている。
Another semiconductor package according to the present invention (hereinafter, referred to as a second invention) is a semiconductor package mounted on a mounting board by solder bonding. And a support pillar in the form of a coil spring made of a shape memory alloy.The support pillar contracts upward from the lower surface of the semiconductor package at a temperature lower than the transformation point of the shape memory alloy, and expands from the lower surface at a temperature higher than the transformation point. It is characterized in that it protrudes downward and extends.

【0012】第1及び第2発明に係る半導体パッケージ
では、好適には、支持柱が、190°以上250℃以下
の範囲の温度を変態点とする形状記憶合金で形成されて
いて、半田ボール又は半田ランド上の半田ペーストが溶
融する温度、即ち共晶半田の融点、183℃以上の温
度、例えば200℃で形状記憶合金製の支持柱が下方に
延在することにより、或いは下方に伸長することによ
り、支持柱が実装基板に対して半導体パッケージを所定
間隔に保持する。言わば、形状記憶合金製の支持柱が、
実装基板と半導体パッケージとの間隔を所定寸法に保持
するスペーサとして機能することにより、円柱状又は鼓
状の良好な形状の半田接合部を形成することができる。
所定寸法とは、0.1mm以上2mm以下である。本発明で
は、形状記憶合金として、Fe系の形状記憶合金、Cu
−Al−Ni合金、Cu−Zn−Al合金、Ni−Ti
合金、Au−Cd合金等を使用することができる。
In the semiconductor package according to the first and second aspects of the present invention, preferably, the support pillar is formed of a shape memory alloy whose transformation point is in a temperature range of 190 ° C. to 250 ° C. At the temperature at which the solder paste on the solder land melts, that is, the melting point of eutectic solder, at a temperature of 183 ° C. or higher, for example, 200 ° C., the support column made of a shape memory alloy extends downward or extends downward. Accordingly, the support pillar holds the semiconductor package at a predetermined interval with respect to the mounting substrate. In other words, the support pillar made of shape memory alloy,
By functioning as a spacer for maintaining the distance between the mounting substrate and the semiconductor package at a predetermined size, a solder joint having a good cylindrical or drum-like shape can be formed.
The predetermined dimension is 0.1 mm or more and 2 mm or less. In the present invention, as a shape memory alloy, an Fe-based shape memory alloy, Cu
-Al-Ni alloy, Cu-Zn-Al alloy, Ni-Ti
An alloy, an Au-Cd alloy, or the like can be used.

【0013】本発明は、半田接合により半田接合により
実装する方式の半導体パッケージに適用できるが、好適
には、半導体パッケージがBGA(Ball Grid Allay )
半導体パッケージ又はLGA(Land Grid Allay )半導
体パッケージに適用する。
The present invention can be applied to a semiconductor package of a type which is mounted by soldering by soldering. Preferably, the semiconductor package is a BGA (Ball Grid Allay).
It is applied to a semiconductor package or an LGA (Land Grid Allay) semiconductor package.

【0014】半田ペーストを印刷したプリント配線板上
に半導体パッケージを配置した後、リフロー炉で半田を
溶融する。その際、半導体パッケージの側面又は内部に
組み込まれていた形状記憶合金の支持柱が、リフロー炉
の温度により突起して伸び、支持柱の役割を果して、半
導体パッケージを押し上げる。これにより、半導体パッ
ケージと実装基板との間の間隔が所定間隔に強制的に保
持されるので、溶融した半田ボールは、円柱形状もしく
は鼓型状となる。円柱状又は鼓状の半田接合部は、温度
サイクルのストレスに対して丈夫で、半田接合寿命を長
くし、信頼性を向上させることができる。
After placing the semiconductor package on the printed wiring board on which the solder paste has been printed, the solder is melted in a reflow furnace. At this time, the support column of the shape memory alloy incorporated in the side surface or the inside of the semiconductor package protrudes and expands due to the temperature of the reflow furnace, and serves as the support column to push up the semiconductor package. As a result, the gap between the semiconductor package and the mounting board is forcibly maintained at a predetermined interval, so that the molten solder ball has a cylindrical shape or a drum shape. The cylindrical or drum-shaped solder joints are robust against temperature cycling stress, prolong the solder joint life and improve reliability.

【0015】[0015]

【発明の実施の形態】以下に、実施形態例を挙げ、添付
図面を参照して、本発明の実施の形態を具体的かつ詳細
に説明する。実施形態例1 本実施形態例は、第1の発明に係る半導体パッケージの
実施形態例に一例であって、図1(a)は形状記憶合金
の変態点以下の温度状態での半導体パッケージの側面
図、図1(b)は形状記憶合金の変態点以上の温度状態
での半導体パッケージの側面図、及び図2は半導体パッ
ケージを実装基板上に半田接合した時の半田接合部の形
状を示す半導体パッケージの側面図である。本実施形態
例の半導体パッケージ50は、半田接合により実装基板
上に実装するBGA型半導体パッケージであって、図1
(a)に示すように、従来のBGA型半導体パッケージ
10の構成に加えて、インタポーザ基板12の対向する
両周縁部51A、Bに、それぞれ、形状記憶合金製の棒
状の2本の支持柱52A、Bを備えている。
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 This embodiment is an example of the embodiment of the semiconductor package according to the first invention, and FIG. 1A shows the side surface of the semiconductor package at a temperature lower than the transformation point of the shape memory alloy. FIG. 1B is a side view of the semiconductor package in a temperature state equal to or higher than the transformation point of the shape memory alloy, and FIG. 2 is a semiconductor showing a shape of a solder joint when the semiconductor package is soldered on a mounting substrate. It is a side view of a package. The semiconductor package 50 according to the present embodiment is a BGA type semiconductor package mounted on a mounting board by solder bonding.
As shown in (a), in addition to the configuration of the conventional BGA type semiconductor package 10, two opposing peripheral portions 51A and 51B of the interposer substrate 12 are each provided with two rod-shaped support columns 52A made of a shape memory alloy. , B.

【0016】本実施形態例では、形状記憶合金として、
Fe系の形状記憶合金を使用している。それ以外でも、
例えば、Cu−Al−Ni合金、Cu−Zn−Al合
金、Ni−Ti合金、Au−Cd合金等を使用すること
ができる。支持柱52は、図1(a)に示すように、形
状記憶合金の変態点以上の温度では下面に沿って延在
し、変態点以上の温度では、図1(b)に示すように、
インタポーザ基板12の下面から下方に突起、延在す
る。支持柱52として、例えば鉄系の形状記憶合金を用
いれば、組成を調整することにより、150℃〜300
℃の間で変態点を自由に設定することができるので、共
晶半田の融点、即ち183℃を越えて、半田が十分に溶
融した温度、例えば200℃では、支持柱52は、イン
タポーザ基板12の下面から下方に突起、延在する。
In this embodiment, as the shape memory alloy,
An Fe-based shape memory alloy is used. Other than that,
For example, a Cu-Al-Ni alloy, a Cu-Zn-Al alloy, a Ni-Ti alloy, an Au-Cd alloy, or the like can be used. As shown in FIG. 1A, the support pillar 52 extends along the lower surface at a temperature higher than the transformation point of the shape memory alloy, and at a temperature higher than the transformation point, as shown in FIG.
It protrudes downward from the lower surface of the interposer substrate 12 and extends. If, for example, an iron-based shape memory alloy is used as the support pillar 52, the composition is adjusted to 150 ° C. to 300 ° C.
At a temperature at which the transformation point can be freely set between ℃ and the melting point of the eutectic solder, that is, 183 ° C., and the solder is sufficiently melted, for example, at 200 ° C., the support column 52 is attached to the interposer substrate 12. And protrudes downward from the lower surface of the.

【0017】印刷機などを使用して半田ペーストを印刷
したプリント配線基板等の実装基板28上に、半導体パ
ッケージ50を実装する際には、先ず、部品装着機など
を使用して正確な位置に半導体パッケージ50を配置す
る。次いで、実装基板28と半導体パッケージ50とを
一緒にしてリフロー炉で加熱することにより、半田ボー
ル18が溶融する。半田ボール18が溶融している間
に、リフロー炉の熱により半導体パッケージ50に設け
られた形状記憶合金製の支持柱52が、突起し、下方に
延在する。支持柱52が、実装基板28に対して半導体
パッケージ50を上方に押し上げることにより、半導体
パッケージ50と実装基板28との間の間隔は、強制的
に所定寸法、例えば0.1mm以上2mm以下にに保持さ
れ、インタポーザ基板12の下面電極16と実装基板2
8の電極30との間に形成された半田接合部54は、図
2に示すように、円柱状もしくは鼓形状に形成され、く
びれの無い形状、即ち応力の集中しない良好な形状にな
る。次いで、半導体パッケージ50をリフロー炉から取
り出し、放冷して、形状記憶合金の変態点以下の温度、
例えば100℃にすると、支持柱52は、再び元の形
態、即ち、図1(a)に示すように、インタポーザ基板
12の下面に沿って延在する。
When mounting the semiconductor package 50 on a mounting board 28 such as a printed wiring board on which solder paste is printed using a printing machine or the like, first, a component mounting machine or the like is used to place the semiconductor package 50 in an accurate position. The semiconductor package 50 is arranged. Next, the solder balls 18 are melted by heating the mounting board 28 and the semiconductor package 50 together in a reflow furnace. While the solder balls 18 are being melted, the support columns 52 made of a shape memory alloy provided on the semiconductor package 50 by the heat of the reflow furnace protrude and extend downward. The support column 52 pushes the semiconductor package 50 upward with respect to the mounting board 28, thereby forcibly setting the distance between the semiconductor package 50 and the mounting board 28 to a predetermined dimension, for example, 0.1 mm or more and 2 mm or less. The lower electrode 16 of the interposer substrate 12 and the mounting substrate 2 are held.
As shown in FIG. 2, the solder joint 54 formed between the electrode 8 and the electrode 8 is formed in a columnar or drum shape, and has a shape without constriction, that is, a favorable shape in which stress is not concentrated. Next, the semiconductor package 50 is taken out of the reflow furnace and allowed to cool to a temperature below the transformation point of the shape memory alloy.
For example, when the temperature is set to 100 ° C., the support columns 52 again extend in the original form, that is, along the lower surface of the interposer substrate 12, as shown in FIG.

【0018】実施形態例2 本実施形態例は、第2の発明に係る半導体パッケージの
実施形態例に一例であって、図3(a)は形状記憶合金
の変態点以下の温度状態での半導体パッケージの側面
図、図3(b)は形状記憶合金の変態点以上の温度状態
での半導体パッケージの側面図、及び、図4は半導体パ
ッケージを実装基板上に半田接合した時の半田接合部の
形状を示す半導体パッケージの側面図である。本実施形
態例の半導体パッケージ60は、半田接合により実装す
るBGA半導体パッケージであって、従来のBGA型半
導体パッケージ10の構成に加えて、図3(a)に示す
ように、半導体パッケージ10の下面の対向する両周縁
部12A、Bに、それぞれ、形状記憶合金製のコイルバ
ネ状の支持柱62を備えている。
Embodiment 2 This embodiment is an example of an embodiment of a semiconductor package according to the second invention. FIG. 3A shows a semiconductor package at a temperature lower than the transformation point of a shape memory alloy. FIG. 3B is a side view of the semiconductor package at a temperature equal to or higher than the transformation point of the shape memory alloy, and FIG. 4 is a view of a solder joint when the semiconductor package is solder-joined on a mounting board. It is a side view of the semiconductor package which shows a shape. The semiconductor package 60 of the present embodiment is a BGA semiconductor package mounted by soldering. In addition to the configuration of the conventional BGA type semiconductor package 10, as shown in FIG. Are provided with coil spring-shaped support columns 62 made of a shape memory alloy, respectively.

【0019】支持柱62は、形状記憶合金の変態点以下
の温度では、図3(a)に示すように、下端に開口を有
してインタポーザ基板12内に下向きに設けられた空洞
64内に収縮した状態で存在し、変態点以上の温度で
は、図3(b)に示すように、インタポーザ基板12の
下面から下方に伸長して突起する。本実施形態例では、
形状記憶合金として、Fe系の形状記憶合金を使用して
いる。それ以外でも、例えば、Cu−Al−Ni合金、
Cu−Zn−Al合金、Ni−Ti合金、Au−Cd合
金等を使用することができる。支持柱14に鉄系の形状
記憶合金を用いれば、組成を調整することにより、15
0℃〜300℃の間で変態点を自由に設定することがで
きるので、共晶半田の融点、即ち183℃を越えて、半
田が十分に溶融した温度、例えば200℃では、支持柱
62は、伸長して、空洞64から下方に突起する。
At a temperature equal to or lower than the transformation point of the shape memory alloy, the support column 62 is placed in a cavity 64 having an opening at the lower end and provided downward in the interposer substrate 12, as shown in FIG. It exists in a contracted state and, at a temperature equal to or higher than the transformation point, extends downward from the lower surface of the interposer substrate 12 and protrudes, as shown in FIG. In the present embodiment,
As the shape memory alloy, an Fe-based shape memory alloy is used. Other than that, for example, Cu-Al-Ni alloy,
A Cu-Zn-Al alloy, a Ni-Ti alloy, an Au-Cd alloy, or the like can be used. If an iron-based shape memory alloy is used for the support pillars 14, by adjusting the composition,
Since the transformation point can be set freely between 0 ° C. and 300 ° C., the temperature exceeds the melting point of eutectic solder, that is, 183 ° C., and the temperature at which the solder is sufficiently melted, for example, 200 ° C. , Extending and protruding downward from the cavity 64.

【0020】印刷機などを使用して半田ペーストを印刷
したプリント配線基板等の実装基板28上に、半導体パ
ッケージ60を実装する際には、先ず、部品装着機など
を使用して正確な位置に半導体パッケージ60を装着す
る。次いで、実装基板28と半導体パッケージ60とを
一緒にしてリフロー炉で加熱することにより、半田ボー
ル18が溶融する。半田ボール18が溶融している間
に、リフロー炉の熱により半導体パッケージ60に設け
られた形状記憶合金製の支持柱62が突起し、下方に延
在する。支持柱62が、図4に示すように、半導体パッ
ケージ60を上方に押し上げることにより、半導体パッ
ケージ60と実装基板28との間の間隔は、強制的に所
定寸法、例えば0.1mm以上2mm以下にに保持され、半
田接合部66は、円柱状もしくは鼓形状に形成され、く
びれの無い形状、即ち応力の集中しない良好な形状にな
る。次いで、半導体パッケージ10がリフロー炉から取
り出されて、放冷され、形状記憶合金の変態点以下の温
度、例えば100℃になると、支持柱62は、再び元の
形態、即ち空洞64内に収縮する。
When mounting the semiconductor package 60 on a mounting board 28 such as a printed wiring board on which solder paste has been printed using a printing machine or the like, first, a component mounting machine or the like is used to place the semiconductor package 60 in an accurate position. The semiconductor package 60 is mounted. Next, the solder ball 18 is melted by heating the mounting board 28 and the semiconductor package 60 together in a reflow furnace. While the solder ball 18 is being melted, the support pillar 62 made of a shape memory alloy provided on the semiconductor package 60 is protruded by the heat of the reflow furnace and extends downward. The support column 62 pushes the semiconductor package 60 upward as shown in FIG. 4, thereby forcibly setting the distance between the semiconductor package 60 and the mounting board 28 to a predetermined dimension, for example, 0.1 mm or more and 2 mm or less. The solder joint 66 is formed in a columnar or drum shape, and has a shape without constriction, that is, a good shape in which stress is not concentrated. Next, when the semiconductor package 10 is taken out of the reflow furnace and allowed to cool, and reaches a temperature below the transformation point of the shape memory alloy, for example, 100 ° C., the support pillar 62 contracts again into its original shape, that is, into the cavity 64. .

【0021】上述の例では、BGA型半導体パッケージ
を例にして説明したが、当然に、本発明はLGA型半導
体パッケージにも適用できる。
In the above-described example, the BGA type semiconductor package has been described as an example, but the present invention is naturally applicable to an LGA type semiconductor package.

【0022】[0022]

【発明の効果】以上、説明したように、本発明によれ
ば、形状記憶合金製の支持柱をスペーサとして用いるこ
とにより、半導体パッケージと実装基板との間の間隔を
強制的に所定寸法、例えば0.1mm以上2mm以下にに保
持することができる。これにより、半田接合部を円柱状
もしくは鼓形状に形成でき、しかも接続間隔を長く保つ
ことができるので、温度サイクル等により生じるストレ
スによって半田接合部が損傷を受けるのを防止し、半導
体パッケージの寿命を大幅に向上させることができる。
As described above, according to the present invention, the spacing between the semiconductor package and the mounting substrate is forcibly set to a predetermined size, for example, by using the support pillar made of a shape memory alloy as a spacer. It can be kept at 0.1 mm or more and 2 mm or less. As a result, the solder joint can be formed in a columnar or drum shape, and the connection interval can be kept long, so that the solder joint is prevented from being damaged by stress caused by a temperature cycle or the like, and the life of the semiconductor package is reduced. Can be greatly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1(a)は実施形態例1の半導体パッケージ
の側面図であって、形状記憶合金の変態点以下の温度状
態での半導体パッケージの側面図、及び図1(b)は形
状記憶合金の変態点以上の温度状態での半導体パッケー
ジの側面図である。
1A is a side view of a semiconductor package according to a first embodiment, and FIG. 1B is a side view of the semiconductor package at a temperature lower than a transformation point of a shape memory alloy, and FIG. FIG. 4 is a side view of the semiconductor package in a temperature state equal to or higher than the transformation point of the memory alloy.

【図2】実施形態例1の半導体パッケージを実装基板上
に半田接合した時の半田接合部の形状を示す半導体パッ
ケージの側面図である。
FIG. 2 is a side view of the semiconductor package showing a shape of a solder joint when the semiconductor package of the first embodiment is solder-joined on a mounting board.

【図3】図3(a)は実施形態例2の半導体パッケージ
の側面図であって、形状記憶合金の変態点以下の温度状
態での半導体パッケージの側面図、及び図3(b)は形
状記憶合金の変態点以上の温度状態での半導体パッケー
ジの側面図である。
FIG. 3A is a side view of a semiconductor package according to a second embodiment, and FIG. 3B is a side view of the semiconductor package at a temperature lower than a transformation point of a shape memory alloy, and FIG. FIG. 4 is a side view of the semiconductor package in a temperature state equal to or higher than the transformation point of the memory alloy.

【図4】実施形態例2の半導体パッケージを実装基板上
に半田接合した時の半田接合部の形状を示す半導体パッ
ケージの側面図である。
FIG. 4 is a side view of the semiconductor package showing a shape of a solder joint when the semiconductor package of the second embodiment is solder-joined on a mounting board.

【図5】図5(a)は従来のBGA型半導体パッケージ
の側面図、及び図5(b)は図5(a)に示すBGA型
半導体パッケージを実装基板上に半田接合した時の半田
接合部の形状を示す半導体パッケージの側面図である。
5 (a) is a side view of a conventional BGA type semiconductor package, and FIG. 5 (b) is a solder joint when the BGA type semiconductor package shown in FIG. 5 (a) is soldered on a mounting substrate. It is a side view of the semiconductor package which shows the shape of a part.

【図6】図6(a)は従来のLGA型半導体パッケージ
の側面図、及び図6(b)は図6(a)に示すLGA型
半導体パッケージを実装基板上に半田接合した時の半田
接合部の形状を示す半導体パッケージの側面図である。
6 (a) is a side view of a conventional LGA type semiconductor package, and FIG. 6 (b) is a solder joint when the LGA type semiconductor package shown in FIG. 6 (a) is soldered on a mounting substrate. It is a side view of the semiconductor package which shows the shape of a part.

【図7】半田接合部の好ましい形状を示す模式図であ
る。
FIG. 7 is a schematic view showing a preferred shape of a solder joint.

【符号の説明】[Explanation of symbols]

10……従来のBGA型半導体パッケージ、12……イ
ンタポーザ基板、14……半導体チップ、16……下面
電極、18……半田ボール、20……電極パッド、22
……ボンディングワイヤ、24……印刷配線、26……
封止用樹脂、28……実装基板、32……電極、32…
…半田接合部、40……従来のLGA型半導体パッケー
ジ、42……下面電極兼半田ランド、44……半田接合
部、50……実施形態例1の半導体パッケージ、51…
…周縁部、52……支持柱、54……半田接合部、60
……実施形態例2の半導体パッケージ、62……支持
柱、64……空洞、66……半田接合部。
10: conventional BGA type semiconductor package, 12: interposer substrate, 14: semiconductor chip, 16: lower surface electrode, 18: solder ball, 20: electrode pad, 22
... bonding wire, 24 ... printed wiring, 26 ...
Sealing resin, 28 mounting board, 32 electrodes, 32
... Solder joint, 40 ... Conventional LGA type semiconductor package, 42 ... Bottom electrode and solder land, 44 ... Solder joint, 50 ... Semiconductor package of the first embodiment, 51 ...
... peripheral part, 52 ... support pillar, 54 ... solder joint part, 60
... The semiconductor package of the second embodiment, 62... A support column, 64... A cavity, 66.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半田接合により実装基板に実装する半導
体パッケージにおいて、 半導体パッケージの下面の対向する両周縁部に、それぞ
れ、形状記憶合金製の棒状の支持柱を備え、 支持柱は、変態点以上の温度では下面に沿って延在し、
形状記憶合金の変態点以上の温度では、半導体パッケー
ジの下面から下方に突起、延在することを特徴とする半
導体パッケージ。
1. A semiconductor package to be mounted on a mounting substrate by solder bonding, wherein two opposing peripheral edges of a lower surface of the semiconductor package are provided with rod-shaped support columns made of a shape memory alloy, respectively. At the temperature of extends along the lower surface,
A semiconductor package characterized by protruding downward from the lower surface of a semiconductor package at a temperature equal to or higher than the transformation point of the shape memory alloy.
【請求項2】 半田接合により実装基板に実装する半導
体パッケージにおいて、 半導体パッケージの下面の対向する両周縁部に、それぞ
れ、形状記憶合金製のコイルバネ状の支持柱を備え、 支持柱は、形状記憶合金の変態点以下の温度では、半導
体パッケージの下面から上方に収縮し、変態点以上の温
度では伸長して下面から下方に突起、延在することを特
徴とする半導体パッケージ。
2. A semiconductor package to be mounted on a mounting board by soldering, wherein two opposing peripheral edges of a lower surface of the semiconductor package are provided with support columns in the form of coil springs made of a shape memory alloy, respectively. A semiconductor package characterized in that it shrinks upward from the lower surface of the semiconductor package at a temperature lower than the transformation point of the alloy, and extends and protrudes downward from the lower surface at a temperature higher than the transformation point.
【請求項3】 半導体パッケージの下面から下方に延び
る支持柱の長さは、0.1mm以上2mm以下であることを
特徴とする請求項1又は2に記載の半導体パッケージ。
3. The semiconductor package according to claim 1, wherein a length of the support pillar extending downward from a lower surface of the semiconductor package is 0.1 mm or more and 2 mm or less.
【請求項4】 支持柱が、190℃以上250℃以下の
範囲の温度を変態点とする形状記憶合金で形成されてい
ることを特徴とする請求項1又は2に記載の半導体パッ
ケージ。
4. The semiconductor package according to claim 1, wherein the support column is formed of a shape memory alloy whose transformation point is in a temperature range of 190 ° C. or more and 250 ° C. or less.
【請求項5】 半導体パッケージがBGA(Ball Grid
Allay )半導体パッケージ又はLGA(Land Grid Alla
y )半導体パッケージであることを特徴とする請求項1
又は2に記載の半導体パッケージ。
5. The semiconductor package is a BGA (Ball Grid).
Allay) Semiconductor package or LGA (Land Grid Alla)
y) a semiconductor package;
Or the semiconductor package according to 2.
JP32246298A 1998-11-12 1998-11-12 Semiconductor package Pending JP2000150709A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32246298A JP2000150709A (en) 1998-11-12 1998-11-12 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32246298A JP2000150709A (en) 1998-11-12 1998-11-12 Semiconductor package

Publications (1)

Publication Number Publication Date
JP2000150709A true JP2000150709A (en) 2000-05-30

Family

ID=18143930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32246298A Pending JP2000150709A (en) 1998-11-12 1998-11-12 Semiconductor package

Country Status (1)

Country Link
JP (1) JP2000150709A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422344B1 (en) * 2001-05-10 2004-03-10 주식회사 하이닉스반도체 Package mounting apparatus
JP2008166411A (en) * 2006-12-27 2008-07-17 Fujitsu Ltd Mounting substrate, height adjustment device, and mounting method
JP2011029669A (en) * 2010-11-08 2011-02-10 Fujitsu Semiconductor Ltd Semiconductor device
KR20210054095A (en) * 2019-11-04 2021-05-13 세메스 주식회사 A processing chamber
KR102517935B1 (en) * 2022-04-15 2023-04-03 홍성민 Pcb exposure apparatus capable of double-sided exposure by closely keeping intervening pcb in close contact with transparent panel optically maintaining horizontal alignment

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422344B1 (en) * 2001-05-10 2004-03-10 주식회사 하이닉스반도체 Package mounting apparatus
JP2008166411A (en) * 2006-12-27 2008-07-17 Fujitsu Ltd Mounting substrate, height adjustment device, and mounting method
US7872875B2 (en) 2006-12-27 2011-01-18 Fujitsu Limited Mounting board, height adjusting apparatus and mounting method
JP2011029669A (en) * 2010-11-08 2011-02-10 Fujitsu Semiconductor Ltd Semiconductor device
KR20210054095A (en) * 2019-11-04 2021-05-13 세메스 주식회사 A processing chamber
KR102420343B1 (en) * 2019-11-04 2022-07-14 세메스 주식회사 A processing chamber
KR102517935B1 (en) * 2022-04-15 2023-04-03 홍성민 Pcb exposure apparatus capable of double-sided exposure by closely keeping intervening pcb in close contact with transparent panel optically maintaining horizontal alignment

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