JP2000150649A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a short circuit between adjoining wirings due to residue of etching in a gap part and eliminate connection failure between vertical wirings even if any gap is formed on an interlayer film because of dust and so on. SOLUTION: A contact layer and a metal layer on an interlayer insulation film 18 are etched back to form a metal plug 22p in a contact hole, and an upper wiring is formed on the metal plug. In this case, after etching back, the metal plug 22p in the contact hole is covered with a resist 23, and etching treatment is applied to remove the contact layer and metal layer left on the interlayer insulation film 18. After removal of the metal layer, the resist is also removed, and the upper wiring is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method of forming a metal plug that connects upper and lower wiring layers in a multilayer wiring structure, and particularly to a process of forming a metal plug by etching back a metal film for forming a plug, the etching back residue of the metal film is reduced. The present invention relates to an improved method for preventing a short circuit between adjacent wiring patterns due to the above and for forming a good contact between upper and lower wirings.

[0002]

2. Description of the Related Art In recent years, design rules for semiconductor devices have been greatly reduced, and the research level has been reduced from sub-half microns to quarter microns or more. However, this relates to the dimensions of the semiconductor device in the horizontal plane (plane parallel to the substrate),
The size reduction in the vertical direction (cross-sectional direction of the substrate) does not proceed at the same pace as the horizontal plane because it is necessary to reduce wiring resistance and parasitic capacitance. In addition, the use of the multilayer wiring structure tends to increase the level difference on the surface of the substrate.

On the other hand, such an increase in the surface step of the substrate is a disadvantageous condition for the recent photolithography technology in which the depth of focus and the contrast have been seriously reduced with the shortening of the exposure light wavelength and the monochromatic light. It is.

[0004] From such a background, planarization of an interlayer insulating film is increasing in importance as a technique for absorbing a surface step of a substrate and improving the accuracy of photolithography. However, since a region having a large thickness locally occurs in the planarized interlayer insulating film, the aspect ratio of a fine contact hole opened in this film is necessarily increased.

Conventionally, a wiring film covering a contact hole has been formed mainly by depositing an aluminum (Al) -based metal material film by a sputtering method. However, when the aspect ratio of the contact hole is about 3 or more, the step coverage (step coverage) is insufficient by the sputtering method, and a contact failure between the upper wiring and the lower wiring occurs.

Therefore, as a technique capable of overcoming the step coverage problem, a so-called metal plug technique has been developed in which a contact plug is formed by filling the inside of a contact hole with a metal film. The electric resistance of the metal plug portion increases as the aspect ratio of the contact hole increases, and the amount of heat generated when a large current flows increases. Therefore, a low-resistance high-melting metal material is generally used as the metal film. Have been.

At present, the most widely adopted method in such a metal plug forming process is a combination of a blanket CVD method and an etch back. this is,
First, a refractory metal film (blanket metal film) is deposited on the entire surface so that the contact hole is completely buried and the surface of the interlayer insulating film is completely covered. This is a method of anisotropically vertically etching back until the surface of the film is exposed. In this case, tungsten (W) is most commonly used as a high melting point metal material for forming a plug.

[0008]

However, the etch-back in the above-described conventional metal plug forming process has a problem in determining the end point. In particular, when a step occurs on the surface of the interlayer insulating film due to some factor, the blanket metal film remains as an etch-back residue on the periphery of the step, and this residue is formed by connecting to the metal plug. Adjacent wiring patterns may be short-circuited. This problem will be further described with reference to FIGS. 8 to 13 showing a conventional metal plug forming process.

FIG. 8 shows a state where a surface step is generated due to dust adhesion on the interlayer insulating film. Briefly describing the process up to the state shown in FIG. 8, first, silicon (S
i) A field oxide film 2 for element isolation is formed on a substrate 1 and, for example, a gate oxide film and a gate electrode of a MOS transistor (not shown) are formed in an active region defined by the field oxide film 2, and then ion implantation is performed. Then, the impurity diffusion layer 3 is formed. An interlayer insulating layer made of a SiOx-based material is formed on the entire surface of the substrate (including the Si substrate itself, the active region formed thereon, and various films sequentially laminated thereafter (same in the following description)) on which such an active region is formed. Membrane 4
Is deposited and planarized. Thereafter, the interlayer insulating film 4 is patterned to open a contact hole 5 facing the impurity diffusion layer 3. At this point, the insulating dust 6 has adhered to the surface of the interlayer insulating film 4. The dust 6 is generated, for example, when the SiOx film deposited on the core tube wall of the CVD reactor during the formation of the interlayer insulating film 4 is peeled off.

Next, as shown in FIG. 9, a blanket tungsten (W) film 7 is formed so as to fill the contact hole 5 and sufficiently cover the surface of the interlayer insulating film 4. Although not shown, a thin Ti film and a TiN film are provided below the actual blanket W film 7 in order to improve adhesion to the interlayer insulating film 4 and reduce a natural oxide film on the surface of the Si substrate 1. Are laminated in this order to form a Ti-based adhesion layer.

Next, this blanket W film 7 is etched back by anisotropic etching, and a W metal plug 7 is formed inside the contact hole 5 as shown in FIG.
Form p. At this time, an etch-back residue 7r of the blanket W film remains on the periphery of the dust 6 on the interlayer insulating film 4. Thereafter, a first upper wiring 8 made of, for example, Al-Si is patterned by covering the metal plug 7p in the contact hole 5 and formed.

Here, FIG. 10A is a cross-sectional view of the substrate in the contact hole portion after the above-mentioned etch back, and FIG. 10B is a top view thereof. FIG. 10 (A)
As shown in (B), the etch-back residue 7r short-circuits two adjacent upper wirings 8. In the vicinity of the contact hole 5, the width of the wiring pattern is generally large and the interval between the patterns is narrowed in view of the margin for the misalignment of the upper and lower patterns in the photolithography.

In order to eliminate the etch-back residue 7r, when forming the metal plug 7p, it is conceivable to perform an excessive over-etch as shown in FIG. However, the metal plug 7p is also etched by such an excessive overetch, and a step (plug loss) from the opening end of the contact hole 5 increases. In this state where the step is large, the contact hole 5
When the upper wiring 8 is formed so as to cover the metal plug 7p in the inside, a deep recess 8a is formed corresponding to the step as shown in FIG.

The deep recess 8a of the upper wiring 8 has
This causes a connection failure of the second upper layer wiring 14 in the upper layer to the first upper layer wiring 8. That is, as shown in FIG. 13, an interlayer insulating film 11 is formed so as to cover the entire surface of the substrate including the interlayer insulating film 4 and the first upper wiring 8, and thereafter,
When a via hole 12 is opened in the interlayer insulating film 11, the interlayer insulating film 11 tends to remain in the recess 8a of the upper wiring 8. If an attempt is made to remove the remaining film of the interlayer insulating film in the recess 8a by over-etching, the upper wiring 8 of Al-Si is likely to disappear under the dry etching condition of the interlayer insulating film which originally uses a large ion incident energy. Therefore, it is difficult to remove the remaining film. As described above, the second metal plug 13 made of W is buried in the via hole 12 in which the residual film exists, and the second metal plug 13 is formed thereon.
When the upper wiring 14 is formed, an electrical connection failure occurs between the first upper wiring 8 and the second upper wiring 14 due to the remaining film.

As described above, in the process of forming a metal plug using a blanket W film, adjacent wirings formed in the same layer due to the etch back residue on the peripheral edge of the step formed on the interlayer insulating film due to dust or the like. May be short-circuited, and if the etch-back is performed excessively to remove the residue, there is a problem that the upper and lower wirings may have a poor connection.

The present invention has been made in view of the above-mentioned conventional technology, and even if a step is formed on an interlayer insulating film by dust or the like, short-circuiting between adjacent wirings due to an etching residue at the step is caused. It is an object of the present invention to provide a method of manufacturing a semiconductor device which prevents the occurrence of a connection failure between upper and lower wirings.

[0017]

In order to achieve the above object, according to the present invention, an interlayer insulating film is formed on an underlying lower wiring, a contact hole is formed in the interlayer insulating film, and an inner surface of the contact hole is formed. Forming an adhesive layer on the interlayer insulating film, including forming a metal layer on the adhesive layer, filling the contact hole with the metal layer, and etching back the adhesive layer and the metal layer on the interlayer insulating film. Forming a metal plug in the contact hole and forming an upper layer wiring on the metal plug, the metal plug in the contact hole is covered with a resist and remains on the interlayer insulating film after the etch back. After performing an etching process for removing the residue of the adhesion layer and the metal layer, and removing the residue of the metal layer, the resist is removed. To provide a semiconductor device manufacturing method characterized by forming the serial upper wiring.

According to this structure, in the process of forming the metal plug in the contact hole by etching back the adhesion layer and the metal layer, a resist pattern is formed by covering the metal plug in the contact hole after the etch back. By performing the etching process using the mask, the contact hole can be protected from the etching, and the etch-back residue of another portion can be removed. This can prevent a short circuit between adjacent wirings due to the etch-back residue.

In this case, since the contact hole portion is protected by the resist, it is not etched, so that the surface of the metal plug is not removed, and the step from the peripheral portion of the contact hole does not increase. In addition, since the contact hole is covered with the resist and the metal residue can be removed by etching as described above, it is not necessary to perform an excessive over-etch for removing the residue, and the film loss due to the etching of the metal plug surface is prevented. be able to. As a result, the buried state of the metal plug becomes almost flat, and the surface of the upper wiring formed by covering this metal plug becomes almost flat, and no recess is formed. Therefore, when the via hole facing the upper wiring is formed in the interlayer insulating film, the etching residue of the interlayer insulating film does not remain on the bottom surface of the via hole, and a poor connection between the upper and lower wirings is prevented to achieve a good contact. Can be.

The etch-back residue mainly remains on the periphery of the step formed by dust or the like adhering to the surface of the interlayer insulating film. The dust adheres after the completion of the formation of the interlayer insulating film. There is a case where it adheres to the surface or a case where it adheres during the formation of the interlayer insulating film and is embedded in the interlayer insulating film. In any case, an etch-back residue is caused, but the residue can be completely removed by the method of the present invention.

Examples of the material which forms the main part of the metal film for forming the metal plug include titanium (Ti), cobalt (Co), molybdenum (Mo), tantalum (Ta), tungsten (W), platinum (Pt) and the like. Is raised. Before forming the metal plug, the inside of the contact hole is generally covered with a barrier metal or an adhesion layer. However, the present invention can be applied to the metal film for plug formation as well as the barrier metal or the adhesion layer.

As a metal material which is a main component of the upper wiring,
Examples include aluminum (Al) and copper (Cu). When forming the upper wiring, an adhesion layer may be formed on the base side, or an antireflection film may be laminated on the surface, but the upper wiring of the present invention includes these adhesion layers and the antireflection film. I do.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 7 are diagrams sequentially illustrating each step of the method of manufacturing a semiconductor device according to the present invention, wherein (A) is a longitudinal sectional view of a contact hole portion of a substrate, and (B) is a top view thereof. is there.

FIG. 1 shows a state where a surface step is generated due to dust adhesion on an interlayer insulating film. Briefly describing the process up to the state of FIG. 1, first, silicon (S
i) A field oxide film 16 for element isolation is formed on the substrate 15 by, for example, a known LOCOS method, and a gate oxide film and a gate electrode of a MOS transistor (not shown) are formed in an active region defined by the field oxide film 16. After that, ion implantation is performed to form the impurity diffusion layer 17. This impurity diffusion layer 17 is, for example, a source / drain region of a MOS transistor having an LDD structure.

On the entire surface of the substrate on which such an active region is formed, an interlayer insulating film 18 made of, for example, a BPSG (boron phosphorus silicate glass) film is formed to a thickness of about 600 nm in this embodiment.
This was planarized by depositing to a thickness of m. Then, the interlayer insulating film 18 is patterned to form the impurity diffusion layer 17.
In the embodiment, a contact hole 19 having a diameter of about 0.4 μm was opened. The aspect ratio of the contact hole 19 is about 1.5. At this point, the interlayer insulating film 18
Has a height of about 3 due to the insulating dust 20.
There was a step of 00 nm. The dust 20 is, for example, the BPSG film deposited on the core tube wall of the CVD reactor during the formation of the interlayer insulating film 18, and is dropped onto the substrate.

Next, as shown in FIG. 2, a Ti film having a thickness of about 30 nm is formed on the entire surface of the substrate including the inner surface of the contact hole 19.
A film and a TiN film having a thickness of about 70 nm were sequentially formed by a sputtering method to form an adhesion layer 21. Ti of the adhesion layer 21
The film serves to reduce the contact resistance by reducing the natural oxide film on the surface of the Si substrate 15, and the TiN film serves as a blanket tungsten (W) film 2
It is provided to improve the adhesion to the second interlayer insulating film 18. Thereafter, for example, by an LPCVD method using a WF6 / H2 mixed gas, as shown in FIG.
A blanket W film 22 having a thickness of about 600 nm was formed on the entire surface of the substrate.

Next, as shown in FIG. 3, the adhesive layer 21 composed of the blanket W film 22 and the Ti / TiN laminated film is anisotropically etched back by RIE (reactive ion etching). A metal plug 22p made of W was formed inside. This etch back
For example, by etching back using SF ₆ / Ar based gas, etching is stopped at the adhesion layer 21 of the Ti / TiN laminated film, and the amount of retreat of the surface of the metal plug 22p from the end face of the opening of the contact hole 19 becomes almost zero. I do.
At this time, an etch-back residue 22r remains on the peripheral portion of the dust 20 on the interlayer insulating film 18.

Next, as shown in FIG. 4, a resist 23 is formed so as to cover the metal plug 22p of the contact hole 19.
Is patterned and etched anisotropically by RIE.
For example, the etch-back residue 22r at the peripheral portion of the dust 20 is removed using an SF ₆ / Ar-based gas. Subsequently, for example, the adhesion layer 21 is etched by switching to a Cl / Ar-based gas. At this stage, the etch-back residue 22r on the periphery of the dust 20 is completely removed.

Next, as shown in FIG. 5, a first upper wiring layer 24 made of an Al / Si film having a thickness of about 500 nm was formed on the entire surface of the substrate by sputtering. In the present invention, as described above, the etch-back process is performed so that the metal plug 22p does not recede from the opening end face of the contact hole 19, so that the surface of the upper wiring layer 24 is substantially above the contact hole 19. It was flat and did not have a deep recess as in the prior art. Note that this Al / S
Under the upper wiring layer 24 made of an i-film, an interlayer insulating film 1 is formed.
A thin TiN film may be interposed in order to secure the adhesion to the substrate 8, and the surface thereof may be, for example, a TiN film or a TN film.
An anti-reflection film made of an iW film may be formed.

A resist pattern 25 was formed on the upper wiring layer 24. In this state, for example, BCl ₃ /
The upper wiring layer 24 was anisotropically etched by performing RIE using a normal chlorine-based gas such as a Cl ₂ -based gas to form an upper wiring pattern 24p as shown in FIG.

Thereafter, a second upper wiring was further formed on the upper wiring pattern 24p according to a conventional method. That is, as shown in FIG. 7, first, the entire surface of the substrate in the state of FIG. 6 is covered with an interlayer insulating film 26 made of, for example, a BPSG film, and is subjected to resist patterning and dry etching to form a via hole facing the first wiring pattern 24p. 27 was opened. At this time, the underlying wiring pattern 24p
Is substantially flat, the wiring pattern 24p can be entirely exposed on the bottom surface of the via hole 27 without performing excessive over-etching.

Next, the via hole 27 was filled with a metal plug 28 made of W. This metal plug 28 was formed by a combination of the entire blanket W film deposition by LPCVD and anisotropic etch-back, as in the case of the lower metal plug 22p described above.

Thereafter, a second upper wiring pattern 29 made of Al / Si connected to the metal plug 28 is formed.
Was formed. The method of forming the wiring pattern 29 is similar to that of the first upper wiring pattern 24p described above.
This was performed by deposition of the entire surface of the film and patterning thereof.

In the semiconductor device formed in this manner, a short circuit between adjacent wiring patterns 24p caused by the etch-back residue 22r as in the related art and an interlayer insulating film remaining in a concave portion on the surface of the wiring pattern 24p are formed. The problem of poor connection between the upper and lower wiring patterns 24p and 29 due to the problem has been solved.

Note that the present invention is not limited to the numerical values and embodiments of the above examples, and the design rules, materials used, substrate structure, film forming conditions, and each process condition such as dry etching, etch back, and plasma processing may be appropriately changed. Changes and selections are possible.

[0036]

As described above, according to the present invention,
Even if the etch-back residue of the metal film for forming the metal plug remains on the interlayer insulating film, the resist layer covering the contact hole portion is formed and etched without excessive over-etching, thereby forming the same layer. A short circuit between wiring patterns in the inside and a connection failure between wiring patterns of upper and lower wiring layers can be prevented very effectively. Thereby, the reliability of the wiring structure is improved, the yield is improved, and it is possible to contribute to miniaturization and high integration of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a structural explanatory view of a state in the middle of a semiconductor manufacturing method according to the present invention.

FIG. 2 is a structural explanatory view of a stage following the stage of FIG. 1;

FIG. 3 is a structural explanatory view of a stage following the stage of FIG. 2;

FIG. 4 is a structural explanatory view of a stage following the stage of FIG. 3;

FIG. 5 is a structural explanatory view of a step that follows the step of FIG. 4;

FIG. 6 is a structural explanatory view of a step that follows the step of FIG. 5;

FIG. 7 is a structural explanatory view of a step that follows the step of FIG. 6;

FIG. 8 is a sectional view of a state in the middle of a conventional semiconductor manufacturing method.

FIG. 9 is a sectional view of a step that follows the step of FIG. 8;

FIG. 10 is a structural explanatory view of a stage following the stage of FIG. 9;

11 is a sectional view of a step that follows the step of FIG. 10;

FIG. 12 is a sectional view of a step that follows the step of FIG. 11;

FIG. 13 is a sectional view of a step that follows the step of FIG. 12;

[Explanation of symbols]

15: Si substrate, 16: field oxide film, 17: impurity diffusion layer, 18, 26: interlayer insulating film, 19: contact hole, 20: dust, 21: adhesion layer, 22: blanket tungsten film, 22p, 28: metal Plug, 2
3: resist, 24: upper wiring layer, 24p, 29: wiring pattern, 25: resist pattern, 27: via hole.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 4M104 BB14 BB36 FF13 FF22 HH12 5F004 AA09 AA16 BA11 DA00 DA18 DA23 DB08 DB10 EA27 EA28 EB01 EB08 5F033 HH09 HH23 HH33 JJ18 JJ19 JJ33 KK01 KK09 KK09 KK09 KK09 KK09 KK09 QQ08 QQ09 QQ13 QQ16 QQ24 QQ31 QQ37 QQ91 RR15 XX01 XX21 XX31

Claims (3)

[Claims] An interlayer insulating film is formed on a lower wiring layer on a base side, a contact hole is formed in the interlayer insulating film, and an adhesion layer is formed on the interlayer insulating film including an inner surface of the contact hole. Forming a metal layer on the adhesion layer and filling the contact hole with the metal layer; etching back the adhesion layer and the metal layer on the interlayer insulating film to form a metal plug in the contact hole; In the method for manufacturing a semiconductor device, an upper layer wiring is formed, after the etching back, an etching process for covering a metal plug of the contact hole with a resist and removing a residue of the adhesion layer and the metal layer remaining on the interlayer insulating film. And removing the residue of the metal layer, and then removing the resist to form the upper wiring. Production method. 2. The method according to claim 1, wherein said etch back is performed while leaving at least a part of said adhesion layer on said interlayer insulating film. 3. An interlayer insulating film is further formed on the upper wiring, a metal plug is formed in the interlayer insulating film, and a second upper wiring connected to the upper wiring via the metal plug is formed. The method for manufacturing a semiconductor device according to claim 1, wherein: