JP2000147463A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a uniform and highly fine picture quality in which deviations of dots and color slippages or the like are not generated on a screen by arranging respective terminals of clock lines, video lines and power lines at the side of one side of a display device to prevent deviations from being generated in timings when video signals are written on signal lines. SOLUTION: Respective terminals of clock lines 12 to 15, power lines 16, 17 and video lines 18 to 20 are arranged so as to exist at the side of one side of the device. Consequently, deviations are not generated in timings when video signals V1 to V3 are written on signal lines X1, X2, X3, X4,.... Then, the power lines 16 and 17 are arranged between the clock lines 12 to 15 and the video lines 18 to 20. Moreover, supplies of these power lines 16, 17 are performed from the same B direction as a first noise conter-measure. Furthermore, clock lines 12 and 13, 15 and 16 are made to be crossed each other respectively as a second noise countermeasure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a built-in driver circuit for driving a signal line.

[0002]

2. Description of the Related Art As a conventional liquid crystal display base having a built-in driver circuit for driving signal lines, "SID" 84 digest p. 316-319 ". FIG. 2 shows the circuit configuration of this device. Signal lines X1, X2, X
Are arranged in the column direction, and a plurality of scanning lines Y1, Y2, Y3,... Are arranged in the row direction. At intersections between the signal lines X and the scanning lines Y, thin film transistors (hereinafter, referred to as TFTs) 22 are arranged in a matrix. TFT
The gate of 22 is connected to the scanning line Y, the source is connected to the signal line X, and the drain is connected to the pixel electrode 23. Also,
The common potential _VCOM is completely applied to the counter electrode 24.

Each signal line X inputs video signals V1 to V3 to the TFT 22, and is driven by an X driver 30. Each scanning line Y is for inputting a selection pulse signal to the gate of the TFT 22 and selectively conducting, and is driven by a Y driver 21.

Here, the X driver 30 comprises a shift register 11 and analog switches TFTSW1, SW2, SW.
3, SW4,... The shift register 11 has a power supply line 3 for supplying power supply voltages VDDX and VSSX.
5 and 36 are connected. Also, the start pulse D
A start pulse line 37 for inputting X is connected. Further, clock lines 31 to 34 are connected, and clock pulses CL1, CL1, CL2 and CL2 are connected.
Are respectively input. The output lines 38 to 41 are respectively connected to the gates of the analog switches TFTSW1 to SW4, and the video lines 18 to 20 for transmitting the video signals V1 to V3 are connected to the analog switches TFTSW1 to SW4.
Connected to the source of W4.

[0005] By the X driver 30, each signal line X
Video signals Vl to V3 are sequentially written to 1, X2, X3, ... as follows. FIG. 3 shows the operation waveform of each signal in this case. Clock pulse CL1, CL1, CL
2 and CL2 are inputted, and clock pulses CL1 and CL2 are inputted.
The start pulse DX is sequentially shifted by the phase difference T from the output signal Q2, and the output lines 38 to 41 are output as output signals Ql to Q4.
Given to. This output is the analog switch TFTS
The signals are input to the gates of Wl to SW4, respectively, and are turned on during the high level.

The analog switches TFTSW1-SW
4 is input while the video signals V1 to V3 are conducting, and written to the signal lines X1 to X3.

[0007]

Here, conventionally, the noise of the clock lines 31 to 34 is reduced by the video lines 18 to 20.
Clock pulses CLl, CLl, C
L2 and CL2 are input from the direction A, and the video signals Vl to V
No. 3 was input from the opposite B direction. However, each signal line X
The timing at which the video signals V1 to V3 are written to 1, X2, X3,...

When a clock pulse is input to the shift register 11 from the direction A, the edge is sharp near the entrance of the signal (right side in the figure), and the edge is near the exit (left side in the figure). However, since the video signals Vl to V3 are input from the opposite direction B, the waveforms of the shift register 11 become smoother from the left side to the right side in the figure. When the waveform of the clock pulse becomes blunt, the analog switch TFTS
Although the timing at which Wl to SW4 conducts is delayed, the waveforms of the video signals Vl to V3 become the same, and there is no particular problem if the timing at which the signals can be completely input to the analog switches TFT SWl to SW4 is delayed.

However, the input directions of the clock pulse and the video signal do not match, and the analog switch TFTSW
1 to SW4 are turned on based on the clock pulse, and the video signals V1 to V3 are analog switch TFTs.
A shift occurs in the timing of input to SW1 to SW4. As a result, there has been a problem that dots are shifted when data is displayed on a screen, and colors are shifted when images of a plurality of liquid crystal display panels are combined like a liquid crystal projector.

The present invention has been made in view of the above circumstances,
It is an object of the present invention to achieve uniform and high-definition image quality without deviation in timing for writing a video signal to a signal line.

[0011]

According to the liquid crystal display device of the present invention, a plurality of scanning lines and signal lines are arranged on a first insulating substrate, and a TFT is scanned by the scanning lines and a signal is inputted by the signal lines. Are arranged in a matrix at the intersections of the scanning lines and the signal lines, and are provided so as to face the first insulating substrate, and the liquid crystal is sandwiched between the second insulating substrate and the counter electrode. A driver circuit for driving a signal line, a clock line connected to the driver circuit and supplying a clock pulse, and a video line connected to the driver circuit and supplying a video signal are arranged on the first insulating substrate. This is characterized in that the direction in which the clock line supplies the clock pulse coincides with the direction in which the video line supplies the video signal.

Here, a power supply line for supplying power to the driver circuit may be arranged while the clock line and the video line are arranged.

The phase of the clock line is 180.
There may be at least two clock lines that respectively supply two clock pulses that are staggered, and each clock line may intersect at least one point.

(Operation) When a clock pulse is supplied to the driver circuit, the waveform of the clock pulse gradually decreases from the input side to the output side of the clock line, so that the timing at which the TFT conducts is delayed. However, since the direction in which the video signal is supplied coincides with the direction in which the clock pulse is supplied, the waveform of the video signal gradually decreases in the same direction, and there is no shift in the timing of writing the video signal to the signal line. .

When the clock pulse and the video signal are supplied from the same direction, noise of the clock line may enter the video line. However, the power line is disposed between the clock line and the video line. Is prevented.

Parasitic capacitance exists in each line connecting each clock line to the driver circuit, and coupling noise occurs when the clock pulse is inverted. However, the clock lines cross at least one point. As a result, the distance from the clock line to the driver circuit becomes equal, and coupling noises having different polarities are generated and canceled at the same timing, thereby reducing the noise.

[0017]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the liquid crystal display device according to the present embodiment. The arrangement of the clock lines 12 to 15 and the power supply lines 16 and 17 is different from that of the conventional device shown in FIG. The clock lines 31 to 34 are arranged such that the clock pulses CL1, CL1, CL2, and CL2 are input to the shift register 11 in the same B direction as the video signals V1 to V3. As a result, the waveform of the clock pulse gradually decreases as going to the left in the figure, and even if the timing at which the analog switches TFTSW1 to SW4 become conductive is delayed, the video signals V1 to V3
The waveforms of the above also turn in the same direction. Therefore, the signal line X
There is no shift in the timing at which the video signals V1 to V3 are written to 1, X2, X3, X4,. In particular, when the time constants of the clock lines 12 to 15 and the video lines 18 to 20 are substantially the same, the timing can be almost completely matched.

When these two signals are input from the same direction, noise on the clock lines 12 to 15 may enter the video lines 18 to 20. Therefore, in this embodiment, noise suppression is performed by providing the following wiring.

First, power supply lines 16 and 17 are arranged between clock lines 12 to 15 and video lines 18 to 20 as a first noise countermeasure. The power supply lines 16 and 17 are also supplied from the same direction B, so that a power supply line is arranged between the clock line and the video line even in a path wired from the outside to the liquid crystal display device. .

As a second noise countermeasure, the clock lines 12 and 13, 14 and 15 are crossed respectively. This is for the following reasons. Clock line 12
To 15 and the shift register 11 are connected to lines 51 to 54,
55-58,... This line 51
, 54, 55, 58,... Each have a parasitic capacitance, which generates coupling noise when the clock is inverted. In order to cancel this noise, noise may be generated at the same timing between the clock pulses CL1 and CL1, and the clock pulses CL2 and CL2, whose polarities are opposite and whose phases are shifted by 180 degrees.

For this reason, the clock lines 12 and 13 cross each other, and the clock lines 14 and 15 cross each other. Thus, the line 51 connected to the clock line 12 and the line 56 connected to the clock line 13,
The lengths of the line 55 connected to the clock line 12 and the line 52 connected to the clock line 13 are the same. Similarly, the line 53 connected to the clock line 14 and the line 5 connected to the clock line 15
8. The lengths of the line 57 connected to the clock line 14 and the line 54 connected to the clock line 15 are the same. As a result, noise generated when the polarity of each clock pulse is inverted is cancelled.

By taking such two noise countermeasures, the clock lines 12 to 20 are connected to the video lines 18 to 20.
To 15 signal lines X1 and X
2, X3, X4,... Can be written at appropriate timing.

The above-described embodiment is an example and does not limit the present invention. For example, the clock pulse and the video signal may be supplied to the X driver from the same direction,
It is not always necessary to take noise countermeasures as in the embodiment. Further, other noise countermeasures may be taken.

[0024]

As described above, in the liquid crystal display device according to the present invention, the direction in which the clock pulse is supplied to the driver circuit for driving the signal line and the direction in which the video signal is supplied coincide with each other. Similarly, even if the waveform of the clock pulse in gradually shifts, the waveform of the video signal to be written to the signal line also shifts in the same direction. Therefore, uniform and high-definition image quality can be realized without causing dot shift or color shift on the screen.

[Brief description of the drawings]

FIG. 1 is a wiring diagram illustrating a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a wiring diagram showing a configuration of a conventional liquid crystal display device.

FIG. 3 is a timing chart showing waveforms of a clock pulse and a video signal which can be used in the liquid crystal display device of the present invention.

[Explanation of symbols]

 11 shift register 12-15 clock line 16, 17 power supply line 18-20 video line SWl-SW4 analog switch TFT X1-X4 signal line Yl-Y3 scanning line 10 X driver 21 Y driver 22 ... TFT 23 ... Pixel electrode 24 ... Counter electrode CL1, CL1, CL2, CL2 ... Clock pulse V1 to V3 ... Video signal

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[Procedure amendment]

[Submission Date] January 26, 2000 (2000.1.2
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

[Title of the Invention] Display device

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device having a built-in driver circuit for driving a signal line.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011] A display device according to the present invention includes transistors arranged in a matrix on a substrate, a signal line connected to the transistor, a driver circuit for driving the signal line, and a clock pulse connected to the driver circuit. A video line connected to the driver circuit and supplying a signal to the signal line, and a power supply line, and the respective terminals of the clock line, the video line, and the power supply line are arranged on one side. It is characterized by having been done. The display device according to the present invention is characterized in that a terminal of the power supply line is arranged between a terminal of the clock line and a terminal of the video line.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Deleted

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Deleted

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Deleted

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Deleted

Claims (3)

[Claims] A plurality of scanning lines and signal lines are arranged on a first insulating substrate, and a thin film transistor scanned by the scanning lines and inputted with a signal by the signal lines is connected to the scanning lines and the signal lines. In a liquid crystal display device in which a liquid crystal is interposed between a second insulating substrate, which is disposed in a matrix at intersections, is provided to face the first insulating substrate, and has a counter electrode disposed thereon, A driver circuit for driving the signal line, a clock line connected to the driver circuit and supplying a clock pulse, and a video line connected to the driver circuit and supplying a video signal are arranged on the substrate; A liquid crystal display device, wherein a direction in which a clock line supplies a clock pulse coincides with a direction in which the video line supplies a video signal. 2. The liquid crystal display device according to claim 1, wherein a power supply line for supplying power to said driver circuit is arranged between said clock line and said video line. 3. A clock line having a phase of 180.
3. The liquid crystal display device according to claim 1, further comprising at least two clock lines for respectively supplying two clock pulses shifted from each other, wherein each of the clock lines intersects at least one point.